New L J Institute of Engineering and Technology Semester: IV (2024)

NEW L J INSTITUTE OF ENGINEERING &

TECHNOLOGY

SEMESTER- 4

BRANCH- CSE

SUBJECT NAME: COMPUTER ORGANIZATION AND

ARCHITECTURE

UNIT: 1 Computer Data Representation

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UNIT 1: INTRODUCTION
Number System:
It is a basis for counting various items.
The digit value in the number system is calculated using:
 The digit
 The index, where the digit is present in the number.
 Finally, the base numbers, the total number of digits available in the number system.
Classification:
1. Binary Number System
2. Decimal Number System
3. Hexadecimal Number System
4. Octal Number System

What is a Digital Computer System?

A Digital computer can be considered as a digital system that performs various
computational tasks.
By convention, the digital computers use the binary number system, which has two digits:
0 and 1. A binary digit is called a bit.
A computer system is subdivided into two functional entities: Hardware and Software.
The hardware consists of all the electronic components and electromechanical devices that
comprise the physical entity of the device.
The software of the computer consists of the instructions and data that the computer
manipulates to perform various data-processing tasks.
Block Diagram of a Digital Computer:

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Computer Architecture.
It deals with the conceptual design and fundamental operational structure of the computer.
It consists of:
 CPU designing
 Set of instructions CPU supports
 Addressing modes
 Data Format

Define Computer Organization.

It deals with the implementation of architecture, physical devices and their interconnections
with the perspective of improving the performance.

Question. Difference between architecture and organization.

Basic Computer Data Types:

Conversions
1. Binary to Decimal Number System
2. Decimal to Binary Number System
3. Octal to Binary Number System
4. Binary to Octal Number System
5. Binary to Hexadecimal Number System
6. Hexadecimal to Binary Number System

Binary to Decimal Conversion

Example 1: (10110.001)2
We multiplied each bit of (10110.001)2 with its respective positional weight, and last we
add the products of all the bits with its
4 3 2 1 0 -1 -2 -3
weight.(10110.001)2=(1×2 )+(0×2 )+(1×2 )+(1×2 )+(0×2 )+(0×2 )+(0×2 )+(1×2 )
(10110.001)2=(1×16)+(0×8)+(1×4)+(1×2)+(0×1)+(0×1⁄2)+(0×1⁄4)+(1×1⁄8)
(10110.001)2=16+0+4+2+0+0+0+0.125
(10110.001)2=(22.125 )10

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Binary to Octal Conversion

Example 1: (111110101011.0011)2
1. Firstly, we make pairs of three bits on both sides of the binary point.
111 110 101 011.001 1
On the right side of the binary point, the last pair has only one bit. To make it a complete
pair of three bits, we added two zeros on the extreme side.
111 110 101 011.001 100
2. Then, we wrote the octal digits, which correspond to each pair.
(111110101011.0011)2=(7653.14)8

Binary to Hexadecimal Conversion

Example 1: (10110101011.0011)2
1. Firstly, we make pairs of four bits on both sides of the binary point.
111 1010 1011.0011
On the left side of the binary point, the first pair has three bits. To make it a complete pair
of four bits, add one zero on the extreme side.
0111 1010 1011.0011
2. Then, we write the hexadecimal digits, which correspond to each pair.
(011110101011.0011)2=(7AB.3)16

Decimal to other Number System

Example 1: (152.25)10

(152)10=(10011000)2

(0.25)10=(.01)2

Octal to Decimal Number System

Example 1: (152.25)8
(152.25)8=(1×82)+(5×81)+(2×80)+(2×8-1)+(5×8-2)
(152.25)8=64+40+2+(2×1⁄8)+(5×1⁄64)
(152.25)8=64+40+2+0.25+0.078125
(152.25)8=106.328125
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So, the decimal number of the octal number 152.25 is 106.328125

Octal to Binary Conversion

Example 1: (152.25)8
(152.25)8=(001101010.010101)2
So, the binary number of the octal number 152.25 is (001101010.010101)2

Octal to hexadecimal conversion

Example 1: (152.25)8
Step 1:
We write the three-bit binary digit for 1, 5, 2, and 5.
(152.25)8=(001101010.010101)2
So, the binary number of the octal number 152.25 is (001101010.010101)2
Step 2:
1. Now, we make pairs of four bits on both sides of the binary point.
0 0110 1010.0101 01
On the left side of the binary point, the first pair has only one digit, and on the right side,
the last pair has only two-digit. To make them complete pairs of four bits, add zeros on
extreme sides.
0000 0110 1010.0101 0100
2. Now, we write the hexadecimal digits, which correspond to each pair.
(0000 0110 1010.0101 0100)2=(6A.54)16

Hexa-decimal to Decimal Conversion

Example 1: (152A.25)16
Step 1:
We multiply each digit of 152A.25 with its respective positional weight, and last we add the
products of all the bits with its weight.
(152A.25)16=(1×163)+(5×162)+(2×161)+(A×160)+(2×16-1)+(5×16-2)
(152A.25)16=(1×4096)+(5×256)+(2×16)+(10×1)+(2×16-1)+(5×16-2)
(152A.25)16=4096+1280+32+10+(2×1⁄16)+(5×1⁄256)
(152A.25)16=5418+0.125+0.125
(152A.25)16=5418.14453125
So, the decimal number of the hexadecimal number 152A.25 is 5418.14453125

Hexadecimal to Binary Conversion

Example 1: (152A.25)16
We write the four-bit binary digit for 1, 5, A, 2, and 5.
(152A.25)16= (0001 0101 0010 1010.0010 0101)2
So, the binary number of the hexadecimal number 152.25 is (1010100101010.00100101)2

Hexadecimal to Octal Conversion

Example 1: (152A.25)16
Step 1:
We write the four-bit binary digit for 1, 5, 2, A, and 5.
(152A.25)16=(0001 0101 0010 1010.0010 0101)2
So, the binary number of hexadecimal number 152A.25 is (0011010101010.010101)2
Step 2:
3. Then, we make pairs of three bits on both sides of the binary point.
001 010 100 101 010.001 001 010

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4. Then, we write the octal digit, which corresponds to each pair.

(001010100101010.001001010)2=(12452.112)8
So, the octal number of the hexadecimal number 152A.25 is 12452.112

Various Codes in Binary System:

1. Gray Code
The Gray Code is a sequence of binary number systems, which is also known as reflected
binary code. The reason for calling this code as reflected binary code is the first N/2 values
compared with those of the last N/2 values in reverse order. In this code, two consecutive
values are differed by one bit of binary digits.
How to generate Gray code?
The prefix and reflect method are recursively used to generate the Gray code of a number.
For generating gray code:
1. We find the number of bits required to represent a number.
2. Next, we find the code for 0, i.e., 0000, which is the same as binary.
3. Now, we take the previous code, i.e., 0000, and change the most significant bit of it.
4. We perform this process reclusively until all the codes are not uniquely identified.
5. If by changing the most significant bit, we find the same code obtained previously,
then the second most significant bit will be changed, and so on.

2. Excess-3 Codes
The excess-3 code is also treated as XS-3 code. The excess-3 code is a non-weighted
and self-complementary BCD code used to represent the decimal numbers.
We can easily get an excess-3 code of a decimal number by simply adding 3 to each
decimal digit. And then we write the 4-bit binary number for each digit of the decimal
number. We can find the excess-3 code of the given binary number by using the
following steps:
1. We find the decimal number of the given binary number.
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2. Then we add 3 in each digit of the decimal number.

3. Now, we find the binary code of each digit of the newly generated decimal number.

3. ASCII Codes
The ASCII stands for American Standard Code for Information Interchange. The ASCII
code is an alphanumeric code used for data communication in digital computers. The ASCII
is a 7-bit code capable of representing 27 or 128 number of different characters. The ASCII
code is made up of a three-bit group, which is followed by a four-bit code.
1. The ASCII Code is a 7 or 8-bit alphanumeric code.
2. This code can represent 127 unique characters.
3. The ASCII code starts from 00h to 7Fh. In this, the code from 00h to 1Fh is used for
control characters, and the code from 20h to 7Fh is used for graphic symbols.
4. The 8-bit code holds ASCII, which supports 256 symbols where math and graphic
symbols are added.
5. The range of the extended ASCII is 80h to FFh.
6. The ASCII characters are classified into the following groups

TOPIC 2: Complements
1’s Complement:
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We can find the 1's complement of the binary number by simply inverting the given number.
For example, 1's complement of binary number 1011001 is 0100110.

Example 1: 11010.1101
For finding 1's complement of the given number, change all 0's to 1 and all 1's to 0. So the
1's complement of the number 11010.1101 comes out 00101.0010.

2’s Complement:
If we want to calculate the 2's complement of the number 1011001, then firstly, we find the
1's complement of the number that is 0100110 and add 1 to the LSB. So, by adding 1 to the
LSB, the number will be (0100110)+1=0100111.

Example 1: 110100
For finding 2's complement of the given number, change all 0's to 1 and all 1's to 0. So the
1's complement of the number 110100 is 001011. Now add 1 to the LSB of this number,
i.e., (001011) +1=001100.

Radix and Diminished Radix complement(r and r-1’s complement)

 For finding the subtraction of the number base system, the complements are used.
 If r is the base of the number system, then there are two types of complements that
are possible, i.e., r's and (r-1)'s.
 We can find the r's complement, and (r-1)'s complement of the number, here r is the
radix. The r's complement is also known as Radix complement (r-1)'s complement,
is known as Diminished Radix complement.
 If the base of the number is 2, then we can find 1's and 2's complement of the number.
 Similarly, if the number is the octal number, then we can find 7's and 8's complement
of the number.
There is the following formula for finding the r's and (r-1)'s complement:
r' s= complement=(rn )10-N
(r-1)' s complement={(rn)10-1}-N
In the above formula, n is the number of digits in the number, N is the given number, r is
the radix or base of the number.

Let's take some examples to understand how we can calculate the r's and (r-1)'s
complement of binary, decimal, octal, and hexadecimal numbers.
Example 1: (1011000)2
This number has a base of 2, which means it is a binary number. So, for the binary numbers,
the value of r is 2, and r-1 is 2-1=1. So, we can calculate the 1's and 2's complement of the
number.
1's complement of the number 1011000 is calculated as:
={(27 )10-1}-(1011000)2
={(128)10-1}-(1011000)2
={(127)10}-(1011000)2
=11111112-10110002
=0100111
2's complement of the number 1011000 is calculated as:

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=(27 )10-(1011000)2
=(128)10-(1011000)2
=100000002-10110002
=01010002

TOPIC:3 Fixed Point Representation and Floating Point

Representation
Data Format
Since the modern day computers/CPU are based on binary no. system hence, they accept
and provide outputs in binary format only.
In order to accept these binary data, we require a particular format called data format.
This binary representation of all data values (integer, real, float and character) is known as
data format.

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TOPIC:5 Register Transfer Language, Register Transfer

Register transfer language
 A digital computer system exhibits an interconnection of digital modules such as
registers, decoders, arithmetic elements, and Control logic.
 These digital modules are interconnected with some common data and control paths
to form a complete digital system.
 Moreover, digital modules are best defined by the registers and the operations that
are performed on the data stored in them.
 The operations performed on the data stored in registers are called Micro-
operations.
 The internal hardware organization of a digital system is best defined by specifying
1. The set of registers and the flow of data between them.
2. The sequence of micro-operations performed on the data which are stored in the
registers.
3. The control paths that initiates the sequence of micro-operation
The Register Transfer Language is the symbolic representation of notations used to
specify the sequence of micro-operations.
In a computer system, data transfer takes place between processor registers and memory
and between processor registers and input-output systems. These data transfer can be
represented by standard notations given below:
1. Notations R0, R1, R2..., and so on represent processor registers.
2. The addresses of memory locations are represented by names such as LOC, PLACE,
MEM, etc.

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3. Input-output registers are represented by names such as DATA IN, DATA OUT and
so on.
4. The content of register or memory location is denoted by placing square brackets
around the name of the register or memory location.
Define and explain register transfer
The term Register Transfer refers to the availability of hardware logic circuits that can
perform a given micro-operation and transfer the result of the operation to the same or
another register.
Most of the standard notations used for specifying operations on various registers are stated
below.
1. The memory address register is designated by MAR.
2. Program Counter PC holds the next instruction's address.
3. Instruction Register IR holds the instruction being executed.
4. R1 (Processor Register).
5. We can also indicate individual bits by placing them in parenthesis. For instance,
PC (8-15), R2 (5), etc.
6. Data Transfer from one register to another register is represented in symbolic form
by means of replacement operator. For instance, the following statement denotes a
transfer of the data of register R1 into register R2.
R2 ← R1
7. Typically, most of the users want the transfer to occur only in a predetermined
control condition. This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
8. It is more convenient to specify a control function (P) by separating the control
variables from the register transfer operation. For instance, the following statement
defines the data transfer operation under a specific control function (P).
P: R2 ← R1
9. The following image shows the block diagram that depicts the transfer of data from
R1 to R2.

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10. Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the
register R1 are connected to the 'n' inputs of register R2.
11. A load input is activated by the control variable 'P' which is transferred to the register
R2.

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The Register Transfer in detail with block diagram and timing

diagram.
Definition: Information transfer from one register to another is designated in symbolic form
by means of a replacement operator is known as Register Transfer.
R2 ← R1
Denotes a transfer of the content of register R1 into register R2.
 Computer registers are designated by capital letters (sometimes followed by numerals)
to denote the function of the register.
For example:

Block Diagram of Registers

 The most common way to represent a register is by a rectangular box with the name
of the register inside, as shown in figure.
 Bits 0 through 7 are assigned the symbol L (for low byte) and bits 8 through 15 are
assigned the symbol H (for high byte). The name of the 16-bit register is PC. The
symbol PC (0-7) or PC(L) refers to the low-order byte and PC(8-15) or PC(H) to the
high-order byte.
 The statement that specifies a register transfer implies that circuits are available from
the outputs of the source register to the inputs of the destination register and that the
destination register has a parallel load capability.

Register Transfer with control function:

 If we want the transfer to occur only under a predetermined control condition. This
can be shown by means of an if-then statement.
If (P = 1) then (R2← R1)
where P is a control signal.
 It is sometimes convenient to separate the control variables from the register transfer
operation control function by specifying a control function.
 A control function is a Boolean variable that is equal to 1 or 0. The control function is
included in the statement as follows:
P: R2←R1
 The control condition is terminated with a colon. It symbolizes the requirement that
the transfer operation be executed by the hardware only if P = 1.

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 Every statement written in a register transfer notation implies a hardware construction

for implementing the transfer. Below figures show the block diagram that depicts the
transfer from R1 to R2 and the timing diagram respectively.

 The n outputs of register R1 are connected to the n inputs of register R2. The letter n
will be used to indicate any number of bits for the register.
 In the timing diagram, P is activated in the control section by the rising edge of a
clock pulse at time t.
 The next positive transition of the clock at time t + 1 finds the load input active and
the data inputs of R2 are then loaded into the register in parallel.
 P may go back to 0 at time t + 1; otherwise, the transfer will occur with every clock
pulse transition while P remains active.
 The basic symbols of the register transfer notation are listed in Table below:

 Registers are denoted by capital letters, and numerals may follow the letters.
 Parentheses are used to denote a part of a register by specifying the range of bits or
by giving a symbol name to a portion of a register.
 The arrow denotes a transfer of information and the direction of transfer.
 A comma is used to separate two or more operations that are executed at the same
time.
 The statement below, denotes an operation that exchanges the contents of two
registers during one common clock pulse provided that T = 1.
T: R2← R1, R1← R2
 This simultaneous operation is possible with registers that have edge-triggered flip-
flops.

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TOPIC:6 Bus and Memory Transfers (Tree-State Bus Buffers,

Memory Transfer)
Three-state bus buffer(Tri-state buffer)
A bus system can also be constructed using three-state gates instead of multiplexers.
The three state gates can be considered as a digital circuit that has three gates, two of which
are signals equivalent to logic 1 and 0 as in a conventional gate.
However, the third gate exhibits a high-impedance state.
The most commonly used three state gates in case of the bus system is a buffer gate.

The following diagram demonstrates the construction of a bus system with three-state buffers

 The outputs generated by the four buffers are connected to form a single bus line.
 Only one buffer can be in active state at a given point of time.
 The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
 A 2 * 4 decoder ensures that no more than one control input is active at any given
point of time

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Common bus system for four register.

 A digital system composed of many registers, and paths must be provided to transfer
information from one register to another. The number of wires connecting all of the
registers will be excessive if separate lines are used between each register and all
other registers in the system.
 A bus structure, on the other hand, is more efficient for transferring information
between registers in a multi-register configuration system.
 A bus consists of a set of common lines, one for each bit of register, through which
binary information is transferred one at a time. Control signals determine which
register is selected by the bus during a particular register transfer.
 The following block diagram shows a Bus system for four registers. It is constructed
with the help of four 4 * 1 Multiplexers each having four data inputs (0 through 3)
and two selection inputs (S1 and S2).
 We have used labels to make it more convenient for you to understand the input-
output configuration of a Bus system for four registers. For instance, output 1 of
register A is connected to input 0 of MUX1.

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 The two selection lines S1 and S2 are connected to the selection inputs of all four
multiplexers. The selection lines choose the four bits of one register and transfer
them into the four-line common bus.
 When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all
four multiplexers are selected and applied to the outputs that forms the bus. This, in
turn, causes the bus lines to receive the content of register A since the outputs of this
register are connected to the 0 data inputs of the multiplexers.
 Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the
content provided by register B.
 The following function table shows the register that is selected by the bus for each
of the four possible binary values of the Selection lines.

Note: The number of multiplexers needed to construct the bus is equal to the number of
bits in each register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k'
data lines. For instance, a common bus for eight registers of 16 bits each requires 16
multiplexers, one for each line in the bus. Each multiplexer must have eight data input
lines and three selection lines to multiplex one significant bit in the eight registers.

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Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated
below.
 The transfer of information from a memory unit to the user end is called a Read
operation.
 The transfer of new information to be stored in the memory is called a Write
operation.
 A memory word is designated by the letter M.
 We must specify the address of memory word while writing the memory transfer
operations.
 The address register is designated by AR and the data register by DR.
 Thus, a read operation can be stated as:
Read: DR ← M [AR]
 The Read statement causes a transfer of information into the data register (DR) from
the memory word (M) selected by the address register (AR).
 And the corresponding write operation can be stated as:
Write: M [AR] ← R1
 The Write statement causes a transfer of information from register R1 into the
memory word (M) selected by address register (AR).

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Question: A digital computer has a common bus system for 16 registers of 32 bits each.
(i) How many selection input are there in each multiplexer?
(ii) What size of multiplexers is needed?
(iii) How many multiplexers are there in a bus?
Solution:
(i) How many selection inputs are there in each multiplexer?
2n=No. of Registers; n=selection input of multiplexer
2n=16; here n=4
Therefore 4 selection input lines should be there in each multiplexer.
(ii) What size of multiplexers is needed?
size of multiplexers= Total number of register X 1= 16 X 1
Hence, Multiplexer of 16 x 1 size is needed to design the above defined common bus.
(iii) How many multiplexers are there in a bus?
No. of multiplexers = bits of register = 32
32 multiplexers are needed in a bus.

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TOPIC:7 Arithmetic Micro-Operations

Arithmetic micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed on numeric
data stored in the registers.
The basic Arithmetic Micro-operations are classified in the following categories:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift
Some additional Arithmetic Micro-operations are classified as:
1. Add with carry
2. Subtract with borrow
3. Transfer/Load, etc.
The following table shows the symbolic representation of various Arithmetic Micro-
operations.

Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are

transferred to R3

R3 ← R1 - R2 The contents of R1 minus R2 are

transferred to R3

R2 ← R2' Complement the contents of R2 (1's

complement)

R2 ← R2' + 1 2's complement the contents of R2

(negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2

(subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Note: The increment and decrement micro-operations are symbolized by '+ 1' and '? 1'
respectively. Arithmetic operations like multiply and divide are not included in the basic
set of micro-operations.

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Binary Adder
 The Add micro-operation requires registers that can hold the data and the digital
components that can perform the arithmetic addition.
 A Binary Adder is a digital circuit that performs the arithmetic sum of two binary
numbers provided with any length.
 A Binary Adder is constructed using full-adder circuits connected in series, with the
output carry from one full-adder connected to the input carry of the next full-adder.
 The following block diagram shows the interconnections of four full-adder circuits
to provide a 4-bit binary adder.

 The augend bits (A) and the addend bits (B) are designated by subscript numbers
from right to left, with subscript '0' denoting the low-order bit.
 The carry inputs starts from C0 to C3 connected in a chain through the full-adders.
C4 is the resultant output carry generated by the last full-adder circuit.
 The output carry from each full-adder is connected to the input carry of the next-
high-order full-adder.
 The sum outputs (S0 to S3) generates the required arithmetic sum of augend and
addend bits.
 The n data bits for the A and B inputs come from different source registers. For
instance, data bits for A input comes from source register R1 and data bits
for B input comes from source register R2.
The arithmetic sum of the data inputs of A and B can be transferred to a third register
or to one of the source registers (R1 or R2).

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Binary Adder-Subtractor
 The Subtraction micro-operation can be done easily by taking the 2's compliment of
addend bits and adding it to the augend bits
Note: The 2's compliment can be obtained by taking the 1's compliment and adding one
to the least significant pair of bits. The 1's compliment can be implemented with inverters,
and one can be added to the sum through the input carry.
 The Arithmetic micro-operations like addition and subtraction can be combined into
one common circuit by including an exclusive-OR gate with each full adder.
 The block diagram for a 4-bit adder-subtractor circuit can be represented as:

 When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder and
when the mode input is at a high logic, i.e. '1', the circuit act as a subtractor.
 The exclusive-OR gate connected in series receives input M and one of the inputs
B.
 When M is at a low logic, we have B⊕ 0 = B. The full-adders receive the value of
B, the input carry is 0, and the circuit performs A plus B.
 When M is at a high logic, we have B⊕ 1 = B' and C0 = 1. The B inputs are
complemented, and a 1 is added through the input carry. The circuit performs the
operation A plus the 2's complement of B.

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Block diagram of 4-bit arithmetic circuit

Arithmetic circuits can perform seven different arithmetic operations using a single
composite circuit.
 It uses a full adder (FA) to perform these operations. A multiplexer (MUX) is used
to provide different inputs to the circuit in order to obtain different arithmetic
operations as outputs.
 4-bit Arithmetic Circuit:

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Truth Table for the above Arithmetic Circuit:

S0 S1 C0 MUX Output Full Adder
Output

0 0 0 B A+B

0 0 1 B A+B+1
0 1 0 B’ A + B’
0 1 1 B’ A + B’ + 1 = A –
B
1 0 0 0 A
1 0 1 0 A+1
1 1 0 1 A–1
1 1 1 1 A–1+1=A

Hence, the different operations for the inputs A and B are:

1. A + B (adder)
2. A + B + 1
3. A + B’
4. A – B (subtracter)
5. A
6. A + 1 (incrementer)
7. A – 1 (decrementer)

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New L J Institute of Engineering and Technology Semester: IV (2024)

TOPIC:8 Logic Micro-Operations

Logic micro-operations
There are four types of micro-operations: -
1. Register micro-operations
2. Arithmetic micro-operations
3. Logic micro-operations
4. Shift micro-operations
Logic Micro-Operations: Logic micro-operations are used on the bits of data stored in
registers. These micro-operations treat each bit independently and create binary variables
from them.
There are a total of 16 micro-operations available, which are:

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The below diagram shows the truth table for all the 16 logic micro-operations mentioned
above. Here, x and y are the variables or registers in which the data is stored and F0, F1,..,
F15 are the outputs that occur after performing these logic micro-operations.

1. Clear: The Clear logic micro-operation is used to clear the register or set the bits of
the register to 0. To use this micro-operation, we need to feed 0 to the register. In
the above truth table, F0 represents the truth table of Clear logic micro-operation.
2. AND: The AND logic micro-operation performs the logical AND between the bits
of the data stored in the two registers. The symbol to represent the logical AND is
∧.
3. Transfer A: The Transfer A logic micro-operation transfers the contents of register
A (first register) to the output register.
4. Transfer B: The Transfer B logic micro-operation transfers the contents of register
B (second register) to the output register.
5. Exclusive OR: Also known as XOR, this logic micro-operation performs the logical
XOR between the data bits stored in the two registers. The logical XOR means either
x should be true or y but not both. The symbol to represent the Exclusive OR is ⊕.
6. OR: The OR logic micro-operation performs the logical OR between the data bits
stored in the two registers. The symbol to represent the logical OR is ∨.
7. NOR: The NOR logic micro-operation is simply the opposite of OR logic micro-
operation. As the name suggests, it is Not OR. The output of OR micro-operation is
1 when the value of either x register or y register or both x and y registers are true.
In contrast, in NOR, the output is 0 when the value of either x register or y register
or both x and y registers are true, and it is 1 when both x and y registers are false. In
the above truth table, F8 represents the truth table of NOR logic micro-operation.
8. Exclusive NOR: If we perform the Exclusive NOR micro-operation, the output will
be 1 when the values of both the x and y registers will be the same. They can be true
or false, but they have to be the same.
9. Complement B: The Complement B logic micro-operation transfers the
complemented contents of register B (second register) to the output register. First,
the content of the register is complemented and then moved to the desired register.
10. Complement A: The Complement A logic micro-operation transfers the
complemented contents of register A (first register) to the output register. First, the
content of the register is complemented and then moved to the desired register.
11. NAND: The NAND logic micro-operation is simply the opposite of AND logic
micro-operation. As the name suggests, it is Not AND. The output of AND micro-
operation is 1 when the value of both the x register and y register is true. In contrast,
in NAND, the output is 0 when the value of both x register and y register is true, and
it is 1 when either x is false, or y is false, or both are false.
12. Set to all 1’s: The set to all 1’s logic micro-operations is used to set all the register
bits to 1. To use this micro-operation, we just need to feed 1 to the register. In the

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above truth table, F15 represents the truth table of Set to all 1’s logic micro-
operation.
Hardware Implementation
 The hardware implementation of logic micro-operation requires that logic gates be
inserted for each bit or pair of bits in the registers to perform the required logic function.
 Although there are 16 logic microoperation, most computers use only four—AND, OR,
XOR (exclusive-OR), and complement from which all others can be derived.
 Below figure shows one stage of a circuit that generates the four basic logic micro-
operations.
Hardware implementation consists of four gates and a multiplexer.
 Each of the four logic operations is generated through a gate that performs the
required logic.
 The outputs of the gates are applied to the data inputs of the multiplexer.
 The two selection inputs S1 and S0 choose one of the data inputs of the
multiplexer and direct its value to the output.
 The diagram shows one typical stage with subscript i. For a logic circuit with n bits,
the diagram must be repeated n times for i = 0, 1, 2, . . . n - 1. The selection variables
are applied to all stages

Single stage logic circuit

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Selective set, selective complement and selective clear

Selective-set operation:
 The selective-set operation sets to 1 the bits in register A where there are
corresponding 1's in register B. It does not affect bit positions that have 0's in
B.
 The following numerical example clarifies this operation:
1010 A before
1100 B (logical operand)
1110 A after
 The two leftmost bits of B are 1's, so the corresponding bits of A are set to
1.
 One of these two bits was already set and the other has been changed from 0
to 1.
 The two bits of A with corresponding 0's in B remain unchanged. The
example above serves as a truth table since it has all four possible
combinations of two binary variables.
 The OR micro-operation can be used to selectively set bits of a register.

Selective-Complement operation:
 The selective-complement operation complements bits in A where there are
corresponding 1's in B.
 It does not affect bit positions that have O's in B. For example:
1010 A before
1100 B (logical operand)
0110 A after
 Again the two leftmost bits of B are 1's, so the corresponding bits of A are
complemented.
 The exclusive-OR micro-operation can be used to selectively complement
bits of a register

Selective-Clear operation:
 The selective-clear operation clears to 0 the bits in A only where there are
corresponding 1's in B. For example:
1010 A before
1100 B (logical operand)
0010 A after
 Again the two leftmost bits of B are 1's, so the corresponding bits of A are
cleared to 0.
 One can deduce that the Boolean operation performed on the individual bits
is AB'.
 The corresponding logic micro-operation is A ← A ∧ B’.

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TOPIC:9 Shift Micro-Operations

Shift micro operations and draw 4-bit combinational circuit shifter
There are three types of shift micro-operations:
 Logical Shift
 Arithmetic Shift
 Circular Shift

Logical Shift: The logical shift micro-operation moves the 0 through the serial input. There
are two ways to implement the logical shift.
 Logical Shift Left
 Logical Shift Right

a) Logical Shift Left:

 Each bit in the register is shifted to the left one by one in this shift micro-operation.
The most significant bit (MSB) is moved outside the register, and the place of the
least significant bit (LSB) is filled with 0.
 For example, in the below data, there are 8 bits 00001010. When we perform a
logical shift left on these bits, all these bits will be shifted towards the left. The MSB
or the leftmost bit i.e. 0 will be moved outside, and at the rightmost place or LSB, 0
will be inserted as shown below.

 To implement the logical shift left micro-operation, we use the shl symbol.
For example, R1 -> shl R1.
 This command means the 8 bits present in the R1 register will be logically shifted
left, and the result will be stored in register R1.
 Moreover, the logical shift left micro-operation denotes the multiplication of 2. The
example we’ve taken above when converted into decimal forms the number 10 and
the result after the logical shift operation when converted to decimal forms the
number 20.
b) Logical Shift Right:
 Each bit in the register is shifted to the right one by one in this shift micro-operation.
The least significant bit (LSB) is moved outside the register, and the place of the
most significant bit (MSB) is filled with 0.
 For example, in the below data, there are 8 bits 00000101. When we perform a
logical shift right on these bits, all these bits will be shifted towards the right. The

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LSB or the rightmost bit i.e. 1 will be moved outside, and at the leftmost place or
MSB, 0 will be inserted as shown below.

 To implement the logical shift right micro-operation, we use the shr symbol.
For example, R1 -> shr R1.
 This command means the 8 bits present in the R1 register will be logically shifted
right, and the result will be stored in register R1.
 Logical right shift micro-operation generally denotes division by 2. The inputted bits
when converted into decimal form the number 5 and the outcome when converted
into decimal forms the number 2.
Arithmetic Shift:
The arithmetic shift micro-operation moves the signed binary number either to the left or to the right
position. There are two ways to implement the arithmetic shift:
a) Arithmetic Shift Left
b) Arithmetic Shift Right
a) Arithmetic Shift Left:
 The arithmetic shift left micro-operation is the same as the logical shift left micro-
operation. Each bit in the register is shifted to the left one by one in this shift micro-
operation. The most significant bit (MSB) is moved outside the register, and the
place of the least significant bit (LSB) is filled with 0.

 For example, in the below data, there are 8 bits 00100011. When we perform the
arithmetic shift left on these bits, all these bits will be shifted towards the left. The
MSB or the leftmost bit i.e. 0 will be moved outside, and at the rightmost place or
LSB, 0 will be inserted as shown below.

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 The given binary number (00100011) represents 35 in the decimal system and the
binary number after logical shift left (01000110) represents 70 in a decimal system.
Since 35 * 2 = 70. Therefore, we can say that the arithmetic shift left multiplies the
number by 2.
 To implement the arithmetic shift left micro-operation, we use the ashl symbol.
For example, R1 -> ashl R1.
 This command means the 8 bits present in the R1 register will be arithmetic shifted
left, and the result will be stored in register R1.
b) Arithmetic Shift Right:
 Each bit in the register is shifted to the right one by one in this shift micro-operation.
The least significant bit (LSB) is moved outside the register, and the place of the
most significant bit (MSB) is filled with the previous value of MSB.
 For example, in the below data, there are 8 bits 10100011. When we perform an
arithmetic shift right on these bits, all these bits will be shifted towards the right.
The LSB or the rightmost bit i.e. 1 will be moved outside, and at the leftmost place
or MSB, the previous MSB value, i.e. 1, will be inserted as shown below:

 Arithmetic right shift divides the number by 2.

 To implement the arithmetic shift right micro-operation, we use the ashr symbol.
For example, R1 -> ashr R1.
 This command means the 8 bits present in the R1 register will be arithmetic
shifted right, and the result will be stored in register R1.
 Next, we will study circular shift micro-operation.

Circular Shift:
The circular shift, also known as the rotate shift, moves the bits in the register's sequence around
both ends, thus ensuring no loss of information. There are two ways to implement the circular shift.

a) Circular Shift Left

b) Circular Shift Right

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a) Circular Shift Left:

 Each bit in the register is shifted to the left one by one in this shift micro-operation.
After shifting, the least significant bit (LSB) place becomes empty, so it is filled
with the value at the most significant bit (MSB).
 For example, in the below data, there are 8 bits 00010100. When we perform a
circular shift left on these bits, all these bits will be shifted towards the left. The
MSB or the leftmost bit i.e. 0 will be placed at the rightmost place or LSB as shown
below.

 To implement the circular shift left micro-operation, we use the cil symbol.
For example, R1 -> cil R1.
 This command means the 8 bits present in the R1 register will be circular shifted
left, and the result will be stored in register R1.

b) Circular Shift Right:

 Each bit in the register is shifted to the right one by one in this shift micro-operation.
After shifting, the most significant bit (MSB) place becomes empty, so it is filled
with the value at the least significant bit (LSB).
For example, in the below data, there are 8 bits 00010100. When we perform a circular shift
right on these bits, all these bits will be shifted towards the right. The LSB or the leftmost
bit, i.e. 0, will be placed at the rightmost place or MSB.

 To implement the circular shift right micro-operation, we use the cir symbol.
For example, R1 -> cir R1.
 This command means the 8 bits present in the R1 register will be circular shifted
right, and the result will be stored in register R1.

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4-Bit Combinational Shifter Circuit

 The 4-bit shifter has four data inputs, A0 through A3 and four data outputs, H0
through H3.
 There are two serial inputs, one for shift left (IL) and the other for shift right (IL).
 When the selection input S = 0, the input data are shifted right (down in the diagram).
 When S = 1, the input data are shifted left (up in the diagram).
 The two serial inputs can be controlled by another multiplexer to provide the three
possible types of shifts.

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TOPIC:10 Arithmetic Logical Shift Unit

Arithmetic logic shift unit

The arithmetic, logic, and shift circuits are combined to one ALU with common selection
variables. The diagram below shows one stage of an arithmetic logic shift unit. The subscript
i designates a typical stage.

One Stage of Arithmetic Logic Shift Unit

 With inputs S1 and S0, a specific microoperation is chosen. At the output, a 4 x 1

multiplexer selects between an arithmetic output and a logic output. Inputs S3 and
S2 select the data in the multiplexer. The multiplexer's other two data inputs receive
inputs Ai — 1 for the shift-right operation(shr) and Ai + 1 for the shift-left operation
(shl).

 It should be noted that the circuit diagram only depicts one typical stage. For an n-
bit ALU, the circuit shown above must be repeated n times. The output that carries
Ci+1 of a given arithmetic stage must be connected to the input carry Ci of the next
stage in the sequence. The input carried to the first stage is the input carry Cin, which
provides a selection variable for the arithmetic operations.

 The circuit whose one stage is specified in the diagram given above provides eight
arithmetic, four logical, and two-shift operations. Each operation is selected with
five variables S3, S2, S1, S0, and Cin. Here Cin is used for selecting an arithmetic
operation only.

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 The table given below is the function table of the Arithmetic Logic Shift Unit.

Operatio Function
S3 S2 S1 S0 Cin
n
0 0 0 0 0 F=A Transfer
A

0 0 0 0 1 F=A+1 Increment
A

0 0 0 1 0 F=A+B Addition

0 0 0 1 1 F = A + B Add with
+1 carry

0 0 1 0 0 F = A + B’ Subtract
with
borrow

0 0 1 0 1 F = A + B’ Subtractio
+1 n

0 0 1 1 0 F=A–1 Decreme
nt A

0 0 1 1 1 F=A Transfer
A

0 1 0 0 X F=A∧B AND

0 1 0 1 X F=A∨B OR

0 1 1 0 X F = A ⊕ B XOR

0 1 1 1 X F = A’ Complem
ent A

1 0 X X X F = shr A Shift right

A into F

1 1 X X X F = shl A Shift Left

A into F

0 0 0 0 1 F=A+1 Increment
A

The above table shows 14 operations of ALU (Arithmetic Logical Unit).

 The first eight are arithmetic operations (where S3S2=0).
 The next four operations are logical and are selected with S3S2=01.
 The final two operations are shift operations, selected with S3S2=10 and 11.

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