3395
3395
com
https://textbookfull.com/product/transformer-based-design-
techniques-for-oscillators-and-frequency-dividers-1st-
edition-howard-cam-luong/
OR CLICK HERE
DOWLOAD EBOOK
https://textbookfull.com/product/cam-design-and-manufacture-second-
edition-jensen/
textbookfull.com
https://textbookfull.com/product/power-transformer-design-
practices-1st-edition-fang-zhu/
textbookfull.com
https://textbookfull.com/product/inverter-based-circuit-design-
techniques-for-low-supply-voltages-1st-edition-rakesh-kumar-palani/
textbookfull.com
https://textbookfull.com/product/frequency-domain-receiver-design-for-
doubly-selective-channels-1st-edition-paulo-montezuma/
textbookfull.com
Transformer Design Principles Third Edition Robert M. Del
Vecchio
https://textbookfull.com/product/transformer-design-principles-third-
edition-robert-m-del-vecchio/
textbookfull.com
https://textbookfull.com/product/transformer-design-principles-third-
edition-robert-m-del-vecchio-2/
textbookfull.com
https://textbookfull.com/product/microwave-and-rf-design-
volume-5-amplifiers-and-oscillators-michael-steer/
textbookfull.com
https://textbookfull.com/product/fragment-based-drug-discovery-1st-
edition-steven-howard/
textbookfull.com
https://textbookfull.com/product/transformer-design-principles-with-
applications-robert-m-del-vecchio/
textbookfull.com
Howard Cam Luong · Jun Yin
Transformer-Based
Design Techniques
for Oscillators and
Frequency Dividers
Transformer-Based Design Techniques
for Oscillators and Frequency Dividers
Howard Cam Luong • Jun Yin
Transformer-Based Design
Techniques for Oscillators
and Frequency Dividers
Howard Cam Luong Jun Yin
ECE department State Key Laboratory of Analog
Hong Kong University and Mixed-Signal VLSI
of Science and Technology University of Macau
Kowloon, Hong Kong SAR Taipa, Macau, China
Voltage-controlled oscillators (VCOs) and frequency dividers are two of the key
building blocks in phase-locked loops (PLLs) and frequency synthesizers, not only
to generate clean LO signals for frequency conversion in wireless transceivers but
also to generate accurate high-frequency clock signals for wireline systems. As the
system applications continue to demand higher and higher performance in terms of
higher frequency, wider bandwidth, lower phase noise, and lower power consump-
tion, the design of these building blocks becomes more and more challenging, in
particular in aggressively scaled low-voltage CMOS processes for low cost and
high system-on-chip integration.
Many years ago, we published a book entitled “Low-Voltage CMOS RF
Frequency Synthesizers” to discuss and summarize various inductor-based design
techniques for low-voltage high-performance frequency synthesizers. The main
focus was on low-voltage and low-power designs for narrow-band applications,
in which integrated inductors play a critical role. However, due to their high-Q and
narrow-band characteristics, these design techniques have limited applications in
recently emerging multi-band multi-mode and software-defined radios. Fortu-
nately, transformer-based design techniques have recently been developed and
emerged as potential replacement of integrated inductors for more features and
even better performance. However, to the best of our knowledge, there has still been
no book aiming to introduce transformer-based low-voltage and wideband CMOS
VCOs and frequency dividers.
As continuation and complementary to our previous book and intended for
engineers, mangers, researchers, and students who are working on or interested in
CMOS radio frequency or mm-Wave integrated circuits and systems, this book
presents in-depth description and discussion of transformer-based design tech-
niques that enable CMOS oscillators and frequency dividers to achieve ultra-wide
frequency tuning range and ultra-wide frequency locking range while maintaining
state-of-the-art performance in terms of high operation frequency, low supply
voltage, good phase noise, and low power consumption. In addition to the design,
simulation, and characterization of integrated transformers for different
v
vi Preface
applications, this book will also discuss their unique characteristics and features
that enable performance improvement, such as passive coupling or multiple imped-
ance peaks, which have not been covered in any of the existing books. Finally, to
illustrate the usefulness of these transformer-based design techniques, design con-
sideration and optimization of various CMOS oscillators and frequency dividers for
different applications together with their measured performance are elaborated,
focusing on not only ultra-low supply voltage but also ultra-wide frequency tuning
range and locking range at very high frequencies.
More specifically, detailed description and discussion of the following selected
designs will be included in the book.
1. A transformer-feedback VCO (TF-VCO) features high swing and low phase
noise even at a supply voltage below the device threshold voltage. Fabricated in
a 0.18-μm CMOS process, a 1.4-GHz PMOS TF-VCO achieves an FoM of
190 at 0.35-V supply voltage, and a 3.8-GHz NMOS TF-VCO achieves an FoM
of 193 at 0.5-V supply voltage.
2. A quadrature VCO using transformer coupling (TC-QVCO) eliminates both
noise and power consumption by active coupling devices in existing QVCOs
while exhibiting all advantages in the TF-VCO. Fabricated in a 0.18-μm CMOS
process, a 17-GHz TC-QVCO achieves an FoM of 187.6 and a phase error of
1.4 at 1-V supply voltage.
3. A transformer-based dual-mode VCO achieves a wide frequency tuning range
exploiting the two impedance peaks of a transformer tank. Fabricated in a 0.13-μ
m CMOS process, the 2.7-to-4.3 GHz and 8.4-to-12.4 GHz dual-mode QVCO
achieves average FoMT of 195 and 203 in the two bands, respectively.
4. A magnetically tuned multi-mode VCO (MT-VCO) measures ultra-wide
frequency tuning range around 70 GHz by changing the coupling coefficient
of the transformer. Fabricated in a 65-nm CMOS process, the 57.1-to-90.1 GHz
MT-VCO achieves an average FoMT of 188.2 at 1-V supply.
5. Transformer-feedback injection-locked frequency dividers (TF-ILFDs) feature
quadrature outputs with enhanced output swing even with low supply and low
power. Fabricated in a 0.18-μm CMOS process, a 18.1-GHz TF-ILFD
with differential outputs achieves 21.6 % locking range when consumes
2.75–4.35 mW at 0.5-V supply, and a 17.5-GHz TF-ILFD with quadrature
outputs achieves 27.8 % locking range when consuming 11.4–13.6 mW at a
0.6-V supply.
6. A self-frequency-tracking injection-locked frequency divider (SFT-ILFD) uti-
lizing transformer to generate the injection current with frequency-dependent
phase shift to extend the locking range. Fabricated in a 65-nm CMOS process, a
62.9-GHz SFT-ILFD achieves 29 % locking range while consuming 1.9 mW at a
0.8-V supply voltage.
It is our great pleasure to have this opportunity to acknowledge and to express our
sincere gratitude to many people who have been directly or indirectly contributing
to this work.
We are whole-heartedly indebted and grateful to Ka-Chun Kwok, Alan
Wing-Lun Ng, Tay Hui Zheng, and Annby Sujiang Rong for their great work and
contribution on transformer-based VCOs, QVCOs, and ILFDs that play an impor-
tant part of this book.
Our special thanks go to Fred Kwok for his enthusiastic and indispensable technical
effort and support in preparing testing setup and enabling good measurements.
We would like to thank many other students in the Analog Research Laboratory
in the ECE Department of HKUST, namely Liang Wu, Shiyuan Zheng, and Charry
Yue Chao, for sharing many fruitful discussions and many sleepless nights before
project tape-out, without which it would not be possible for us to acquire good
understanding of the topic to complete this book.
Technical support and assistance by many technical officers in the ECE
Department at HKUST, in particular Siu-Fai Luk, Kenny Pang, John Law, and
Jacob Lai, are greatly appreciated.
We would also like to acknowledge valuable financial support from various
funding agencies including Hong Kong General Research Funding (GRF), Hong
Kong Innovation Technology Funding (ITF) and Macao Science and Technology
Development Fund (FDCT). Generous sponsorship and donations for university
programs and chip fabrication from Taiwan Semiconductor Manufacturing Corpo-
ration (TSMC), MediaTek in Singapore (MSL), and Broadcom Foundation are also
highly appreciated.
Lastly, we are indebted to our family members (Kim Truong, Lilian Luong, and
Mengzhu Luo) for their constant love, support, encouragement, and patience
throughout the projects and during the writing of this book.
vii
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Transformer Design and Characterization
in CMOS Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Transformer Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Transformer Measurement and Characterization . . . . . . . . . . . . . 12
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Design Considerations for CMOS Voltage-Controlled
Oscillators (VCOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1 Start-Up Oscillation Conditions . . . . . . . . . . . . . . . . . . . 21
3.1.2 Phase-Noise Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.3 LC-Tank Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.4 Frequency Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Phase-Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1 Linear and Time-Invariant (LTI) Model . . . . . . . . . . . . . 29
3.2.2 Linear and Time-Variant (LTV) Model . . . . . . . . . . . . . . 31
3.3 Design Insights Using the Time-Variant Model . . . . . . . . . . . . . 34
3.3.1 Phase Noise in 1/f 2 Region . . . . . . . . . . . . . . . . . . . . . . 35
3.3.2 Phase Noise in 1/f 3 Region . . . . . . . . . . . . . . . . . . . . . . 38
3.3.3 Comparison of Different LC-VCO Topologies . . . . . . . . 43
3.3.4 VCO Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 Quadrature VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5 Low-Voltage CMOS VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6 Wideband CMOS VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ix
x Contents
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 1
Introduction
1.1 Motivation
Wireless and wireline transceiver systems have greatly been benefited from the
aggressive scaling down of CMOS technology to improve their performance in
terms of speed, power, and form factor. On the other hand, the CMOS technology
scaling down also imposes great challenges to designs of radio frequency (RF) and
analog circuits mainly because the supply voltage (VDD) scales much faster than the
threshold voltage (Vth) of CMOS transistors. From Fig. 1.1, the available overdrive
voltage (VDD Vth) in 65-nm CMOS technology is reduced to around 0.5 V, which
limits the voltage headroom and significantly degrades the performance of RF and
analog circuits.
For emerging applications powered by various energy-harvesting methods, the
generated supply voltage VDD may be as low as or even lower than the device
threshold voltage Vth, which limits practical use of many conventional RF and
analog integrated circuits design techniques. Although on-chip boost converters can
be employed to increase the supply voltage, for applications with such low input
voltages and large voltage conversion ratios, their limited efficiency of around
40–75 % would cause significant power penalty [2]. Instead, exploiting RF and
analog circuit techniques that can work under supply voltage close to Vth has been
proven to be a promising solution to greatly reduce the power consumption [3].
On the other hand, emerging wireless applications utilizing much high carrier
frequencies can take advantages of the large bandwidth available to provide
services with data rate of multi-gigabit per second. For example, the IEEE
802.11ad (WiGig) standard [4] and IEEE 802.15.3c standard [5] located at
60 GHz provide available bandwidth of 9 GHz. However, design of wideband
transceivers to cover such a large bandwidth at such a high frequency becomes
quite challenging.
RF frequency synthesizers based on phase-locked loops (PLLs) to provide the
local oscillation (LO) signals for frequency conversion is one of the key building
VDD
5
Vth
4
Voltage [V]
0
1.4 1.0 0.8 0.6 0.35 0.25 0.18 0.13 0.09 0.065
CMOS Technology [µm]
Fig. 1.1 Scaling down of supply voltage (VDD) and threshold voltage (Vth) with the CMOS
technologies [1]
Fig. 1.2 Schematic of conventional (a) LC-VCO, (b) LC-ILFD with direct injection, and (c)
LC-ILFD with indirection injection from current bias
usage as the CMOS technology is further scaled down. Even worse, for the
applications requires a supply voltage lower than the device threshold voltage
Vth, the conventional LC-VCOs and LC-ILFDs may fail to work properly since
the cross-coupled transistors cannot provide large enough negative transcon-
ductance to compensate the loss from the LC tank.
For the design of LC tanks in conventional LC-VCOs and LC-ILFDs, high tank
quality factor (Q) is preferred to suppress the noise while still maintaining low
power consumption. On the other hand, the narrowband frequency response char-
acteristics of a high-Q tank would in turn limit the operating frequency range of
LC-VCOs and the locking range of LC-ILFDs. In particular, it would impose a
critical challenge in modern RF transceivers that can support multi-standard and
multiband applications or even the software-defined radio (SDR) and cognitive
radio applications, in which ultra-wideband LOs are required. The most straight-
forward way to cover a wide frequency range is to duplicate multiple narrowband
LC VCOs and to multiplex their outputs [12, 13]. For example, in a 40-nm digital
CMOS process, two LC-VCOs (6–9 and 9–12 GHz) are needed to cover the
required 6–12 GHz frequency range with sufficient phase-noise performance for
SDR application in [14]. However, this method is not area efficient since the
monolithic inductor occupies much larger chip area than other devices and is not
scalable with CMOS technology.
To make the matter worse, the problem with insufficient tuning range of conven-
tional LC-VCOs becomes more and more acute as the oscillation frequency keeps
increasing. Since the varactor Q becomes dominantly low in the tank, the limited
varactor size degrades the frequency tuning range greatly. The typical tuning range
of LC-VCOs reported at around 60 GHz is less than 10 % [14–16], which is far from
being sufficient to cover the 9-GHz bandwidth required by IEEE 802.11ad standard
or IEEE 802.15.3c standard when taking into account process variations and inac-
curate device modeling. Similarly, high-frequency LC-ILFDs suffer from a big
4 1 Introduction
problem with insufficient frequency locking range due to their desirable high tank Q
for low power consumption and narrowband filtering. At input frequency of around
60 GHz, the typical locking range of LC-ILFDs reported is around 12 % [17, 18].
In this book, in-depth description and discussion of transformer-based design
techniques that enable CMOS VCOs and ILFDs to achieve state-of-the-art perfor-
mance in terms of low supply voltage, low-power consumption, good phase noise,
high operation frequencies, and wide frequency tuning range and locking range are
presented. To illustrate the usefulness of these transformer-based design tech-
niques, design consideration and optimization of various VCOs and dividers for
different applications together with their measured performance are discussed in
detail, focusing on not only ultra-low supply voltage but also ultrawide frequency
tuning range and locking range at high frequencies.
This book is organized as follows. Chapter 2 will introduce how to design, simulate,
and characterize on-chip inductors and transformers in CMOS process, including
step-by-step procedures to simulate and model the passive devices for circuit design
and to verify the model based on silicon measurement. In Chap. 3, the phase-noise
analysis and design consideration of VCOs and quadrature VCOs (QVCOs) will be
reviewed, and the performance degradation with the scaling down of VDD will be
discussed in detail. Chapter 4 introduces the principle of ILFDs and Miller dividers
and analyzes their locking range based on the phasor diagram. To demonstrate the
usefulness of the transformer-based design techniques, detailed design consider-
ations and measured results of a couple selected low-voltage high-performance
VCOs and QVCOs using transformer feedback will be presented in Chap. 5.
Chapters 6 and 7 will focus on the designs of transformer-based dual-mode or
multimode VCOs for wideband applications. In Chap. 8, design examples for
ILFDs using transformer technique to achieve either low-voltage or wide locking
range will be discussed. Finally, conclusion will be drawn in Chap. 9, from which
recommendations for future work will be made.
References
1. Packan, P. (2007, December). Device and circuit interactions. IEEE International Electron
Device Meeting Short Course: Performance Boosters for Advanced CMOS Devices.
2. Carlson, E. J., Strunz, K., & Otis, B. P. (2010). A 20 mV input boost converter with efficient
digital control for thermoelectric energy harvesting. IEEE Journal of Solid-State Circuits, 45,
741–750.
3. Zhang, F., Wang, K., Koo, J., Miyahara, Y., & Otis, B. (2013). A 1.6mW 300mV-supply
2.4GHz receiver with 94dBm sensitivity for energy-harvesting applications. IEEE ISSCC
Digest of Technical Papers, pp. 456–457.
References 5
4. Wireless LAN medium access control (MAC) and physical layer (PHY) specifications, amend-
ment 3: Enhancements for very high throughput in the 60 GHz band, IEEE Std 802.11adTM.
(2012). New York: IEEE.
5. Wireless medium access control (MAC) and physical layer (PHY) specifications for high rate
wireless area network, amendment 2, IEEE 802.15.3cTM. (2009). New York: IEEE.
6. Staszewski, R. B., Hung, C.-M., Maggio, K., Wallberg, J., Leipold, D., & Balsara, P. T. (2004).
All-digital phase-domain TX frequency synthesizer for bluetooth radios in 0.13μm CMOS.
IEEE ISSCC Digest of Technical Papers, pp. 272–273.
7. Wu, W., Bai, X., Staszewski, R. B., & Long, J. R. (2013). A 56.4-to-63.4GHz spurious-free
all-digital fractional-N PLL in 65nm CMOS. IEEE ISSCC Digest of Technical Papers,
pp. 352–353.
8. Rategh, H. R., Samavati, H., & Lee, T. H. (2000). A CMOS frequency synthesizer with an
injection-locked frequency divider for a 5-GHz wireless LAN receiver. IEEE Journal of Solid-
State Circuits, 35, 780–787.
9. Tiebout, M. (2004). A CMOS direct injection-locked oscillator topology as high-frequency
low-power frequency divider. IEEE Journal of Solid-State Circuits, 39, 1170–1174.
10. Kim, D., Kim, J., & Cho, C. (2008). A 94 GHz locking hysteresis-assisted and tunable CML
static divider in 65 nm SOI CMOS. IEEE ISSCC Digest of Technical Papers, pp. 460–461.
11. Ghilioni, A., Mazzanti, A., & Svelto, F. (2013). Analysis and design of mm-wave frequency
dividers based on dynamic latches with load modulation. IEEE Journal of Solid-State Circuits,
48, 1842–1850.
12. Borremans, J., Vengattaramane, K., Giannini, V., Debaillie, B., Thillo, W. V., & Craninckx,
J. (2010). A 86 MHz–12 GHz digital-intensive PLL for software-defined radios, using a
6 fJ/step TDC in 40 nm digital CMOS. IEEE Journal of Solid-State Circuits, 45, 2116–2129.
13. Yu, S.-A., Baeyens, Y., Weiner, J., Koc, U.-V., Rambaud, M., Liao, F.-R., et al. (2011). A
single-chip 125-MHz to 32-GHz signal source in 0.18-μm SiGe BiCMOS. IEEE Journal of
Solid-State Circuits, 46, 598–614.
14. Cao, C., & O, K. K. (2006). Millimeter-wave voltage-controlled oscillators in 0.13-μm CMOS
technology. IEEE Journal of Solid-State Circuits, 41(6), 1297–1304.
15. Kim, D. D., Kim, J., Plouchart, J.-O., Cho, C., Li, W., Lim, D., et al. (2007). A 70GHz
manufacturable complementary LC-VCO with 6.14GHz tuning range in 65nm SOI CMOS.
IEEE ISSCC Digest of Technical Papers, pp. 540–541.
16. Li, L., Reynaert, P., & Steyaert, M. S. J. (2009). Design and analysis of a 90 nm mm-wave
oscillator using inductive-division LC tank. IEEE Journal of Solid-State Circuits, 44,
1950–1958.
17. Gu, Q., Xu, Z., Huang, D., LaRocca, T., Wang, N.-Y., Hant, W., et al. (2008). A low power
V-band CMOS frequency divider with wide locking range and accurate quadrature output
phases. IEEE Journal of Solid-State Circuits, 43, 991–998.
18. Rong, S., Ng, A. W. L., & Luong, H. C. (2009). 0.9 mW 7 GHz and 1.6 mW 60 GHz frequency
dividers with locking-range enhancement in 0.13 μm CMOS. IEEE ISSCC Digest of Technical
Papers, pp. 96–97.
Chapter 2
Transformer Design and Characterization
in CMOS Process
2.1 Background
Fig. 2.1 Schematic symbol of (a) an ideal N : 1 transformer and (b) a transformer made of two
coupled inductors
the impedance seen from the primary coil becomes N2 times of the loading
impedance of the secondary coil.
Figure 2.1b shows a transformer made of two coupled inductors. From the
Faraday’s law of induction, the induced voltage at either coil equals to the rate of
change of the total magnetic flux going through it:
dðΦ11 þ Φ21 Þ dΦ11 dI1 dΦ21 dI2
V1 ¼ ¼ þ ð2:1aÞ
dt dI1 dt dI2 dt
dðΦ22 þ Φ12 Þ dΦ22 dI2 dΦ12 dI1
V2 ¼ ¼ þ ð2:1bÞ
dt dI2 dt dI1 dt
where Φ11 (Φ22) is the magnetic fluxes in the primary (secondary) coil generated by
the current I1 (I2) in itself and Φ21 (Φ12) is the magnetic fluxes in the secondary
(primary) coil generated by the current I2 (I1) in its neighboring coil. By defining the
self-inductance as L1 ¼ ðdΦ11 =dI1 Þ, L2 ¼ ðdΦ22 =dI2 Þ, the mutual inductance as
M ¼ ðdΦ12 =dI1 Þ ¼ ðdΦ21 =dI2 Þ, and applying Laplace transformation to (2.1a)
and (2.1b), V–I equations of the ideal transformer can then be expressed as
V1 sL1 sM I1
¼ ð2:2Þ
V2 sM sL2 I2
In the circuit analysis, the T-model as shown in Fig. 2.2 is typically employed to
represent the transformer made of coupled inductors as shown in Fig. 2.1b, which
can also be easily shown to be equivalent to (2.2). To represent the coupling
strength between the two coupled inductors, the magnetic coupling coefficient k
defined as the ratio between mutual inductance and self-inductance can be used as
below:
M
kpffiffiffiffiffiffiffiffiffiffi ð2:3Þ
L1 L 2
P− S−
The common ways to realize integrated transformers are illustrated in Figs. 2.5, 2.6,
and 2.7, which offer different tradeoffs on self-inductances, magnetic coupling
coefficient, inter-coil and coil-to-substrate capacitances, self-resonant frequencies,
and chip area [5]. Here, all the layouts are based on the differential configurations
since they are commonly used in VCOs and frequency dividers with balanced
differential outputs.
Figure 2.5 shows an interleaved transformer layout. Both the primary and
secondary coils are implemented with the same metal layer. As for on-chip inductor
design considerations [2], the thick top metal layer is typically used for maximum
quality factor Q and high self-resonant frequency because it has much smaller
square resistance than other metal layers and far away from the low resistance
substrate in CMOS process. When the metal traces need to be crossed over, the
lower metal layer can be used as a bridge. Since the interleaved configuration
allows large common periphery between the primary and secondary coils, it can
10 2 Transformer Design and Characterization in CMOS Process
k2L1
Ideal
P− S−
S+ S−
I1 i2
i1 i2
P+ S+ S− P− P+ P−
I1 I2 I1
P+ k S+ P+ S+
k
L1 L2 L1 L2
P− S− P− S−
I2
Fig. 2.4 Transformers with different coupling directions and their corresponding schematic
symbol using the dot convention
P+ S+ S− P−
2.2 Transformer Layout 11
P+ S+ S− P−
P+ S+ P− S− Metal
b
Trace
Dielectic
Dielectic
Substrate
12 2 Transformer Design and Characterization in CMOS Process
Basic considerations and guidelines for design, simulation, layout, and character-
ization of integrated transformers are mostly the same as those for on-chip induc-
tors, which have been well described in many references [2, 3] and will not be
repeated here. In the following section, only critical differences unique for inte-
grated transformers are summarized and highlighted.
As illustrated in Fig. 2.8, a typical design and characterization flow of integrated
transformers is summarized as below:
2.3 Transformer Measurement and Characterization 13
Electrical
Step 1:
Parameters
Fast
Step 2:
Simulation
Step 3: Accurate
Simulation
Simulation Unsatisfied
Results Circuit
Calibration Simultion
Satisfied
Testing
Step 5:
Structure
Step 6: Measurement
Unmatched Compared
with the
Simulation
Matched
End
Step 1: Obtain the required electrical parameters of the transformer such as self-
inductance, quality factor, and coupling coefficient from either calculation or
simulation of the targeted transformer using equivalent circuit models.
Step 2: At the beginning, the physical parameters of the transformer can be
quickly estimated and optimized for a given transformer structure by using a fast
simulator such as ASITIC [6]. In the optimization, different layout configurations
can be considered, from which the physical parameters such as the number of turns,
the diameter, metal width, and metal space can be adjusted. Since fast simulators
usually overestimate the quality factor Q, the relative trend of the quality factor
from different parameter combinations is more useful than its absolute value as a
quick reference for optimization.
14 2 Transformer Design and Characterization in CMOS Process
Step 3: After obtaining the physical parameters from a fast simulation, the
transformer can be further simulated by using more accurate electromagnetic
(EM) simulator such as the ADS Momentum [7] or HFSS [8]. Usually the simula-
tion results are in the formats of S parameters. To compare with the design goals,
the simulated S-parameter data need to be converted into the Z-parameters using
the following equations [9]:
where Z0 is impedance of the ports used in the simulation. With the Z-parameters,
the following equations can be employed to obtain the electrical parameters of the
transformer:
ImðZ11 Þ ImðZ22 Þ
L1 ¼ and L2 ¼ ð2:5aÞ
ω ω
ImðZ11 Þ ImðZ22 Þ
Q1 ¼ and Q2 ¼ ð2:5bÞ
ReðZ11 Þ ReðZ22 Þ
ImðZ21 Þ
k ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð2:5cÞ
ImðZ11 Þ ImðZ22 Þ
where ω ¼ 2πf. At this stage, the physical parameters can be further fine-tuned to
obtain the optimized design that can best satisfy the requirements.
Step 4: After the physical parameters of the transformer are fixed, the lumped
model as shown in Fig. 2.9 can be used for circuit simulation. This lumped model is
based on the wideband inductor model from [10], which merges the π models from
[11] and [12] and the substrate-coupled model from [13]. Here, the self-inductance
and the ohmic loss are modeled by components L1/L2 and r1/r2, while the parasitic
capacitance and the resistive loss of the substrate are modeled by Cox1/Cox2, Csub1/
Csub2, and Rsub1/Rsub2. The magnetic coupling and capacitive coupling between the
two coils are modeled by k and CC, respectively, and the capacitive coupling
between the metal traces in the same coil is modeled by Cm1/Cm2. The substrate-
coupled network made of Led1/Led2 and Red1/Red2 models the substrate losses due to
the eddy current which is increased with frequency. The model parameters are
extracted from and fitted to the simulated S-parameter data by using optimizer and
fitting tools. Simulations can be used to ensure that the frequency response of the
2.3 Transformer Measurement and Characterization 15
Cm2
CC k k CC
Cm1
Fig. 2.9 A wideband transformer model for parameter extraction and circuit simulation
model can match well the EM simulation results over a wide frequency range. The
transformer model can then be directly used in the time-domain or frequency-
domain transistor-level simulation, which enables complete evaluation of the
circuit performance. In practice, several iterations with the whole procedure
repeated may be necessary to fine-tune the physical and electrical parameters of
the transformers until the circuit specifications are satisfactorily met.
Step 5: The transformer testing structure as shown in Fig. 2.10a and its
de-embedded structures as shown in Figs. 2.11a and 2.12a can be laid out and
fabricated for measurement, characterization, and comparison with the simulation
results. The de-embedded open and short structures are employed for de-embedding
purpose to eliminate the impacts from the testing PADs and the parasitic metal
traces connecting between the transformer core and the testing PADs. For simplic-
ity, the single-ended testing structures with one port of the primary and secondary
coils being directly connected to the ground plane are considered here. If a 4-port
network analyzer is available, the fully differential testing structures can be
constructed in a similar way. The de-embedding principles and procedures in
Step 6 can also be applied to the differential testing structures.
16 2 Transformer Design and Characterization in CMOS Process
a b
Y3
Y1 DUT Y2
G
G
Z3 Z4
Port1
Port2
S
Ground Plane
G
Fig. 2.10 (a) Layout and (b) equivalent circuit of the transformer testing structure
a b
Y3
G
Port1 Port2
Z1 Z2
Port1
Port2
S
Y1 Y2
Ground Plane
Z3 Z4
G
Fig. 2.11 (a) Layout and (b) equivalent circuit of the open de-embedded structure
a b
Y3
G
Port1 Port2
Z1 Z2
Port1
Port2
S
Y1 Y2
Ground Plane
Z3 Z4
G
Fig. 2.12 (a) Layout and (b) equivalent circuit of the short de-embedded structure
and then converting YDE1 to ZDE1. So ZDE1 only contains the information of
parasitic parameters Z1 to Z4.
2. Open de-embedding for measurement data of the transformer testing structure.
According to the equivalent circuits for the transformer testing structure and the
open de-embedded structures as shown in Figs. 2.10b and 2.11b, the effect of
parasitic parameters Y1 to Y3 can be removed by subtracting Yopen from Yraw:
YDE2 ¼ Yraw Yopen ð2:8Þ
G
G
on different sides: (a) the
transformer testing
Port2
Port1
structure, (b) the open
S
S
de-embedded structure, and
(c) the short de-embedded DUT
structure
G
G
Ground Plane
G
G
Port2
Port1
S
S
G
G
Ground Plane
c
G
G
Port2
Port1
S
S
G
G
Ground Plane
Other documents randomly have
different content
“That’s her; who could have the heart to do her a wrong? Ah; she
is coming in here.”
The door was thrown open, and the singer stood upon the
threshold like a picture in a frame—a beautiful picture, too. Theresa
Van Curter was a rare type of her style of beauty—the blonde. Her
fair hair, lustrous and waving, was put back from a white forehead,
and confined at the back with an antique comb; her dress was
suited to the station in which she was placed, partaking something
of the Indian character, and giving free play to her limbs, a broad
hat, which she had been wearing in her stroll through the forest,
was swung upon her arm, while her hand clasped a bouquet of wild
flowers she had gathered. She started in some surprise at the
appearance of Boston, and then, dropping the flowers and hat to the
floor, sprung forward.
“Oh, sir, you here! Have you any news?”
She paused in some confusion.
“You needn’t go on,” said Boston, “I never keep a lady waiting. I
have a letter for you.”
Theresa put out her hand quickly.
“It must be from him!”
“Yes, it’s from him. Your father tried hard to find it. He would give
me both Jerusalem and Jericho if he knew I had it. You see I
calculated on being searched, and hid the paper.”
“You did?”
“Yes, I did. Have you got such a thing as a knife around here?
Thank you, Katrine. What a famous little house-keeper you’ll make,
having every thing so handy about you! Take hold of my old cap and
help me.”
A few moments’ work about the lining of the old hat which the
hawker had worn revealed a letter, which he took and handed to
Theresa. She turned away to the window, and read it hastily. A
shade passed over her fine face as she read.
“Is he well?” she asked, turning to Boston, who was engaged in a
flirtation with Katrine.
“Oh, yes, ma’am. You see he is out of spirits on your account, and
that runs him down some. But he is hearty. Just send him a cheery
word, and all will be well in the twinkling of an eye.”
“I am going to my room now, and shall write an answer to this.
You must remain until I come back. I shall not be long.”
She hurried away quickly, leaving Boston with Katrine—and they
sat down by the casement. They quarreled, and “made up” again,
several times, before Theresa appeared with an answer to the note.
“I have a little to say to you. Your father took me to-day, and
made me confess that I had a message to you.”
“Oh dear! You did not show him that letter?”
“Not a bit of it. But I told him that the message was verbal, and
gave him one of my own making up. Sounded natural enough.
Faithful unto death, and that sort of stuff. You understand.”
“And did not Willie send any such message to me?”
“A thousand; but I couldn’t think of half he said, if I were to spend
a week in meditation on the subject. You will take them all for
granted.”
“I fancy that Willie had better change his messenger,” said
Theresa, with a pout. “I am sure he might do better.”
“I am sorry to say that I think you are wrong,” replied Boston,
coolly stroking his beard. “There ain’t another man in the five
provinces that would do for you what I’ve done, time and again.”
“I am sorry I said that, Boston,” said Theresa, relenting quickly. “I
know you are faithful and true, but you ought to remember. Was my
father very angry?”
“Very particularly angry,” replied Boston. “Looked as if he wanted
to eat all the tribe of Yankees, beginning with me.”
“Was he angry at me?”
“I calculate he was. I don’t want no one to be angrier with me, I
guess. He was awful mad.”
“Then you had better go away. But first open your pack and let
me get what I need. We have waited a long time for you.”
“That’s because you can trust me. You know that, though I will
beat Dutch men sometimes, I never try to beat women.”
“What a twister,” cried Katrine.
“Now don’t you put in at all, Katrine. I won’t have it. Let me trade
with Miss Theresa in my own way. You know I won’t try to cheat
her.”
“But you do some women.”
“In trade I might. You stop talking, or the dress I am going to sell
you will fall to pieces in washing.”
The girl was bending over the pack when the commandant
entered. He looked a little angry when he saw the peddler.
“Don’t attempt to ply your trade here, sir. Go elsewhere.”
“Why, squire, as to that, the way I look at it is this: You gave me
two days to trade, and you didn’t say where I should go in particular.
You didn’t buy any thing, and I thought your daughter might want a
few traps.”
“Where do you intend to pass the night?”
“I don’t know. But surely some one will be glad to entertain me,
and take some of my wares in consideration. I’ve picked up a good
many furs since I came out here, and they are getting heavy. I can’t
travel far in a day.”
“You should have a horse,” said Theresa, looking up from the
pack, which she was turning over after a woman’s fashion.
“I did have one when I came, but old Paul Swedlepipe wouldn’t
take ‘no’ for an answer, but would have him.”
“I’ll wager my commission that he paid for the horse,” said Van
Curter, with a laugh. “How much did he give you?”
“Seventy-five guilders. I look upon it in the light of a praiseworthy
action—giving that hoss away.”
“Giving it away! S’death, man, I have a dozen horses, and you
may have the best of them for seventy-five guilders.”
“I’ll take a look into your stable before I go away,” said Boston. “In
the mean time, I’ve got something I want you to look at.” He
tumbled over the wares and took out a pair of heavy spurs. “Now
look at that,” he cried, in a tone of exultant admiration. “Did you
ever, in your born days, see sech a pair of spurs as that? No you
didn’t, so you needn’t say it. I don’t say that they are the best pair
of spurs in the Colonies, but I put it to you, squire, can you put your
finger upon a pair as good, anywhere? If you can, I should be proud
to know it.”
Van Curter took up the spurs and looked at them closely.
“Now tell me,” said he, “where is the cheat in this pair of spurs. I
take it for granted that there is such a thing about it, since a Yankee
brought them. Is it in the price, or in the articles themselves?”
“Oh, as to that,” replied Boston, with an air of injured innocence,
“I don’t say any thing. You will have it that there is a cheat in every
thing I offer for sale; but, if there is one there, you can’t find it.”
Van Curter laughed again.
“Come now,” he said, “I am willing to take the spurs, and at your
price, too, if you will tell me just where the cheat is to be?”
“You will take them any way?”
“Yes.”
“Then I’ll tell you; or, rather, it won’t be necessary to tell you any
more than the price.”
“And what is the price?”
“Forty guilders.”
“Hein!” shouted Van Curter, breaking into Dutch. “Do you mean,
seriously and gravely, to ask me forty guilders for a pair of spurs not
worth ten?”
“You wanted to know where the cheat was—in the spurs or the
price. You’ve got it. It’s in the price.”
“Der tuyvel! Hold; here is your money. And now take away your
pack, or you will ruin my house. Go quickly.”
“I was thinking to wait,” said Boston, coolly buttoning up the cash
in his breeches-pocket, “until the lady has made her selections; she
don’t seem to have finished.”
“Make your purchases quickly, Theresa, and come with me. I wish
to speak with you. Do not delay.”
Theresa gathered up her purchases and demanded the price. He
gave such a moderate one, even for him, that Van Curter was
astonished, and made no attempt to make the price less.
“You have some conscience yet, Bainbridge,” he said. “Here is
your money. Come, Theresa.”
The girl followed him from the room, casting a glance back at the
peddler, who had stooped over his pack, and was throwing out
various articles, at the bidding of Katrine.
“Do you know what I will bring from Boston when I come again?”
said he.
“No,” said Katrine, with a smile. “What?”
“A ring and a minister.”
“What for?” asked Katrine, in sublime unconsciousness.
“If you don’t know now you will know then,” was the answer.
“You’d better have this dress made up against that time.” With this
he kissed her again, arranged his pack, and left the house, making
his way back to the house of Paul Swedlepipe.
CHAPTER IV.
BOSTON “SHEATS” THE LEAN DUTCHMAN,
AND TURNS UP IN HIS REAL CHARACTER.
Our website is not just a platform for buying books, but a bridge
connecting readers to the timeless values of culture and wisdom. With
an elegant, user-friendly interface and an intelligent search system,
we are committed to providing a quick and convenient shopping
experience. Additionally, our special promotions and home delivery
services ensure that you save time and fully enjoy the joy of reading.
textbookfull.com