▪​ When data are being put in or taken out of the 8237’s

registers, the 8237 is a slave it receivers 16-bit addresses with

the 12 MSBs of those addresses determining whether or not
the chip is selected and the 4 LBSs being used fro internal
addressing.

▪​ When both HRQ and CS are low, the 8237 becomes a slave
with the IOR and IOW being the input control pins. The CPU
can read from or write to the internal registers of the controller
by activating IOR or IOW.

▪​ The AEN, which is active when the controller is-a master and
is outputting an address, is 0 while the system is
communicating with the controller’s registers
▪​ If the controller is the master, then it must supply the bus
 address. When it is master it puts the low-order byte of the
address on the pins A7-A0 and the high­ order byte on
DB7-DB0, and sets AEN to l.

▪​ With AEN = 1, the outputs of the external address latch are

enabled, thereby allowing the upper address byte to be put on
the A15-A8 lines.
▪​ The HRQ signal is sent to the cpu and upon taken ack (HLDA)
the DMA controller transfer data
2.

Key Factors in Memory Design

Memory design is based on several important factors that impact its
efficiency, performance, and cost-effectiveness. These factors
include cost, capacity, speed, power consumption, reliability, and
volatility. Below is a detailed explanation of each criterion:

1. Cost
The cost of a memory module consists of two components:
●​ Overhead Cost (Fixed Cost):​

○​ This cost does not depend on the size of the memory

module.
○​ It includes the cost of support and interface electronics
used in the module.
○​ The power supply design and the number of pin
connections also contribute to overhead cost.
●​ Incremental Cost (Variable Cost):​

○​ This cost depends on the size and capacity of the

memory module.
○​ It is mainly determined by the price of memory chips.
○​ More memory capacity leads to higher incremental
costs.
To minimize costs, it is generally better to use fewer memory
modules with larger bit capacities. This reduces the need for extra
support electronics and simplifies power supply design.

2. Capacity
The capacity of memory refers to the amount of data it can store. It
is usually measured in bits or bytes. The memory size is determined
by the number of addressable locations (words) and the number of
bits stored in each location.
For example:
●​ A 4K × 8 memory module contains 4,096 words, with each
word storing 8 bits (1 byte).
To efficiently use memory, designers try to maximize storage while
minimizing cost and power consumption.

3. Speed
Memory speed is measured by access time, which is the delay
between receiving an address input and providing the
corresponding data output. Faster memory allows a system to
process data more quickly.
●​ Factors affecting speed:
○​ Technology used: High-speed memory requires
advanced transistors, which take up more chip space.
○​ Access time: Faster access time leads to improved
system performance.
○​ Bipolar technology: Used for high-speed memory but
consumes more power.
To achieve high speed while maintaining cost efficiency, designers
often use a mix of different memory types, such as SRAM for
cache memory and DRAM for main memory.

4. Power Consumption
Power consumption is crucial, especially in battery-operated
systems (e.g., space probes, mobile devices). Different memory
technologies consume different amounts of power:
●​ CMOS (Complementary Metal-Oxide Semiconductor)
Technology:​

○​ Used in low-power applications.

○​ Requires more space per memory cell.
○​ Balances power efficiency and capacity.
●​ HMOS (High-Density MOS) Technology:​

○​ Offers a compromise between speed, power

consumption, and capacity.
○​ Used in many modern memory chips.
Minimizing power consumption is especially important for
applications that rely on limited energy sources, such as
solar-powered devices.

5. Reliability
Memory reliability depends on:
●​ Number of solder connections and board complexity:​

○​ Fewer solder joints reduce the risk of failure.

○​ Simpler board designs improve long-term reliability.
●​ IC (Integrated Circuit) Testing:​

○​ Once a memory chip is tested, it becomes highly

reliable.
○​ Fewer components on a memory module improve overall
reliability.
Reliability is critical for applications where memory failure can
cause significant problems, such as in medical devices or
aerospace systems.
6. Volatility and Access Capability
Memory is classified as volatile or non-volatile based on whether
it retains data after power loss.
●​ Volatile Memory (RAM):​

○​ Loses stored data when power is turned off.

○​ Requires backup power if data needs to be preserved.
●​ Non-Volatile Memory (ROM):​

○​ Retains data even after power is turned off.

○​ Used in firmware storage because of its stability.
○​ More resistant to noise and external interference.
○​ Less expensive and offers higher cell density.
For most systems, ROM is preferred whenever possible due to
its reliability, lower cost, and ability to store permanent data.

Conclusion
Memory design requires balancing cost, speed, power, reliability,
and volatility to create an efficient and cost-effective storage
solution. High-speed memory is more expensive and consumes
more power, while low-power memory sacrifices speed and
capacity. Choosing the right memory type depends on the
application’s needs—whether it requires fast processing (e.g.,
cache memory), large storage (e.g., DRAM), or long-term data
retention (e.g., ROM).
Q.3 Here's a simplified and well-organized answer based on your
Microprocessors Lecture 11,12 PDF:

Basic Static RAM (SRAM) Organization and Its Operation

1. What is Static RAM (SRAM)?

●​ SRAM (Static Random-Access Memory) is a type of
memory that stores data using flip-flop circuits made of
 transistors.
●​ Unlike Dynamic RAM (DRAM), it does not require
refreshing, meaning it retains data as long as power is
supplied.
●​ SRAM is faster and more reliable than DRAM but requires
more space and is more expensive.
●​ Used mainly for cache memory due to its high speed.

2. Organization of Static RAM

 ●​ An SRAM chip consists of a matrix (array) of memory cells.
●​ Each memory cell is made up of six MOS transistors
arranged as a flip-flop circuit.
●​ The organization is typically described as M × N, where:
○​ M = Number of words (memory locations).
○​ N = Number of bits stored per word.
●​ Example: A 4K × 8 SRAM stores 4,096 words, each
containing 8 bits (1 byte).

3. Operation of SRAM
Write Operation (Storing Data)
1.​The CPU sends an address to select a memory location.
2.​The Write Enable (WE) signal activates.
3.​The data to be stored is placed on the data bus.
4.​The selected memory cell stores the data using its flip-flop
circuit.
5.​Once stored, the data remains unchanged until a new write
operation occurs.
Read Operation (Retrieving Data)
1.​The CPU sends an address to select a memory location.
2.​The Read Enable (RE) signal activates.
3.​The stored data is placed on the data bus and sent to the
processor.
4.​The read operation does not erase the data from memory.

4. Advantages & Disadvantages of SRAM

✅ Advantages:
●​ Very fast (low access time).
●​ No need for refreshing like DRAM.
●​ More reliable due to stable storage mechanism.
❌ Disadvantages:
 ●​ Requires more transistors per cell, making it larger and
more expensive.
●​ Consumes more power than DRAM.
●​ Limited in size compared to DRAM.

Conclusion
SRAM is a high-speed, reliable memory mainly used for cache
memory in computers. It stores data using flip-flop circuits,
making it faster but more expensive than DRAM. The write and

🚀
read operations allow data to be stored and retrieved efficiently
without requiring constant refreshing.
Q.4

❖​The sum of the access time and read recovery time is the memory
read cycle time.
❖​ This is the time needed between the start of a read operation and
the start of the next memory cycle.
❖​The memory write cycle time can be similarly defined and may be
different from the read cycle time.
❖​Figure 10-7(a) illustrates the timing of a-memory read cycle.

❖​The address is applied at point A, which is the beginning of the read

cycle, and must be held stable during the entire cycle.
❖​In order to reduce the aceess time, the chip enable Input should be
applied before point B .
❖​ The data output becomes valid after point C and remains valid as
long as the address and chip enable inputs hold. The R/W control
input is not shown in the timing diagram for the read cycle, but
should remain high throughout the entire cycle.