Addition in binary system

• The 4 basic rules of adding binary digits (or bits)

are:

• For example, add binary 11 to binary 1:

Binary subtraction
The 4 basic rules for subtracting bits are:
0−0=0
1−=0
1−0=1
10 − 1 = 1
Binary multiplication
The 4 basic rules for multiplying bits are:
00=0
01=0
10=0
11=1
Binary division
Perform the following binary division:
(a) 110  11 (b) 110  10
Solution:
 Axiom Addition Multiplication
Commutative Law A+B=B+A A · B = B· A
Associative Law A+(B+C)=(A+B)+C A(BC) = (AB)C
Distributive Law A(B+C)=AB+AC (A+B).(A+C)=A+BC
Identity A + 0 =A A·1=A
Null A+1=1 A·0=0
Idempotency A+A=A A·A=A
Complementary A + A’ = 1 A · A’ = 0
Involution (A’)’ = A
Other Basic Rules of Boolean
Algebra
⚫ There are other basic rules of Boolean algebra
that can be derived from the axioms in the
previous table.
A + AB = A
A + A’ B = A + B
(A + B)(A + C) = A + B C
DeMorgan’s Theorem
⚫ DeMorgan’s Theorem can be used to convert a
complement of an AND operation of two variables X
and Y into an OR operation of the individual
complement of X and Y, or vice versa, as follows:

⚫ It can also used to convert the complement of an OR

operation of two variables X and Y into the AND of
individual complement of X and Y, or vice versa, as
follows:
 The Sum of Products (SOP)
• The Boolean expressions in the previous slide
examples are written in the form called the sum of
products.
• When two or more product terms are summed by
Boolean addition, the resulting expression is a sum-of-
products (SOP).
• For example, AB + ABC
ABC + CDE + B’CD’
are all sum of products (SOP).
 The Product of Sum (POS)
• When two or more sum terms are multiplied, the
resulting expression is a product-of-sums (POS).
• For example, (A’ + B)(A + B ‘ + C)
(A’ + B’ + C’)(C + D’ + E)(B’ + C + D)
A’(A + B’ + C)(B’ + C’ +D)
• Note that (A + B + C)’ is not a POS because in a POS
a single overbar cannot extend over more than one
variable.
The 3-variable and 4-variable K-map

• The 4-variable K-map

• The 3-variable K-
map
 Implicants, Prime implicants and
Essential Prime implicants
Implicants: An implicant is a product/minterm term in Sum of
Products (SOP) or sum/maxterm term in Product of Sums (POS)
of a Boolean function.
Prime Implicants: A group of squares or rectangles made up of a
bunch of adjacent minterms which is allowed by the definition
of K-Map are called prime implicants(PI) i.e. all possible groups
formed in K-Map.
Essential Prime Implicants: These are those subcubes(groups)
that cover at least one minterm that can’t be covered by any
other prime implicant. Essential prime implicants(EPI) are those
prime implicants that always appear in the final solution.
Seven-Segment Decoder a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
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Binary• Half
AdderAdder x
x S
HA + y
• Adds 1-bit plus 1-bit y C ───
• Produces Sum and Carry C S

x y C S
0 0 0 0
x S
0 1 0 1
1 0 0 1
1 1 1 0 y C

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 x
Binary• Full
Adder
Adder x S
+ y
+ z
• Adds 1-bit plus 1-bit plus 1-bit y FA
z C ───
• Produces Sum and Carry C S

y
x y z C S 0 1 0 1
0 0 0 0 0 x 1 0 1 0
0 0 1 0 1 z
0 1 0 0 1 S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0 y
1 0 0 0 1 0 0 1 0
1 0 1 1 0 x 0 1 1 1
1 1 0 1 0 z
1 1 1 1 1 C = xy + xz + yz 14 / 65
• Carry propagation
• The sum and the output carry of any stage cannot be
produced until the input carry occurs; this causes a time
delay in the addition process,
• (A1, B1, C1) → C2 → C3 → C4 → (C5, S4)

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Magnitude Comparator
• Compare 4-bit number to 4-bit number

x3 = A3 B3 + A3 B3 A3A2A1A0 B3B2B1B0
x2 = A2 B2 + A2 B2
Magnitude
x1 = A1 B1 + A1 B1 Comparator
x0 = A0 B0 + A0 B0
A<B A=B A>B
( A = B) = x3 x2 x1 x0
( A  B) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
( A  B) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
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Decoders
• Binary (2-to-4 Line) Decoder
Y3

y3 Y2

Decoder
I1

Binary
y2
y1 Y1
I0 y0
Y0

I1 I 0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
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Decoders
• Y3

Y3

Decoder
I1 Y2

Binary
Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y 3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
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Decoders
• Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0 I1 I0 Y 3 Y 2 Y 1 Y 0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y1
Y3 Y3
Decoder

Decoder
I1 I1
Binary

Binary
Y2 Y2 Y0

Y1 Y1
I0 Y0 I0 Y0 I1
I0

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Decoders
• 3-to-8 Line Decoder Y7 = I 2 I1 I 0
Y6 = I 2 I1 I 0
Y7 Y5 = I 2 I1 I 0
Y6
Y5 Y4 = I 2 I1 I 0

Decoder
Binary
I2 Y4 Y3 = I 2 I1 I 0
I1 Y3
I0 Y2 Y2 = I 2 I1 I 0
Y1 Y1 = I 2 I1 I 0
Y0
Y0 = I 2 I1 I 0

I2
I1
I0
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Encoders
• Put “Information” into code Only one
• 2^N- input and N – output input
• For 2^N inputs, all out put will be high or low switch
should be
activated
at a time

1
x1
x3 x2 x1 y1 y0
x2 y1 0 0 0 0 0
2 Binary
Encoder 0 0 1 0 1
y0 0 1 0 1 0
x3
3 1 0 0 1 1

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Encoders
• Octal-to-Binary Encoder (8-to-3)
I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
I5

Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 = I 7 + I 6 + I 5 + I 4 I4
I3 Y1
Y1 = I 7 + I 6 + I 3 + I 2 I2
I1
Y0 = I 7 + I 5 + I 3 + I1 I0 Y0
22 / 65
 Implementation Using Multiplexers
(8:1)
• Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z

23 / 65
 Implementation Using Multiplexers
(8:1)
• Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
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 Example of Dynamic Hazard

• If the input state (x1 x2 x3) = ( 0 0 0), the steady

state output is f = 0. If the input state is (1 0 0), the
output is f = 1.
• Suppose that G3 and G5 have zero propagation
delays, and G1 switches faster than G2, which is
faster than G4.

25
 Example of Static 1 Hazard

• Initially the input state (x1 x2 x3) = ( 1 1 1). The output f = 1.

• Then input variable x2 is changed to 0. This change affects the top
AND gate directly and its input goes to 0.
• This change takes a little time to pass through the NOT gate, and
thus when the top AND gate outputs 0, the bottom AND gate is
still outputting 0. This causes the OR gate output to change from 1
to 0.
• Once the change has passed through the NOT gate, the bottom
AND gate outputs is 1, and the OR gate output will switch back to
1. 26
26
 Example of Static 0 Hazard
1

• Initially the input state (x1 x2 x3) = ( 0 0 0). The output f = 0.

• Then input variable x2 is changed to 1. This change affects the top
OR gate directly and its input goes to 1.
• This change takes a little time to pass through the NOT gate, and
thus when the top OR gate outputs 0, the bottom OR gate is still
outputting 1. This causes the AND gate output to change from 0 to
1.
• Once the change has passed through the NOT gate, the bottom
OR gate outputs a 0, and the OR gate output will switch back to 0.27
27
Logic Family

28
Logic Family

29
Logic Family

30
Logic Family

31
Logic Family

32
Logic Family

33
Logic Family

34
Logic Family

35
Latches
• SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
36
Flip-flop
• A flip-flop is a bistable (two stable states) logic
circuit that can store only one bit at a time, either a 1
or a 0.
• The output of a flip-flop indicates which bit it is
storing.
• An edge-triggered flip-flop changes state either at
the positive edge (rising edge) or at the negative
edge (falling edge) of the clock pulse and is sensitive
to its inputs only at this transition of the clock.

37
Truth Table of D flip-flop

• The operation of a negative edge-triggered D flip-flop are the

same as those of the positive edge-triggered device except
that the falling edge of the clock pulse is the triggering edge.
38
JK flip-flop
• When J is HIGH and K is LOW, the Q output goes
HIGH on the triggering edge of the clock pulse, and
the flip-flop is SET.
• When J is LOW and K is HIGH, the Q output goes
LOW on the triggering edge of the clock pulse, and
the flip-flop is RESET.
• When both J and K are LOW, the output does not
change from its prior state. It is in STORE operation.
• When both J and K are HIGH, the flip-flop changes
state. This is called TOGGLE mode.

39
T flip-flop
• The T flip-flop or Toggle flip-flop changes output
state at every active clock edge if the input T = 1.
• If T = 0, the output stays the same.
• T flip-flops are often used as counters.

40
 Timing Diagram of D flip-flop with PRESET and CLEAR
inputs
• When active-LOW PRESET = 0, the output of D flip-flop is SET (Q=1).
• When active-LOW CLEAR = 0, the output of D flip-flop is RESET or
CLEAR (Q=0).
• When active-LOW CLEAR and PRESET are both HIGH, normal
synchronous operation of D flip-flop takes place.

41
Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)

42
Asynchronous binary counter by negative-edge-triggered flip-flops
• We have to reverse the connections.
• Up count: Q output of present flip-flop is connected to T input of following flip-
flop.
• Down count: Q’ output of present flip-flop is connected to T input of following
flip-flop.
• Again, for counting up, a RESET is required and for counting down, a SET is
required before the counting starts.
• Note that counting sequence, propagation delay, and time period T are the same
as positive-edge-triggered cases for counting up and down.
FF0 Q0 FF1 Q1 FF0 Q0 FF1 Q1
Q Q Q Q
CLK T T CLK T T

Up counter Down counter

Trigger FF0 Trigger FF1
Trigger FF0 Trigger FF1
CLK 1 2 3 4 5 6
CLK 1 2 3 4 5 6
Q’
Q0(LSB)
Q0(LSB)
Q1(MSB)
Q1(MSB)
  T 2T 4T
  T 2T 4T
Up counter Down counter 43
n-bit asynchronous binary counter: generalization

Count
Control FF0 Q0 FF1 Q1 FF(n-2) Qn-2 FF(n-1) Qn-1
T Q T Q T Q T Q
CLK C C C C
CLR CLR CLR CLR
CLR
•Total delay time (called cumulative delay) from CLK
CLK to Qn-1 is n. Q0
•Total number of different states of the counter is 2n. Q1
•The period of Qn-1 waveform is 2nT, where T is the
period of clock signal. Qn-2
•If Q0 is the LSB (least significant bit) and Qn-1is Qn-1
the MSB (most significant bit), the maximum count tPHL tPD
in decimal is 2n - 1.

Frequency limitation in an n-bit asynchronous binary counter

The cumulative delay is n
Assume  = 10 ns and n = 4, then tPD = 4 x 10 ns = 40 ns.
Hence, the maximum frequency is 1/40ns = 25 MHz
44
 Synchronous counters
• Synchronous refers to events that have a fixed time relationship with each
other.

• A synchronous counter is one in which all the flip-flops in the counter are
clocked at the same time by a common clock pulse.

• Note that only JK or clocked T flip-flop is used because hold and toggle
modes are need for the counter operation.

45
 • Counters can be connected in cascade to achieve higher-modulus
operation. Cascading means that the last-stage output of one counter
drives the input of the next counter. e.g.

CLK Modulus-4 Modulus-8

Counter Counter
The overall modulus is 4 x 8 = 32

FF0 Q0 FF1 Q1 FF2 Q2 FF3 Q3

Q Q Q Q
CLK T T T T
CLR CLR CLR CLR

Mod-10

FF0 Q0 FF1 Q1 FF2 Q2 FF3 Q3 Mod-100

Q Q Q Q
T T T T
CLR CLR CLR CLR
Mod-10
Cascade counters 46
A generic shift register
A generic shift register
A generic shift register is shown in Fig SR1. Parallel in (Y)
Parallel in (Yi, i = 1, n): one input line for each Parallel out (X)
flip-flop with data to be entered into the register.
Parallel out (Xi, i = 1, n): one output line coming
from each flip-flop Q terminal. Serial in Serial out
Shift pulse (sometimes labeled CLOCK): a pulse n-bit
shift register
on this control line makes the binary data in the
register move over one cell simultaneously. Preset control
Serial in: data line feeding the first cell in the shift Shift pulse
Clear control
register; a bit enters on each shift pulse.
Serial out: data line from the Q terminal of the last Fig SR1: Generic shift register logic
flip-flop in the register; a bit exits on each shift symbol
pulse
Clear control: a pulse on this line drives all the
flip-flops in the register to logic 0.
Preset control: a pulse on this control line presets
certain flip-flops to logic 1, those with a logic 1 on
their parallel input line Yi.

47
 • The shift register may be operated in four modes: serial in and serial out,
Basic types of data movement in shift registers
parallel in and serial out, serial in and parallel out, or parallel in and parallel
out as shown in Fig below. The rotation modes are used to generate binary
sequence continuously.

Data in

Data Data Data Data Data

in out in out out
(a) Serial in/shift right/serial out (b) Serial in/shift left/serial out (c) Parallel in/serial out
Data in

Data
in

Data out Data out

(d) Serial in/parallel out(e) Parallel in/parallel out (f) Rotate right (g) Rotate left

48