355

Constraint Generation and Placement for Automatic Layout

Design of Analog Integrated Circuits
Margherita Pillan, Donatella Sciuto
Politecnico di Milano, Dipartimento di Elettronica e Informazione.
Piazza Leonard0 da Vinci. 3 2 . 2 0 1 3 3 Milano, ITALY.
ABSTRACT Furthermore, whenever the performances of the netlist with
extracted parasitic effects do not satisfy the required
Electrical performances of integrated circuits operating at constraints, no information can be derived on the areas
high frequencies, can be sigruficantly degraded by electrical which do not allow to reach the performance goals.
parasitics non intentionally introduced during the layout Therefore the strategy of layout post-processing for parasitic
design. We present here new tools for the automatic analysis should be abandoned.
constraint driven placement and routing of analog
integrated circuits. Furthermore we introduce a new To allow for an efficient design of analog integrated circuits
constraint generation program, based on AC analysis in the it is therefore necessary to upgrade existing CAD tools for
frequency domain. The constraints produced by this physical design in the sense that the placement and routing
program have been employed to drive the automatic layout phases must be driven by constraints controlling the
tools, during the experiments here reported. These programs introduction of electrically effective parasitics during the
automatically produce the layout of high performance layout design. Parasitics controlled in such design phases
integrated circuits, sigmiicantly reducing the electrically are the interconnect parasitics which are entirely dependent
effective parasitics due to finite length interconnections. on the type of placement and routing performed.
Different papers on the subject have appeared in literature
INTRODUCTION ([2], [3]). All papers emphasize the aspects of routing
Digital circuits have become the most used designs in the constraints, while we believe that constraints in the
world of electronic systems. Design tools for digital systems placement phase will give better results in terms of final
have been developed and stable solutions exist for the layout performances. All approaches base their analysis on
physical design phase [11. SPICE simulations, which makes simulation of distributed
However, the analog nabre of real signals requires the structures critical. Moreover, time domain circuit simulation
design of circuits for analog operations. Therefore, most is not very efficient and accurate whenever the steady state
electronic systems dealing with the real world environment circuit solution is required.
include at least A D , D/A converters, filters, operational Aim of this paper is to introduce an approach to the
amplifiers. Furthermore, in most cases, high frequency constraint driven automatic layout design of analog
processing can be better dominated with the design of integrated circuits. The system we present here operates in
analog circuits instead of digital signal processing devices. three phases: first constraints are generated for the
The design of analog circuits cannot be afforded with placement design tool, then the automatic cell placement is
existing CAD tools for digital design. Main reason is the performed by a constraint driven program, finally
difference in the physical design methodology; in analog constraints are produced for the routing phase. Our
design, components must be modelled in a detailed fashion approach, differently from most published papers, generates
since their electrical behavior affects deeply the final result. the placement and routing constraints, through AC phasor
In particular, parasitics introduced in the layout phase must analysis. In the frequency domain in fact it is relatively easy
be controlled in order to meet the specification to develop accurate models for distributed devices, even in
performances such as bandwidth, gain, noise figure. In presence of dispersion, coupling and loss effects ([4], [5]).
physical devices, non zero length interconnections can Furthermore, frequency domain circuit simulators [6]
modify node impedance and introduce delay and coupling produce efficient and accurate steady state analysis, and for
effects thus producing significant performance degradation this reason they are most suitable in linear and non-linear
especially in case of high fresuency applications. design of monolithic analog circuit operating at very high
In actual design of analog integrated circuits, the layout frequency.
phase requires a sigruScant amount of time and quite often The paper is organized as follows. Next Section introduces
designers must iterate the placement and routing operations the proposed approach to constraints generation for
more than once. In hct, if the extracted parasitic effects at placement, with the definition of a new algorithm. Section 3
the end of layout generation do not allow to satisfy the proposes a new algorithm for constraint driven automatic
design specifications, the layout must be modified. placement in a mcro-cellstyle, while the routing phase is

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 356

briefly explained in section 4. Examples on some sub circuits (graph branches). Parasitics are associated with
benchmark circuits show the effectiveness of the approach each circuit branch in order to evaluate their performance
proposed for analog circuits with a low level of integration. sensitivity to the introduction of non zero length
interconnections. In other words, our constraint generation
2. CONSTRAINTS GENERATION program, evaluates the electrical activity of each circuit
Most tools for the automatic layout generation of digital branch. We define electrical activity of a selected subcircuit
integrated circuits, are driven by general criteria, such as with respect to a single electrical performance, the
total chip area and total interconnection length maximum deviation from the ideal value of the
minimization. In the design of analog circuits, especially in performance, due to the parasitic introduction, evaluated
case of high performance applications, these goals can be of with respect to the specification tolerance attributed to that
second order importance when compared to the electrical particular performance. The electrical activity coefficients
requirements. For this reason, most programs presented in allow to single out those circuit branches that potentially
literature for the automatic placement and routing of analog can mostly af€& the final circuit performances, and that we
circuits, are dnven by electrical constraints expressing the design as critical. Critical subcircuits will have higher
dependence of the electrical performances on the parasitic priority during the layout design. While in constraints
elements introduced during the layout. generation for routing it is necessary to evaluate the
We present here a new tool for the automatic generation of influence of each single net segment on each circuit
constraints that can be applied to linear and non-linear performance, we can substantially reduce the problem
networks, at the end of the electrical synthesis and complexity by analyzing the global effect of parasitic
optimization phases, before the layout design, in order to introduction, in the network branches. Anyway, in
evaluate the dependence of each electrical circuit constraints generation for the placement phase, the analysis
performance, on the introduction of interconnection of the electrical activity of each single net segment would be
parasitics at each node. While interconnections responsible redundant and not signtficant.
of parasitic introduction, are actually drawn during the In the frequency domain, AC analysis is very fast, and the
routing phase, we demonstrated in our experiments, that the circuit performances can be efficiently evaluated for
total interconnection length can be maintained low only different parasitic values (i.e. interconnection estimated
when the device placement is optimized toward the net length), by a perturbation method; the estimated maximum
minimization. In fact, as it can be Seen in figure 1, a net length is evaluated by considering the circuit
placement configuration optimized versus the total area complexity, the dimension of the included devices and
occupation, can correspond to a very unfavorable routing statistical data on the technology.
solution. The placement of figure 1 has been performed by In analog circuits, sometimes, parasitics introduced at
Puppy, a simulated annealing based placement program for Merent nodes, reciprocally compensate their influence on
digital applications. The cost function governing the the finalcircuit performance. That is for instance the case of
placement algorithm includes terms expressing the total circuits including identical modules, repeated several times.
area occupation (main term), the total interconnection Our program investigates compensation phenomena, by
length and the device overlapping. On the other hand, when considering the simultaneous introduction of parasitics in
the placement is optimized in order to minimize at least the the most critical branches. Eventually, statistical sampling
most critical interconnections, a satisfactory routing can be employed to detect sigmficant coupling effects
solution can be more easily automatically performed. In between less critical branches.
several cases, and in particular for high frequency
applications, the electrical behavior of metal lines used as In figures2 we reported the different effects of the parasitics
interconnections, cannot be simply modeled in terms of introduction in a simple three stages microwave GaAs-
lumped capacitors, and distributed effects can not be MESFET amplifier operating in the 4-8 Gig& range.
neglected. In the frequency domain, transmission lines and Figure 2 examines the amplifier power gain. In particular it
microstrip discontinuities can be accurately and efficiently shows the effects of Werent length interconnections
described by close form equations [6]. Analytical expression introduced between the first stage active elements source
are also available, describing coupling effects and parasitics and ground.
produced by line discontinuities. Furthermore, steady state 3. THE PLACEMENT METHODOLOGY
linear and non-linear analysis in the frequency domain, are
rapid and accurate for most cases of interest. For these Circuit placement is automatically performed by a new
reasons, our approach for constraints generation, employs a constraint driven placement tool based on the well known
frequency domain, circuit simulator based on the Harmonic simuhted annealing optimization technique. Simulated
Balance Method. [6] annealing ([7]]) has been extensively employed in CAD
tools for digital applications and, in particular, in automatic
In our program, the first step of the constraint generation placement programs 181. In these programs the circuit
procedure consists of the specification of the circuit under placement is realized by generating several different
analysis in terms of a graph. The circuit graph only retains contigurations, and for each one a cost function is
non degenerate nodes and highlights the interconnection evaluatd, the final placement configuration is the one that
properties of the circuit. Furthermore, the graph minimizes the cost function. For rl selected configuration
specification of a circuit allows for a natural partitioning in

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 357

this cost function linearly depends on the total area appeared to produce second order effects on the electrical
occupation, cell overlapping area and total estimated performances of the circuit. Devices included in low
interconnection length; for each term an empirical weight sensitivity branches are progressively added till the total
coefficient must be given. In principle, the cost function inclusion of each device of the circuit Symmetry constraints
governing the placement could be more complex and can be taken into account in the placement phase by
include terms expressing electrical and technological applying Merent strategies. For instance, high priority can
constraints. However our experiments showed that, in order be attributed to cells which have to be positioned
to obtain realistic results, it is necessary to attribute very symmetrically by first placing one of the branches of the
large weight coefficients to the terms depending on the total symmetrical structure, then by mirroring it, thus obtaining
area occupation and cell overlapping parameters; in this the whole symmetrical module that will be treated in the
way the cost function results almost unaf€ected by the terms following as a single non-separable module.
expressing electrical constraints. In other words, in the Automatic placement results obtained by such an approach
design of analog IC's, the plain use of simulated annealing are characterized by the fact that all devices in the most
placement tools designed for digital applications, is not critical branches occupy neighbor sites: interconnection nets
convenient. The proposed methodology to analog circuits between these devices can be very short and, as a
placement is based on a iterative placement of the circuits consequence, parasitic introduction during the routing
blocks. The placement order is defined hierarchically phase can be minimized.
following the results of the constraints generation
algorithm. Each block is placed by applying the simulated 4. ROUTING AND EXPERIMENTAL RESULTS
annealing algorithm, modified in such a way to be After the circuit placement is performed, the final routing
effectively applied to analog circuits, allowing to obtain an phase must be performed. Several papers have been
optimized placement with respect to electrical parameters. presented in literature, proposing algorithms suitable for
Every time a placement has been performed the following automatic routing of analog integrated circuits ([9], [lo]).
iterations consider the most critical subcircuits, for which Some of these papers introduce constraintdriven algorithms
layout has been already performed, as single entities. This for circuit routing govemed by a cost function generated
hierarchical approach, which can be criticized as too during the previous constraint generation phase.
expensive in terms of complexity with respect to previously We started our routing experiments using two existing
proposed approaches, can be justified by considering the low programs written for digital applications, YACR and
level of integration of analog circuits which reduces in MIGHTY ([111). In fact, since following our approach, the
practical terms the analysis complexity, allowing to obtain circuit placement is optimized in order to minimize the
optimal results with respect to electrical constraints. critical interconnection length, we assumed that the routing
Let us detail the constraintsdriven placement methodology. problem could be solved using standard algorithms.
The system considers, at first, the circuit branches that Unfortunately these programs do not behave effectively for
were determined to be most critical during the previous analog circuits that are characterized by large channels and
constraint generation phase, that is, the branches for which small interconnection number; in this case in fact, they tend
parasitic introduction mostly affects circuit performances. to introduce unnecessary long paths and useless bents.
For each branch separately, the system performs the Therefore we modified the original algorithms by
automatic placement of the device cells, using a classical introducing a priority function associated with each net.
simulated annealing algorithm, whose cost function only Such fimction is employed together with the vertical
depends on three parameters: total area occupation, cell constraint graph which drives the rows occupation by the
overlapping, total estimated interconnection length. In nets. These modifications have provided a substantial
particular, the total length of interconnections is an improvement in the routing quality as shown in fig. 3.
important parameter in the cost function evaluation: some Nevertheless the results obtained are not completely
c o n f i rtions which would affect the electrical parameters satisfactory, and we are now defining a completely new
are m d e d a priori, even before evaluating the cost approach to the routing problem, based on the automatic
function. For instance, those configurations with an definition of a cost function expressing electrical and
overlapping greater than 20% of the total area occupied by a symmetry constraints. The main goal of this new approach
subcircuit (or the entire chip, in case of the final global is the exploitation of the analog circuit characteristics, such
placement) are discarded. Furthermore, the cost function as the low integration level and the placement optimization
includes a term which constrains the C O M ~ C ~ O ~of
S the sub
with respect to the minimization of the electrical
circuit to the rest of the network to lie on the devices interconnections.
boundaries. After the optimal placement of the critical In the new algorithm, after the definition of the symmetry
subcircuits has been completed, the global placement of the constraints, the critical nets are determined by considering
circuit is performed. The modules are constituted by the one net at a time. For each net the worst configuration with
critical sub circuits treated as non separable entities and by respect to performance degradation is determined by
the elementary cells belonging to those branches determined simulation. A net is considered critical if the performance
to be less critical by the constraints generation algorithm, degradation is higher than a predefined upper bound
i.e. the branches for which the introduction of parasitics (determined by the specification performance tolerance

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 358

range). For each critical net a cost function is then

established: it is composed by all performance variables
weighted by a coefficient. The weights are determined for
each critical net by considering the net criticality with
respect to the current performance variable and type of
tolerance allowed by such term. The higher the criticality
and the lower is the tolerance the larger is the weight
coefficient. Therefore, for each single net, the cost function
is a direct consequence of the performances degradation.
These terms can be inserted into a more general cost
function that drives the routing process, whose detailed
structure strictly depends on the chosen router. Typical
factors of such cost function include the occupied area and
the yield.
5. CONCLUDING REMARKS
In @s paper we detailed the different phases of the parasitic
conktrained layout generation methodology, by showing the
algorithms and the construction of the different cost
functions. The advantages of such an approach have been
practically shown on some circuit example. Figure 1:Exampleof layout generated with Puppy
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Figure 3 An example of layout performedwith the proposed tools

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