INPUT/OUTPUT

ORGANIZATION
M ODULE 4
Accessing I/O
Devices
 Accessing I/O devices

Processor Memory

Bus

I/O device 1 I/O device n

•Multiple I/O devices may be connected to the processor and the memory via a bus.
•Bus consists of three sets of lines to carry address, data and control signals.
•Each I/O device is assigned an unique address.
•To access an I/O device, the processor places the address on the address lines.
•The device recognizes the address, and responds to the control signals.
 Accessing I/O devices (contd..)
Memory mapped I/O & I/O mapped I/O

 I/O devices and the memory may share the same address
space:
 Memory-mapped I/O.
 Any machine instruction that can access memory can be used to
transfer data to or from an I/O device.

 I/O devices and the memory may have different address

spaces: (I/O mapped I/O)
 Special instructions to transfer data to and from I/O devices.
 I/O devices may have to deal with fewer address lines.
 I/O address lines need not be physically separate from memory
address lines.
 In fact, address lines may be shared between I/O devices and
memory, with a control signal to indicate whether it is a memory
address or an I/O address.

4
Accessing I/O devices (contd..)
Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device

•I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
•Data register holds the data being transferred to or from the processor.
•Status register holds information necessary for the operation of the I/O device.
•Data and status registers are connected to the data lines, and have unique addresses.
•I/O interface circuit coordinates I/O transfers.
 Accessing I/O devices (contd..)
 Rate of transfer to and from I/O devices is slower than the
speed of the processor. This creates the need for
mechanisms to synchronize data transfers between them.
 Program-controlled I/O:
 Processor repeatedly monitors a status flag to achieve the
necessary synchronization.
 Processor polls the I/O device.

 Two other mechanisms used for synchronizing data transfers

between the processor and memory:
 Interrupts.
 Direct Memory Access.
Interrupts
Interrupts
◦ In program-controlled I/O, when the processor continuously
monitors the status of the device, it does not perform any
useful tasks.
◦ An alternate approach would be for the I/O device to alert
the processor when it becomes ready.
◦ Do so by sending a hardware signal called an interrupt to the
processor.
◦ At least one of the bus control lines, called an interrupt-
request line is dedicated for this purpose.
◦ Processor can perform other useful tasks while it is waiting
for the device to be ready.
Interrupts - Example
Program 1 Program 2
COMPUTE routine PRINT routine

1
2

n lines are
ready j
here
j+1

•COMPUTE routine produces n lines of output to be printed on printer

•Printer accepts only one line of text at a time
•PRINT routine sends one by one line to printer
•After printing all n lines COMPUTE routine continues producing another n lines
 Interrupts - Example
Program 1 Program 2
COMPUTE routine PRINT routine
(Interrupt Service Routine)
1
2
j
Interrupt
occurs i
here
i+1

•Processor is executing the instruction located at address i when an interrupt occurs.

•Routine executed in response to an interrupt request is called the interrupt-service
routine.
•When an interrupt occurs, control must be transferred to the interrupt service routine.
•But before transferring control, the current contents of the PC (i+1), must be saved in a
known location.
•This will enable the return-from-interrupt instruction to resume execution at i+1.
•Return address, or the contents of the PC are usually stored on the processor stack.
Subroutine and Interrupt-Service Routine (ISR)
 Treatment of an interrupt-service routine is very
similar to that of a subroutine.
 However there are significant differences:
 A subroutine performs a task that is required by the calling
program.
 Interrupt-service routine and the program that it interrupts
may belong to different users.
 As a result, before branching to the interrupt-service
routine, not only the PC, but other information such as
condition code flags, and processor registers used by both
the interrupted program and the interrupt service routine
must be stored.
 This will enable the interrupted program to resume execution
upon return from interrupt service routine.
Interrupts – Context Saving
 Saving and restoring information can be done automatically
by the processor or explicitly by program instructions.
 Saving and restoring registers involves memory transfers:
 Increases the total execution time.
 Increases the delay between the time an interrupt request is
received, and the start of execution of the interrupt-service
routine. This delay is called interrupt latency.
 In order to reduce the interrupt latency, most processors
save only the minimal amount of information:
 This minimal amount of information includes Program Counter
and processor status registers.
 Any additional information that must be saved, must be
saved explicitly by the program instructions at the beginning
of the interrupt service routine.
Interrupts - Acknowledgment
◦ When a processor receives an interrupt-request, it must
branch to the interrupt service routine.
◦ It must also inform the device that it has recognized the
interrupt request.
◦ This can be accomplished in two ways:
◦ Some processors have an explicit interrupt-acknowledge
control signal for this purpose.
◦ In other cases, the data transfer that takes place
between the device and the processor can be used to
inform the device.
 Interrupts – Enabling
 Interrupt-requests interrupt the execution of a program, and may
alter the intended sequence of events:
 Sometimes such alterations may be undesirable, and must not be
allowed.
 For example, the processor may not want to be interrupted by the
same device while executing its interrupt-service routine.
 Processors generally provide the ability to enable and disable such
interruptions as desired.
 One simple way is to provide machine instructions such as
Interrupt-enable and Interrupt-disable for this purpose.
 To avoid interruption by the same device during the execution of
an interrupt service routine:
 First instruction of an interrupt service routine can be Interrupt-
disable.
 Last instruction of an interrupt service routine can be Interrupt-
enable.
Interrupts - Issues
 Multiple I/O devices may be connected to the processor and
the memory via a bus. Some or all of these devices may be
capable of generating interrupt requests.
 Each device operates independently, and hence no definite order
can be imposed on how the devices generate interrupt requests?
 How does the processor know which device has generated an
interrupt?
 How does the processor know which interrupt service routine
needs to be executed?
 When the processor is executing an interrupt service routine
for one device, can other device interrupt the processor?
 If two interrupt-requests are received simultaneously, then
how to break the tie?
Interrupts (Which Device)
Consider a simple arrangement where all devices send their
interrupt-requests over a single control line in the bus.
When the processor receives an interrupt request over this
control line, how does it know which device is requesting an
interrupt?
This information is available in the status register of the
device requesting an interrupt:
 The status register of each device has an IRQ bit which
it sets to 1 when it requests an interrupt.
Interrupt service routine can poll the I/O devices connected
to the bus. The first device with IRQ equal to 1 is the one
that is serviced.
Polling mechanism is easy, but time consuming to query the
status bits of all the I/O devices connected to the bus.
Vectored Interrupt
The device requesting an interrupt may identify itself
directly to the processor.
 Device can do so by sending a special code (4 to 8
bits) the processor over the bus.
 Code supplied by the device may represent a part of
the starting address of the interrupt-service
routine.
 The remainder of the starting address is obtained
by the processor based on other information such as Memory
the range of memory addresses where interrupt
service routines are located. 4002
85000
(Starting address of

Usually the location pointed to by the interrupting

ISR1)

device is used to store the starting address of the 4006 48040

interrupt-service routine.
(Starting address of
ISR2)

4010 96500
(Starting address of
ISR3)
Interrupts Nesting
Before the processor started executing the interrupt service
routine for a device, it disabled the interrupts from the device.
In general, same arrangement is used when multiple devices can
send interrupt requests to the processor.
 During the execution of an interrupt service routine of
device, the processor does not accept interrupt requests
from any other device.
 Since the interrupt service routines are usually short, the
delay that this causes is generally acceptable.
However, for certain devices this delay may not be acceptable.
Ex: Real time clock
 Which devices can be allowed to interrupt a processor
when it is executing an interrupt service routine of another
device?
Interrupts (contd..)
I/O devices are organized in a priority structure:
 An interrupt request from a high-priority device is accepted
while the processor is executing the interrupt service routine
of a low priority device.
A priority level is assigned to a processor that can be changed
under program control.
 Priority level of a processor is the priority of the program that
is currently being executed.
 When the processor starts executing the interrupt service
routine of a device, its priority is raised to that of the device.
 If the device sending an interrupt request has a higher priority
than the processor, the processor accepts the interrupt
request.
Interrupts (contd..)
Processor’s priority is encoded in a few bits of the processor
status register.
◦ Priority can be changed by instructions that write into the
processor status register.
◦ Usually, these are privileged instructions, or instructions that
can be executed only in the supervisor mode.
◦ Privileged instructions cannot be executed in the user mode.
◦ Prevents a user program from accidentally or intentionally
changing the priority of the processor.
If there is an attempt to execute a privileged instruction in the
user mode, it causes a special type of interrupt called as privilege
exception.
Interrupt- Priority
IN T R 1 INTR p
Processor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration

•Each device has a separate interrupt-request and interrupt-acknowledge

line.
•Each interrupt-request line is assigned a different priority level.
•Interrupt requests received over these lines are sent to a priority
arbitration circuit in the processor.
•If the interrupt request has a higher priority level than the priority of the
processor, then the request is accepted.
Simultaneous Interrupts
◦ Which interrupt request does the processor accept if it
receives interrupt requests from two or more devices
simultaneously?
◦ If the I/O devices are organized in a priority structure,
the processor accepts the interrupt request from a device
with higher priority.
◦ Each device has its own interrupt request and interrupt
acknowledge line.
◦ A different priority level is assigned to the interrupt
request line of each device.
◦ However, if the devices share an interrupt request line,
then how does the processor decide which interrupt
request to accept?
◦ Simple Solution - Polling scheme
Simultaneous Interrupts - Daisy chain
scheme
INTR
Processor

Device 1 Device 2 Device n

INTA

•Devices are connected to form a daisy chain.

•Devices share the interrupt-request line (INTR), and interrupt-
acknowledge line (INTA) is connected to form a daisy chain.
•When devices raise an interrupt request, the interrupt-request line is
activated.
•The processor in response activates interrupt-acknowledge (INTA).
•Received by device 1, if device 1 does not need service, it passes the signal
to device 2.
•Device that is electrically closest to the processor has the highest
priority.
 Interrupts - Priority groups
•When I/O devices were organized into a priority structure, each device had its own
interrupt-request and interrupt-acknowledge line.
Processor

IN T R 1 I NT R p
Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration

•When I/O devices were organized in a daisy chain fashion, the devices shared
an interrupt-request line, and the interrupt-acknowledge propagated through
the devices.
INTR
Processor

Device 1 Device 2 Device n

INTA
 Interrupts - Priority groups
A combination of priority structure and daisy chain scheme can also used.

INTR 1

Device Device
INTA1
Processor

IN T R p

Device Device
INTA p
Priority arbitration
circuit

•Devices are organized into groups.

•Each group is assigned a different priority level.
•All the devices within a single group share an interrupt-request line, and are
connected to form a daisy chain.
Direct Memory
Access
Data transfer between I/O devices and
Processor
Processor determines that the I/O device is
ready by:
(i) Polling a status flag in the device interface
(ii) Waits for the device to send an interrupt request

Overhead:
(i) Instructions are needed for incrementing the memory
address and keeping track of word count
(ii) Saving and restoring PC and other state information
Direct Memory Access
A special control unit may be provided to transfer a
block of data directly between an I/O device and the
main memory, without continuous intervention by the
processor.

 Control unit which performs these transfers is a part of the

I/O device’s interface circuit. This control unit is called as a
DMA controller.
 DMA controller performs functions that would be normally
carried out by the processor:
 For each word, it provides the memory address and all the
control signals.
 To transfer a block of data, it increments the memory addresses
and keeps track of the number of transfers.
Direct Memory Access (contd..)
 DMA controller can transfer a block of data from an external
device to the processor, without any intervention from the
processor.
 However, the operation of the DMA controller must be under the
control of a program executed by the processor. That is, the
processor must initiate the DMA transfer.

 To initiate the DMA transfer, the processor informs the DMA

controller of:
 Starting address
 Number of words in the block
 Direction of transfer (I/O device to the memory, or memory to the
I/O device)

 Once the DMA controller completes the DMA transfer, it informs

the processor by raising an interrupt signal.
Control registers in DMA
Status and
Control

IRQ Done
IE R/W

Starting
address

Word
count
Direct Memory Access
Main
Processor
memory

System bus

Disk/DMA DMA Keyboard

controller controller Printer

Disk Disk Network

Interface

•DMA controller connects a high-speed network to the computer bus.

•Disk controller, which controls two disks also has DMA capability. It provides two
DMA channels.
•It can perform two independent DMA operations, as if each disk has its own DMA
controller. The registers to store the memory address, word count and status and
control information are duplicated.
Block / Burst Mode
 Processor and DMA controllers have to use the bus in an
interwoven fashion to access the memory.
 DMA devices are given higher priority than the processor to
access the bus.
 DMA controller is provided by an exclusive capability to
initiate transfers on the bus, and hence exclusive access to
the main memory. This is known as the block or burst mode
 The entire block of memory is copied to the destination as a
single contiguous block.
 For the entire duration of the transfer, the CPU stays idle
and the DMA controller and the peripheral device gets
complete access to the system
Cycle stealing mode
 Processor originates most memory access cycles on the bus.
 DMA controller can be said to “steal” memory access cycles from
the bus. This interweaving technique is called as cycle stealing
 Data is transferred one byte at a time.
 The DMA controller, after transferring one byte of data,
releases control of the system buses
 Lets the CPU process an instruction and then requests access
to the bus by sending the bus request signal through the
control bus and then transfers another byte of data.
 This keeps going on until all the data has been transferred.
 The transfer rate is slower but it prevents the CPU from
staying idle for a long period of time.
Bus arbitration
 Processor and DMA controllers both need to initiate data
transfers on the bus and access main memory.
 The device that is allowed to initiate transfers on the bus at any
given time is called the bus master.
 When the current bus master relinquishes its status as the bus
master, another device can acquire this status.
 The process by which the next device to become the bus master is
selected and bus mastership is transferred to it is called bus
arbitration.
 Centralized arbitration:
 A single bus arbiter performs the arbitration.
 Distributed arbitration:
 All devices participate in the selection of the next bus master.
Centralized Bus Arbitration

B BS Y

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2
Centralized Bus Arbitration (cont.,)
• Bus arbiter may be the processor or a separate unit
connected to the bus.
• Normally, the processor is the bus master, unless it grants
bus membership to one of the DMA controllers.
• DMA controller requests the control of the bus by asserting
the Bus Request (BR) line.
• In response, the processor activates the Bus-Grant1 (BG1)
line, indicating that the controller may use the bus when it
is free.
• BG1 signal is connected to all DMA controllers in a daisy
chain fashion.
• BBSY signal is 0, it indicates that the bus is busy. When
BBSY becomes 1, the DMA controller which asserted BR can
acquire control of the bus.
Centralized arbitration (contd..)
DMA controller 2
asserts the BR signal.
Processor asserts
BR
the BG1 signal

BG1 BG1 signal propagates

to DMA#2.
BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.
Time
Distributed arbitration
 All devices waiting to use the bus share the responsibility of
carrying out the arbitration process.
 Arbitration process does not depend on a central arbiter and
hence distributed arbitration has higher reliability.
 Each device is assigned a 4-bit ID number.
 All the devices are connected using 5 lines, 4 arbitration
lines to transmit the ID, and one line for the Start-
Arbitration signal.
 To request the bus a device:
 Asserts the Start-Arbitration signal.
 Places its 4-bit ID number on the arbitration lines.
 The pattern that appears on the arbitration lines is the
logical-OR of all the 4-bit device IDs placed on the
arbitration lines.
Distributed arbitration
Distributed Arbitration
Start-Arbitration

Processor

0101 0111 0110 0111

DMA
controller DMA
controller
A B
Distributed arbitration
(Contd.,)
 Arbitration process:
 To request the bus a device:

 Asserts the Start-Arbitration signal.

 Places its 4-bit ID number on the arbitration lines.
 The pattern that appears on the arbitration lines is the logical-
OR of all the 4-bit device IDs placed on the arbitration lines.
 Each device compares the pattern that appears on the
arbitration lines to its own ID, starting with MSB.
 If it detects a difference, it transmits 0s on the arbitration
lines for that and all lower bit positions.
Distributed Arbitration
Start-Arbitration

Processor

0101 0111 0110 0111

DMA
controller DMA
controller
A B

Device A has the ID 5 - 0 1 0 1

Device B has the ID 6 - 0 1 1 0
Logical OR on the bus liens 0 1 1 1
Distributed arbitration
(Contd.,)
•Device A has the ID 5 and wants to request the bus:
- Transmits the pattern 0101 on the arbitration lines.

•Device B has the ID 6 and wants to request the bus:

- Transmits the pattern 0110 on the arbitration lines.

0101
0110
-------
0111

•Pattern that appears on the arbitration lines is the logical OR of the

patterns:

- Pattern 0111 appears on the arbitration lines.

Distributed Arbitration
Start-Arbitration

Processor

0100 0111 0110 0111

DMA
controller DMA
controller
A B

A - 0101
B - 0110
---------------------
Line - 0 1 1 1
Distributed arbitration
Arbitration process:

•Each device compares the pattern that appears on the arbitration lines to
its own ID, starting with MSB.
•If it detects a difference, it transmits 0s on the arbitration lines for that
and all lower bit positions.

•Device A compares its ID 5 with a pattern 0101 to pattern 0111

0101
0111
----------
0100
Device B compares its ID 6 with a pattern 0110 to pattern 0111
0110
0111
----------
0110
•This pattern is the same as the device ID of B, and hence B has won the
arbitration.
 Speed, Size, and Cost
 A big challenge in the design of a computer system is to provide a
sufficiently large memory, with a reasonable speed at an affordable
cost.
 Static RAM:
▪ Very fast, but expensive, because a basic SRAM cell has a complex circuit
making it impossible to pack a large number of cells onto a single chip.
 Dynamic RAM:
▪ Simpler basic cell circuit, hence are much less expensive, but significantly
slower than SRAMs.
 Magnetic disks:
▪ Storage provided by DRAMs is higher than SRAMs, but is still less than
what is necessary.
▪ Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
 Memory Hierarchy
Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing Increasing Increasing •Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory
of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk that will be used in the near future as
secondary close to the processor as possible.
memory
The Memory System
Cache Memories
 Cache Memories
 Processor is much faster than the main memory.
▪ As a result, the processor has to spend much of its time
waiting while instructions and data are being fetched from the
main memory.
▪ Major obstacle towards achieving good performance.
 Speed of the main memory cannot be increased beyond a
certain point.
 Cache memory is an architectural arrangement which makes
the main memory appear faster to the processor than it
really is.
 Cache memory is based on the property of computer
programs known as “locality of reference”.
Locality of Reference
 Analysis of programs indicates that many instructions in
localized areas of a program are executed repeatedly
during some period of time, while the others are accessed
relatively less frequently.
▪ These instructions may be the ones in a loop, nested loop or
few procedures calling each other repeatedly.
▪ This is called “locality of reference”.

 Temporal locality of reference:

▪ Recently executed instruction is likely to be executed again
very soon.
 Spatial locality of reference:
▪ Instructions with addresses close to a recently instruction are
likely to be executed soon.
 Cache memories
Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred from the

main memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the
cache.
• At any given time, only some blocks in the main memory are held in the cache.
Which blocks in the main memory are in the cache is determined by a
“mapping function”.

• When the cache is full, and a block of words needs to be transferred from
the main memory, some block of words in the cache must be replaced. This
is determined by a “replacement algorithm”.
 Cache hit
• Existence of a cache is transparent to the processor. The
processor issues Read and Write requests in the same
manner.

• If the data is in the cache it is called a Read or Write hit.

• Read hit:
▪ The data is obtained from the cache.

• Write hit:
▪ Cache has a replica of the contents of the main memory.
▪ Contents of the cache and the main memory may be updated
simultaneously. This is the write-through protocol.
▪ Update the contents of the cache, and mark it as updated by
setting a bit known as the dirty bit or modified bit. The
contents of the main memory are updated when this block is
replaced. This is write-back or copy-back protocol.
 Cache miss
• If the data is not present in the cache, then a Read miss or Write
miss occurs.

• Read miss:
▪ Block of words containing this requested word is transferred from the
memory.
▪ After the block is transferred, the desired word is forwarded to the
processor.
▪ The desired word may also be forwarded to the processor as soon as it is
transferred without waiting for the entire block to be transferred. This is
called load-through or early-restart.

• Write-miss:
▪ Write-through protocol is used, then the contents of the main memory
are updated directly.
▪ If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
Cache Coherence Problem
• Data transfers between main memory and disk occur
directly bypassing the cache.
• When the data on a disk changes, the main memory block is
also updated.

What happens if the data in the disk and main memory

changes and the write-back protocol is being used?
• In this case, the data in the cache may also have changed
and is indicated by the dirty bit.
• The copies of the data in the cache, and the main memory
are different. This is called the cache coherence problem.
• One option is to force a write-back before the main
memory is updated from the disk.
Mapping functions
 Mapping functions determine how memory blocks Main
memory Block 0

are placed in the cache. Cache Block 1

tag
Block 0
 A simple processor example: tag
Block 1
▪ Cache consisting of 128 blocks of 16 words each.
Block 127
▪ Total size of cache is 2048 (2K) words.
Block 128
▪ Main memory is addressable by a 16-bit address. tag
Main memory has 64K words.
Block 127 Block 129
▪
▪ Main memory has 4K blocks of 16 words each.

 Three mapping functions: Block 255

Tag Block Word
▪ Direct mapping 5 7 4 Block 256
▪ Associative mapping Block 257
Main memory address
▪ Set-associative mapping.

Block 4095
 Direct mapping
Main
memory Block 0 •Block j of the main memory maps to j modulo 128 of
Block 1
the cache. 0 maps to 0, 129 maps to 1.
Cache
tag •More than one memory block is mapped onto the same
Block 0
position in the cache. (0, 128, 256 … maps to 0)
tag
Block 1
•May lead to contention for cache blocks even if the
Block 127 cache is not full.
Block 128 •Resolve the contention by allowing new block to
tag replace the old block, leading to a trivial replacement
Block 127 Block 129
algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
Block 255
Tag Block Word - When a new block is brought into the cache,
5 7 4 Block 256 the next 7 bits determine which cache block
Block 257 this new block is placed in.
Main memory address
- High order 5 bits determine which of the possible
32 blocks is currently present in the cache. These
are tag bits.
Block 4095
•Simple to implement but not very flexible.
 Associative mapping
Main
memory Block 0 •Main memory block can be placed into any cache
Cache Block 1 position.
•Memory address is divided into two fields:
tag
Block 0
tag
Block 1 - Low order 4 bits identify the word within a block.
Block 127 - High order 12 bits or tag bits identify a memory
Block 128 block when it is resident in the cache.
tag
Block 127 Block 129 •Flexible, and uses cache space efficiently.
•Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
Block 255
Tag Word the need to search all 128 patterns to determine
Block 256
whether a given block is in the cache. (Associative
12 4

Block 257
Main memory address search)

Block 4095
 Set-Associative mapping
• Blocks of cache are grouped into sets.
Cache
Main
memory Block 0 • Mapping function allows a block of the main
tag
Block 0 memory to reside in any block of a specific set.
Block 1
Set 0 tag Block 1 • Divide the cache into 64 sets, with two blocks per
Block 2
set.
tag

Set 1 tag • Memory block 0, 64, 128 etc. map to cache set 0,
Block 3 Block 63 and they can occupy either of the two positions.
Block 64 • Memory address is divided into three fields:
tag
Block 126 Block 65 - 6 bit field determines the set number.
Set 63 - High order 6 bit fields are compared to the
tag Block 127 tag fields of the two blocks in a set.
• Set-associative mapping combination of direct and
Block 127 associative mapping.
Tag Set Word
Block 128 • Number of blocks per set is a design parameter.
6 6 4
- One extreme is to have all the blocks in one
Main memory address Block 129
set, requiring no set bits (fully associative
mapping).
- Other extreme is to have one block per set, is
the same as direct mapping.
Block 4095
• K-way Set-Associative Cache