Digital IC Design

Switching Characteristics and Interconnect Effects

Switching Characteristics and Interconnect Effects

See Kang and Leblebici Book
Digital IC Design

MOSFET Capacitance: (i) Oxide Related , (ii) Junction Capacitances

Digital IC Design

Switching Characteristics and Interconnect Effects

Cload = Cgd ,n + Cgd , p + Cdb,n + Cdb, p + Cint + Cg

Csb,n and Csb,p : no effect on transient behaviour since VSB is always zero
Cgs,n and Cgs,p : no effect since they always tied between input node to ground or power supply
Digital IC Design

Switching Characteristics and Interconnect Effects

First Stage CMOS Inverter With Lumped Output Load Capacitance

Digital IC Design

Switching Characteristics and Interconnect Effects

Delay Times

Propagation Delay: Input to output signal delay during high to low (ΓPHL) and low to high
(ΓPLH) transition
Digital IC Design

Switching Characteristics and Interconnect Effects

Delay Times

Average propagation delay: Average time

required for the input signal to propagate
through the inverter.

Average rise and fall time:

Digital IC Design

Switching Characteristics and Interconnect Effects

Simplified Delay Times Calculations

Average capacitance current during

charging and discharging:
Digital IC Design

Switching Characteristics and Interconnect Effects

Simplified Delay Times Calculations

Average capacitance current during

charging and discharging:
Digital IC Design

Switching Characteristics and Interconnect Effects

Simplified Delay Times Calculations

Average capacitance current during

charging and discharging:
Digital IC Design

Switching Characteristics and Interconnect Effects

Simplified Delay Times Calculations

Average capacitance current during

charging and discharging:
Digital IC Design

Switching Characteristics and Interconnect Effects

Simplified Delay Times Calculations

Average capacitance current during

charging and discharging:
Digital IC Design

Switching Characteristics and Interconnect Effects

Simplified Delay Times Calculations

Average capacitance current during

charging and discharging:
Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations

Current during discharging: nMOS is in saturation and pMOS is cut-off

Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations

Current during discharging: nMOS is in saturation and pMOS is cut-off

When the nMOS is saturation:

Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations

Current during discharging: nMOS is in saturation and pMOS is cut-off

When the nMOS is saturation:

Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations

Current during discharging: nMOS is in saturation and pMOS is cut-off

When the nMOS is saturation:

Since, iD,n is independent of Vout in saturation.

Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations
Current during discharging: nMOS is in saturation and pMOS is cut-off

Delay when nMOS is in saturation

Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations

Current during discharging: nMOS is in linear and pMOS is cut-off

Similarly, when the nMOS is in linear:

Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations
Current during discharging: nMOS is in linear and pMOS is cut-off
Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations

Finally the delay time during high to low transition is the addition of these two:
Digital IC Design

Switching Characteristics and Interconnect Effects

Detailed Delay Times Calculations

For CMOS inverters, VOH = VDD and VOL = 0

Similarly, the charge-up event of Cload i.e. Vin switches from VOH to VOL

Thus, the sufficient conditions for balanced delays .ie., for

Digital IC Design

Switching Characteristics and Interconnect Effects

Delay Constraints

The load cap. consists of intrinsic and extrinsic components. If Cload

mainly consists of extrinsic components i.e. independent of transistor
dimensions, then the transconductance kn can be used in the following
equation to design the inverter with a specific delay:

Note that, the transistor sizes thus found from the delay requirements must also meet the other design criteria such as noise
margin, logic inversion threshold, power dissipation and Si area.
Digital IC Design

Switching Characteristics and Interconnect Effects

An example: Ring Oscillator

Note odd numbers

of gates
Digital IC Design

Switching Characteristics and Interconnect Effects

An example: Ring Oscillator

Note odd numbers of gates

The oscillation period T can be given as

For any arbitrary odd number (n) of inverters

The avg. propagation delay of a typical inverter

with minimum capacitive load can be obtained by
cascading the odd n identical inverters

Typically, n is made much

larger than 3 or 5.

For higher accuracy & stability of oscillation frequency, an off-chip crystal oscillator is usually preferred.
Digital IC Design

Interconnect Effects: Estimation of Interconnect Parasitics

Inverters connected to interconnects
Digital IC Design

Interconnect Effects

Gate and interconnect delay

Digital IC Design

Interconnect Effects: Estimation of Interconnect Parasitics

Statistical distribution of interconnection length on a typical chip

An example of six interconnect lines running on three different levels.

Digital IC Design

Interconnect Effects: Estimation of Interconnect Capacitance

Interconnect segment running parallel to surface: Electrostatic problem

Digital IC Design

Interconnect Effects: Estimation of Interconnect Capacitance

Interconnect segment running parallel to surface: Electrostatic problem

Digital IC Design

Interconnect Effects: Estimation of Interconnect Capacitance

Fringing field and parasitic capacitances can be calculated by the following formula as
suggested by Yuan and Trick
Digital IC Design

Interconnect Effects
Interconnect signal cross talk

(a)

Capacitive coupling components,

(a) between two parallel lines running on the same level,
(b) between three parallel lines running on two
different levels.

(b)

This coupling between the interconnect lines is mainly responsible for signal crosstalk.
Digital IC Design

Interconnect Effects: Estimation of Interconnect Capacitance

Capacitance design rule for interconnects

Ctotal = total cap of the line, Cground and Cx are the caps to the ground and the interline respectively.
Design rules: Minimum distance between the lines
Digital IC Design

Interconnect Effects: Estimation of Interconnect Capacitance

Capacitance design rule for interconnects

Cross-sectional view of a double-metal CMOS structure, showing capacitances between various layers.
Digital IC Design

Interconnect Effects: Interconnect Resistance Estimation

The resistance of a line depends on the type of material used (e.g., polysilicon, aluminum, or gold), the
dimensions of the line and finally, the number and locations of the contacts on that line.
Digital IC Design

Interconnect Effects: Calculation of Interconnect Delay

The Elmore Delay model:
Digital IC Design

Interconnect Effects

Elmore Delay:
Digital IC Design

Interconnect Effects

Elmore Delay:
Digital IC Design

Interconnect Effects

Elmore Delay:
Digital IC Design

Interconnect Effects

Elmore Delay:
Digital IC Design

Interconnect Effects

Elmore Delay:
Digital IC Design

Power Dissipation
Digital IC Design

Power Dissipation
Digital IC Design

Power Dissipation
Digital IC Design

Power Dissipation
Digital IC Design

Power Dissipation

Faster performance draws more power from circuit

Digital IC Design

Power-Delay Product (PDP):

the average energy required for a gate to switch its output voltage from low to high and from
high to low. PDP is a fundamental parameter which is often used for measuring the quality and
the performance of a CMOS process and gate design.

Also defined as
Digital IC Design

Power Dissipation

Power-delay curve in CMOS