ISR

• An interrupt is an external or internal

event that interrupts the • CPUs have fixed number of interrupts
microcontroller to inform it that a • Every interrupt has to be associated
device needs its service. with a piece of code called “Interrupt
• Allow a system to respond Service Routine”, or ISR.
asynchronously to an event and • If interrupt-x is received by CPU, the ISR-
deal with the event while another x is executed
program is executing. • CPU architecture defines a specific “code
address” for each ISR, which is stored in the
• An interrupt driven system gives the “Interrupt vector Table (IVT)”
illusion of doing many things • ISRs are basically “subroutines”, but they
simultaneously. end with the RETI, instruction instead of
• CPU cannot execute more than one RET
instruction at a time. • When an interrupt occurs, the CPU fetches
• It can temporarily suspend its ISR code address from the IVT and
execution of one program, executes it.
execute another, then return to
the first program. INTERRUPTS EXECUTION
• Interrupts are like subroutines.
Except that one does not know 1. Interrupt happens..
when the interrupt code will be 2. CPU finishes the instruction it is
executed. currently executing and stores the PC
on the stack
Enable and Disable Interrupt 3. CPU saves the current status of all
interrupts internally
• Interrupts can be individually enabled 4. Fetches the ISR address for the
or disabled. This is done in the IE interrupt from IVT and jumps to that
(Interrupt Enable) register (A8H). address
• IE is bit addressable. 5. Executes the ISR until it reaches the
• All interrupts correspond to bits in registers. RETI instruction. (in assembly)
• Therefore, it is possible to cause an 6. Upon RETI, the CPU pops back the
interrupt by setting the appropriate old PC from the stack and continues
bit in the appropriate register. with whatever it was doing before
• The end result is exactly as if the the interrupt occurred.
hardware interrupt occurred.
•Pending Interrupt External Hardware Interrupts
If an interrupt occurs while it is • Regarding the IT0 and IT1 bits in the TCON
disabled, or while a higher priority register, the following two points must be
interrupt is active, it becomes emphasized
pending. • When the ISRs are finished (that is, upon
• As soon as the interrupt is execution of RETI), these bits (TCON.1 and
enabled, it will cause a call. TCON.3) are cleared, indicating that the
• It is also possible to cancel it by interrupt is finished and the 8051 is ready to
software by clearing the respond to another interrupt on that pin
appropriate bit in the register • During the time that the interrupt service
routine is being executed, the INTn pin is
Timer Interrupt ignored, no matter how many times it makes
• The timer flag (TF) is raised when the a high-to-low transition
timer rolls over • RETI clears the corresponding bit in TCON
• In polling TF, we have to wait until register (TCON.1 or TCON.3)
the TF is raised • There is no need for instruction CLR
• The problem with this method TCON.1 before RETI in the ISR associated
is that the microcontroller is with INT0
tied down while waiting for TF
to be raised, and can not do Serial Communication Interrupt
anything else • TI (transfer interrupt) is raised when
• Using interrupts solves this problem the last bit of the framed data, the stop
and, avoids tying down the controller bit, is transferred, indicating that the
• If the timer interrupt in the IE SBUF register is ready to transfer the
register is enabled, whenever the next byte
timer rolls over, TF is raised, and • RI (received interrupt) is raised when
the microcontroller is interrupted in the entire frame of data, including the
whatever it is doing, and jumps to stop bit, is received
the interrupt vector table to service • In other words, when the SBUF
the ISR register has a byte, RI is raised to
• In this way, the microcontroller can indicate that the received byte
do other until it is notified that the needs to be picked up before it is
timer has rolled over lost (overrun) by new incoming
serial data