Department of Electronics &

Communication Engineering

Analog and Digital System

Design Laboratory (BECL305)
 Program Outcomes (POs)
PO 1: Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO 2: Problem Analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
PO 3: Design/ Development of Solutions: Design solutions for complex engineering problems and
design systemcomponents or processes that meet the specified needs with appropriate consideration for
the public health and safety, and the cultural, societal, and environmental considerations.
PO 4: Conduct Investigations of Complex Problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.
PO 5: Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and modern
engineeringand IT tools including prediction and modeling to complex engineering activities with an
understanding of thelimitations.
PO 6: The Engineer and Society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineeringpractice.
PO 7: Environment and Sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
PO 8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of theengineering practice.
PO 9: Individual and Team Work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
PO 10: Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write effective
reports and design documentation, make effective presentations, and give and receive clear instructions.
PO 11: Project Management and Finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader
in a team, to manage projects and in multidisciplinary environments.
PO 12: Life-Long Learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Program Specific Outcomes (PSOs)
PSO 1: Graduates will have the ability to apply the technology in the areas of Analog and Digital Systems Design
adopting Internet of Things.
PSO 2: Design and implement embedded system which involves hardware software co-design for signal
processing and communication application.
Program Educational Objectives (PEOs)
PEO 1: To produce competent graduates with ability to analyze, design, develop, and implement Electronics and
Communication systems which are useful to the society.
PEO 2: To make the students capable of managing their profession based on existing as well as new emerging
technologies in the domain of Electronics and Communication Engineering.
PEO 3: To deliver the course curriculum such that students will be able to exhibit professionalism, ethical
attitude, communication skills, team work in their profession and to update themselves by engaging in life-long
learning.
PEO 4: To instill capacity in students to excel in professional career and/or higher education by acquiring
knowledge in the field of Electronics and Communication.
 Analog and Digital Systems Design Semester 3
Laboratory
Course Code BECL305 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2 SEE Marks 50
Credits 01 Exam Hours 100
Examination type (SEE) Practical
Course objectives:
This laboratory course enables students to
 Understand the electronic circuit schematic and its working
 Realize and test amplifier and oscillator circuits for the given specifications
 Realize the opamp circuits for the applications such as DAC, implement mathematical functions and precision rectifiers.
 Study the static characteristics of SCR and test the RC triggering circuit.
 Design and test the combinational and sequential logic circuits for their functionalities.
 Use the suitable ICs based on the specifications and functions.
Sl.NO Experiments (All the experiments has to be conducted using discrete
components)
1 Design and set up the BJT common emitter voltage amplifier with and without feedback and determine the gain-
bandwidth product, input and output impedances.
2
Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator

3
Design and set up the circuits using opamp: i) Adder, ii) Integrator, iii) Differentiator and iv) Comparator

4 Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) for a 4-bit binary input using toggle switches (ii) by
generating digital inputs using mod-16
5 Design and implement (a) Half Adder & Full Adder using basic gates and NAND gates, (b) Half subtractor&
Full subtractor using NAND gates, (c) 4-variable function using IC74151(8:1MUX).
6 Realize (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-3 code conversion and
vice versa
7 a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop b) Realize the
shift registers using IC7474/7495: (i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson
counter.
8 Realize a) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop b) Mod-N
Counter using IC7490 / 7476 c) Synchronous counter using IC74192
Demonstration Experiments ( For CIE )
9 Design and Test the second order Active Filters and plot the frequency response,
i) Low pass Filter
ii) High pass Filter

10 Design and test the following using 555 timer

i) MonostableMultivibraator
ii) AstableMultivibrator
11 Design and Test a Regulated Power supply

12 Design and test an audio amplifier by connecting a microphone input and observe the output using a loud
speaker.
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Design and analyze the BJT/FET amplifier and oscillator circuits.
2. Design and test Opamp circuits to realize the mathematical computations, DAC and precision rectifiers.
3. Design and test the combinational logic circuits for the given specifications.
4. Test the sequential logic circuits for the given functionality.
5. Demonstrate the basic circuit experiments using 555 timer.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The minimum
passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum passing mark is
35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the academic requirements
and earned the credits allotted to each subject/ course if the student secures a minimum of 40% (40 marks out of 100) in
the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation (CIE):

CIE marks for the practical course are 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment is to be evaluated for conduction with an observation sheet and record write-up. Rubrics for the
evaluation of the journal/write-up for hardware/software experiments are designed by the faculty who is handling
the laboratory session and are made known to students at the beginning of the practical session.
 Record should contain all the specified experiments in the syllabus and each experiment write-up will be evaluated
for 10 marks.
 Total marks scored by the students are scaled down to 30 marks (60% of maximum marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct a test of 100 marks after the completion of all the experiments listed in the syllabus.
 In a test, test write-up, conduction of experiment, acceptable result, and procedural knowledge will carry a
weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
 The marks scored shall be scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and marks of a test is the total CIE marks scored by
the student.

Semester End Evaluation (SEE):

 SEE marks for the practical course are 50 Marks.
 SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the Head of the Institute.
 The examination schedule and names of examiners are informed to the university before the conduction of the
examination. These practical examinations are to be conducted between the schedule mentioned in the academic
calendar of the University.
 All laboratory experiments are to be included for practical examination.
 (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be strictly
adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be decided jointly by
examiners.
 Students can pick one question (experiment) from the questions lot prepared by the examiners jointly.
 Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners.
General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result in -60%, Viva-
voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks and scored marks shall be scaled
 down to 50 marks (however, based on course type, rubrics shall be decided by the examiners)
Change of experiment is allowed only once and 15% of Marks allotted to the procedure part are to be made zero.
The minimum duration of SEE is 02 hours

Suggested Learning Resources:

1. David A Bell, “Fundamentals of Electronic Devices and Circuits Lab Manual”, 5th Edition, 2009, Oxford
University Press.
th
2. Albert Malvino, David J Bates, Electronic Principles, 7 Edition, McGraw Hill Education, 2017.
3. Fundamentals of Logic Design, Charles H Roth Jr., Larry L Kinney, Cengage Learning, 7th Edition.
Experiment -1 BJT Common Emitter amplifier using voltage divider biaswith
and without feedback.

Aim: To design and set up the common emitter amplifier using voltage divider bias with and without
feedback and determine the gain-bandwidth product from its frequency response.
Components Required:

# Apparatus and Components Range Quantity

1 Bread board - 1
2 Transistor BC-107 1
3 Resistors As per design -
4 CRO - 1
5 Function Generator - 1
6 DC Power supply - 1
7 Probes - 3
8 Connecting wires - -
9 Capacitors As per design -

Circuit Diagram:

Common Emitter amplifier without feedback

 Common Emitter amplifier with feedback

Theory:
CE amplifier is widely used in audio frequency applications in radio and television receivers.
For the proper functioning of an amplifier, the transistor must be biased in the active region where
the base current has a complete control over the collector current. Thus a small increase in the base
current results in a relatively large increase in the collector current.

In the circuits shown, an NPN transistor is connected as a CE amplifier in which the voltage
divider bias is employed. The name voltage divider comes from the voltage divider network formed
by the resistors R1 and R2.

The voltage divider bias provides good stabilization so that the operating point can be made
independent of the variations in hfe. This is achieved by properly selecting the resistor values R1 and
R2. The purpose of the bypass capacitor CE is to bypass signal current to the ground. The AC signal
(feedback voltage) developed across the emitter resistor RE is bypassed through the capacitor CE.
Thus the gain of the amplifier increases, since this bypassing reduces the negative feedback across
RE. This implies that when the bypass capacitor CE is connected, gain increases and bandwidth
decreases and when it is disconnected, gain falls and bandwidth increases.

The purpose of the coupling capacitors Cc1 and Cc2 is to couple the AC signal to the input and
output of the amplifier respectively. Meanwhile they block the DC signal and also determine the
lowest frequency which is to be amplified.
Procedure:

 Check all the components and equipment’s for their good working condition.
 Connections are made as shown in circuit diagram.
 Apply a 100mV peak-to-peak sinusoidal signal from the signal generator by
pressingthe 20 dB or 40 dB attenuation knob on signal generator.
 Keeping the input voltage constant at 100mV, vary the frequency of the input
signal and measure the output peak-to-peak voltage amplitude corresponding to
different frequencies and enter it in a tabular column.
 Calculate the gain in decibels. Plot the frequency response Vs gain in dB. From the graph
obtain gain, bandwidth, gain-bandwidth product.
Tabular Column:
Common Emitter amplifier without feedback
Select Vi = 100mV(p-p)

Frequency in Hz Vo(p-p) in V Av = Vo/Vi Gain in dB =20log10 Av

Common Emitter amplifier with feedback

Select Vi = 100mV(p-p)

Frequency in Hz Vo(p-p) in V Av = Vo/Vi Gain in dB =20log10 Av

 deal Graph:

To measure input and output impedances:

Input Impedance Zi:

Procedure:
 Connect the circuit as shown in figure.
 Set the DRB to minimum resistance (0Ω), I/P sine wave amplitude to 1V p-p, I/P sine
wave frequency to 10 KHz.
 Measure Vo (p-p). Let Vo=Va
 Increase DRB till Vo=Va/2.the corresponding DRB value gives Zi.

Output Impedance Zo:

Procedure:
 Connect the circuit as shown in figure. Set the DRB to its maximum resistance value, I/P sine
wave amplitude to 1V p-p, frequency to 10 KHz.
 Measure Vo p-p, let Vo = Vb
 Decrease DRB till Vo =Vb/2.
 The corresponding DRB value gives Zo.

Calculation:
Without feedback:
Lower Cut-off Frequency, fL =
Upper Cut-off Frequency, fU =
Gain = dB
Bandwidth = Hz
Gain-Bandwidth Product= .

With feedback:
Lower Cut-off Frequency, fL =
Upper Cut-off Frequency, fU =
Gain = dB
Bandwidth = Hz
Gain-Bandwidth Product= .

Result:

The BJT common emitter amplifier using voltage divider bias with and without feedback
was designed and determined the following parameters.
 Experiment No. 2: a) Colpitt’s Oscillator

Aim: To Design and setup Colpitts Oscillator using BJT and to determine the frequency of
Oscillation.

Components Required:

Sl. No Apparatus and Components Range Quantity

1 Transistor BF 194/195 1
2 Resistors As per design -
3 Capacitors As per design -
4 DCB - 2
5 DIB - 2
6 CRO probes and connecting wires - -

Theory:
An oscillator is an electronic circuit that produces a respective electronic signal,often a
sine wave or a square wave.
A Colpitts oscillator, invented by Edwin H. Colpitts is one of a number of designs for electronic
oscillator circuits using the combination of an inductance (L) with a capacitor (C)for frequency
determination, thus also called LC oscillator. One of the features of this typeof oscillator is its
simplicity (needs only a single inductor) and robustness. A Colpitts oscillator is the electrical dual of
Hartley oscillator.
In Colpitts oscillator, the feedback needed for oscillator is taken from a voltage divider made
by the two capacitors, where in the Hartley oscillator, the feedback is taken from a voltage divider
made by two inductors.
The basic CE amplifier provides 1800 phase shift and feedback network provides the
remaining 1800 phase shift so that the overall phase shift is 3600 to satisfy the Barkhausen criteria.
The Barkhausen criteria states that- “In a positive feedback amplifier, to obtain sustained oscillation,
the overall loop gain must be unity and the overall phase shift must be 00 or 3600”.
When the power supply is switched ON, due to random motion of electrons inpassive
components like resistor, capacitor, a noise voltage of different frequencies will be developed at the
collector terminal of transistor, out of these the designed frequency signal is fed back to the amplifier
by the feedback network and the process repeats to givesuitable oscillation at output terminal.
Circuit diagram:

Colpitt Oscillator

Design:
Design of the amplifier circuit is Colpitts oscillator.

Selection of transistor: Select the high frequency transistor BF 194/195.

Details:
Type: NPN silicon
Application: AM or FM, Radio, TV
Nominal ratings: VCE=5 to 10V, IC=1mA
Typical hfe= 36 or 125

Physical appearance:

DC biasing conditions:
Let VCC = 12V, IC= 1mA

Then, VRC = 40% of VCC = 0.4 x 12= 4.8 V

VCE = 50% of VCC = 0.5 x 12 = 6V

VRE = 10% of VCC = 0.1 x 12 = 1.2V
Expected output waveform:
Result:

Frequency of Designed value Observed value

oscillation
100 KHz
 Experiment No. 2: b) Crystal Oscillator.

Aim: To design and setup the crystal oscillator and to determine the frequency ofoscillation.

Components Required:

# Apparatus and Components Range Quantity

1 Transistor BF 194/195 1
2 Resistors As per design -
3 Capacitors As per design -
4 DCB - 1
5 DIB - 2
6 CRO probes and connecting wires - -
Theory:
An oscillator is an electronic circuit that produces a respective electronic signal, often a sine
wave or a square wave. A crystal oscillator is an electronic circuit that uses the mechanical resonance
of a vibrating crystal of piezoelectric material to create an electrical signal with a very precise
frequency. This frequency is commonly used to keep track of time (as in quartz wristwatches), to
provide a stable clock signal for digital integrated circuits, and to stabilize frequencies for radio
transmitters and receivers. The most common type of piezoelectric resonator used is the quartz
crystal, so oscillator circuits designed around them were called “Crystal oscillator”.

Circuit diagram:
Design:
Design of the amplifier circuit is Colpitts oscillator.

Selection of transistor: Select the high frequency transistor BF 194/195.

Details:
Type: NPN silicon
Application: AM or FM, Radio, TV
Nominal ratings: VCE=5 to 10V, IC=1mA
Typical hfe= 36 or 125

Physical appearance:

DC biasing conditions:
Let VCC = 20V, IC= 1mA

Then, VRC = 40% of VCC = 0.4 x 20= 8V

VCE = 50% of VCC = 0.5 x 20 = 10V

VRE = 10% of VCC = 0.1 x 20 = 2V

Expected output waveforms

Result:
Theoretical frequency fo= Hz

Practical frequency fo= Hz

 Experiment No. 3: Adder, Integrator and Differentiator using Op-Amp.
Aim: To design a two input adder, integrator and a differentiator using Op-Amp.

Components required:

SL No. Apparatus Quantity

1 Op-Amp (µA 741) 1
2 Resistors As per design
3 Capacitors As per design
4 CRO and signal generator 1
5 Multimeter 1

Theory:
An operational amplifier along with amplification it can also performmathematical
operations like addition, subtraction, differentiation and integration.
i) Adder circuit using 741 op-amp:
An adder is an electronic circuit that produces an output, which is equal to the sum of the
applied inputs.
An op-amp based adder produces an output equal to the sum of the input voltages applied
at its inverting terminal. It is also called as a summing amplifier, since the output is an amplified
one. The non-inverting input terminal of the op-amp is connected to ground. That means zero volts
is applied at its non-inverting input terminal.
According to the virtual short concept, the voltage at the inverting input terminal of an op-amp is
same as that of the voltage at its non-inverting input terminal. So, the voltage at the inverting input
terminal of the op-amp will be zero volts. The expression for the output voltage is given as,

ii) Differentiator:
The differentiator circuit performs the mathematical operation of differentiation; that is, the
output waveform is the derivative of the input waveform. The differentiator may be constructed
from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1. The expression
for the output voltage is given as,

Here the negative sign indicates that the output voltage is 1800 out of phase with the input
signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-
amp to compensate for the input bias current. A workable differentiator can be designed by
implementing the following steps:
1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a
value of C1 < 1 μF, calculate the value of Rf.
2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1*C1 = Rf *Cf.

The differentiator is most commonly used in wave-shaping circuits to detect high frequency
components in an input signal and also as a rate–of–change detector in FM modulators.

iii) Integrator:
A circuit in which the output voltage waveform is the integral of the input voltage waveform
is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the
feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given as,

Here the negative sign indicates that the output voltage is 1800 out of phase with the input signal.
Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb. The
input signal will be integrated properly if the Time period T of the signal is larger than or equal to
Rf Cf. That is,

The integrator is most commonly used in analog computers and ADC and signal-wave
shaping circuits.

Circuit diagram:

i) Adder:

Two input summing circuit/ adder:

Three input summing Circuit:

Design for two input summing circuit:

For a two input summing circuit output voltage is calculated using

Thus the designed summing circuit givens inverted, direct sum of two applied inputs.

Procedure:

 Rig up the circuit as shown in the circuit diagram.

 Apply input voltages v1 and V2 using DC power supplies.
 Observe the inverted sum at pin no. 6 of op-amp.
 This circuit can be extended to add three inputs by connecting an
additionalresistor at its inverting input terminal.
 Compare the output with the theoretical value.
 Tabular column:

V1(volts) V2(Volts) V0(Theoretical) V0(Practical)

ii) Differentiator circuit using 741 op-amp:

Note: A workable differentiator can be designed by implementing the following steps: 1.Select fa equal
to the highest frequency of the input signal to be differentiated. Then, assuming a value of C1< 1 µF,
calculate the value of Rf. 2. Choose fb = 20 fa and calculatethe values of R1 and Cf so that R1C1 = Rf
Cf. Assume Rcomp = Rf.

Design:

To design a differentiator circuit to differentiate an input signal that varies in frequency

from 10 Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied tothe differentiator,
Given fa = 1 KHz We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1)
Let us assume C1 = 0.1 µF ; then Rf = _Since fb = 20 fa , fb = 20 KHz
We know that the gain limiting frequency fb = 1 / (2π R1 C1) Hence R1 =

Also since R1C1 = Rf Cf ; Cf =

Given Vp = 1 V and f = 1000 Hz, the input voltage is Vi = Vp sin ωt We know ω = 2πf
Hence Vo = - Rf C1 ( dVi /dt ) = - 0.94 cos ωt
Procedure:
 Connections are given as per the circuit diagram.
 + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
 By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the OpAmp.
 The output voltage is obtained in the CRO and the input and output
voltagewaveforms are plotted in a graph sheet.
Observation:

Output Waveform

iii) Integrator circuit using 741 op-amp:

Note: [To obtain the output of an Integrator circuit with component values R1Cf = 0.1ms , Rf = 10
R1 and Cf = 0.01 µF and also if 1 V peak square wave at 1000Hz is applied as input.]

Design:
We know the frequency at which
thegain is 0 dB, fb = 1 / (2π R1
Cf) Therefore fb =
Since fb = 10 fa , and also the gain limiting frequency fa = 1 / (2π Rf Cf) We get , R1 =
and hence Rf =

Procedure:
 Connections are given as per the circuit diagram.
 + Vcc and -Vcc supply is given to the power supply terminal of the Op-Amp IC.
 By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
 The output voltage is obtained in the CRO and the input and output.
 voltagewaveforms are plotted.

Output Waveform:
iv) Comparator Circuit using IC 741

Waveform:

Result:
An adder, Integrator, Comparator differentiator circuits are designed and observed
output waveforms on CRO
 Experiment No. 4: R – 2R Digital to Analog Converter Using Op – Amp.
Aim: To design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binaryinput
from toggle switches and (ii) by generating digital inputs using mod-16 counter using IC7493

Components required:

SL No. Apparatus Quantity

1 Op-Amp (µA 741) 1
2 Resistors 1KΩ, 2.2 KΩ
3 IC trainer kit 1
4 CRO 1
5 Multimeter 1

Theory:
Data in binary digital form can be converted to corresponding analog form by using a R- 2R ladder
(binary weighted resistor) network and a summing amplifier. R-2R weighted resistor ladder network
uses only 2 set of resistors- R and 2R. Vref is nothing but the input binary value reference voltage,
that is for binary 1, Vref=5V and for binary 0, Vref=0V. This type of DAC utilizes Thevenin’s theorem
in arriving at the desired output voltages.
For 0001 only D0=Vref, all other inputs are at 0V and can be treated as ground. So finally
Vref/16 volt is appearing as the input to op amp. This value gets multiplied by the gain of op amp
circuit – (Rf/Ri). If we proceed in this manner (Thevenin equivalent reduction), we will get

In this circuit the 7493 IC simply provides digital inputs to DAC. It is a counter IC which counts from
0 to 15 and not an integral part of the DAC circuit.

Design:

Circuit diagram:

i) 4 bit R – 2R Op-Amp Digital to Analog Converter using 4 bit binary input from toggle switches:
Tabular Column:
ii) 4 bit R – 2R Op-Amp Digital to Analog Converter using 16 mod counter IC:

Waveform:
Procedure:
 Make connections as shown in the circuit diagram
 Vary the digital input from 0000 to 1111and note down the output of the op-amp in each
case. Tabulate the readings in the tabular column.

Procedure:
 Make connections as shown in the circuit diagram
 Vary the digital input from 0000 to 1111 and note down the output of the op- amp in each
case. Tabulate the readings in the tabular column.
 To Measure full scale output voltage.
 Full scale output voltage is obtained by setting all the binary inputs to logic high.

Result:
A 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input from toggle
switches and (ii) by generating digital inputs using mod-16 counter has been designed and output
obtained is verified with the theoretical value.
 Experiment No. 5:
a) Design & Implement of Half Adder & Full Adder Using Basic Gates &
NAND Gate
Aim: Realization of Full adder using (i) Basic logic gates and (ii) NAND gates.
Apparatus Required: IC 7404, IC 7432, IC 7408, IC 7400, etc.
Theory:
Half Adder: A half adder is a combinational circuit which has two inputs for the two bits to be added
and two outputs one for the sum ‘ S’ and other for the carry ‘ C’ into the higher adder position.
Full Adder: A full adder is a combinational circuit that forms the arithmetic sum of inputs; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from
OR Gate.

Procedure: -
 Verify the gates.
 Make the connections as per the circuit diagram.
 Switch on VCC and apply various combinations of input according to the truth table.
 Note down the output readings for half/full adder sum/Carry bit for different
combinations of inputs

Half Adder using Basic Gate & NAND gates

Truth Table:

Input Output

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
K-Map for SUM & CARRY

SUM = A’B + AB’

 CARRY = AB

Full Adder using Basic Gate & NAND gates

Truth Table:
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC
b) Design & Implement of Half Subtractor & Full Subtractor Using NAND Gate

Aim: To realize Half Subtractor & Full Subtractor adder using NAND Gate.

Apparatus Required
IC 7400, etc.

Procedure: -
 Verify the gates.
 Make the connections as per the circuit diagram.
 Switch on VCC and apply various combinations of input according to the truth table.
 Note down the output readings for half/full Subtractor Difference/Barrow bit for
different combinations of inputs.

Half subtractor

Full Subtractor
 Half Subtractor
Full Subtractor
A B D B D(V) B(V)
A B Cn-1 D B D(v) B(v)
0 0 0 0
0 0 0 0 0
0 1 1 1
0 0 1 1 1
1 0 1 0
0 1 0 1 1
1 1 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

c) Realization of 4 variable Logic expression using 8:1multiplexer

Logic symbol and function table of 8:1 Mux

Use hardware reduction method and implement the given Boolean expression with the help of neat
logic diagram. (N-circle Method)

Truth Table: Y = F(A, B, C, D) = Ʃm (0, 1, 2, 7, 8, 9, 14, 15)

AB C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 10 1 1 1
D=0 1 1 0 0 1 0 0 1
D=1 1 0 0 1 1 0 0 1
Y 1 D 0 D 1 0 0 1
8:1 mux Data D0=1 D1= D D2=0 D3=D D4=1 D5=0 D6=0 D7=1
I/P
Result:
Thus the Logic circuits of Half Adder & Full Adder and Half subtractor & Full subtractor using
(i) basic gates (ii) NAND gates were constructed and verified with the truth table also Realization 4-
variable function using 8:1 mux (IC 74151) is Verified.
 Experiment No. 6:
Realize i) Binary to Gray Code Conversion & Vice Versa (IC74139)
ii) BCD to Excess-3 Code Conversion and Vice verse

Aim: To realize binary to gray and gray to binary code converters.

Components Required:
1. IC 74139, 7486,
2. Trainer kit,
3. patch cords.

Theory:

Gray code – also known as Cyclic Code, Reflected Binary Code (RBC), Reflected Binary(RB) or
Grey code – is defined as an ordering of the binary number system such that each incremental value
can only differ by one bit. In gray code, while traversing from one step to another step only one bit in
the code group changes. That is to say that two adjacent code numbers differ from each other by only
one bit.
Gray code is the most popular of the unit distance codes, but it is not suitable for arithmetic
operations. Gray code has some applications in analog to digital converters, as well as being used for
error correction in digital communication. Gray code can be difficult to understand initially, but
becomes much easier to understand when looking at the gray code.

Binary to Gray Code Converter

The logical circuit which converts the binary code to equivalent gray code is known as binary
to gray code converter. An n-bit gray code can be obtained by reflecting an n-1 bit code about an
axis after 2n-1 rows and putting the MSB (Most Significant Bit) of 0 above the axis and the MSB of 1
below the axis. Reflection of Gray codes is shown below.

How to Convert Binary to Gray Code

The MSB (Most Significant Bit) of the gray code will be exactly equal to the first bit of the
given binary number. The second bit of the code will be exclusive-or (XOR) of the first and second bit
of the given binary number, i.e if both the bits are same the result will be 0 and if they are different
the result will be 1. The third bit of gray code will be equal to the exclusive (XOR) of the second and
third bit of the given binary number. Thus the binary to gray code conversion goes on.

IC 74139 Pin Diagram

The 3 bit binary to gray code conversion table is given below:

Circuit Diagram:

Binary to Gray Code Conversion Circuit Diagram

Gray to Binary Code Converter
In a gray to binary code converter, the input is gray code and output is its equivalent binary code.

Gray Code to Binary Conversion

Gray code to binary conversion is again a very simple and easy process. Following steps can
make your idea clear on this type of conversions. The MSB of the binary number will be equal
to the MSB of the given gray code. Now if the second gray bit is 0, then the second binary bit
will be the same as the previous or the first bit. If the gray bit is 1 the second binary bit will
alter. If it was 1 it will be 0 and if it was 0 it will be 1.
This step is continued for all the bits to do Gray code to binary conversion

Let us consider a 3 bit gray to binary code converter.

Circuit Diagram:

Gray Code to Binary Conversion Circuit Diagram

IC 7420 Pin Diagram

Aim: Design and implement BCD to Excess-3 code conversion and vice-versa.

Theory:
Code converter is a combinational circuit that translates the input code word into a
new corresponding word. The excess-3 code digit is obtained by adding three to the
corresponding BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder
feed BCD-code to the 4-bit adder as the first operand and then feed constant 3 as the second
operand. The output is the corresponding excess-3 code. To make it work as a excess-3 to
BCD converter, we feed excess-3 code as the first operand and then feed 2's complement of
3 as the second operand. The output is the BCD code.

BCD to Excess 3 Code Conversion

BCD Code to Excess-3 Code conversion

Excess 3 to BCD Code Conversion

Result:
As per the logical functions of BCD to Excess 3 code and vice versa logic diagrams are
designed and verified.
 Experiment:7
a) Realize the following i) Flip-Flops using NAND Gates.
ii)Master-Slave JK, iii) D & T Flip-Flop.

Aim: Realize Master-Slave JK, D and T flip flops using NAND Gates.

Components required:
1. Trainer Kit
2. 7400 IC, 7410 IC
3. Patch cards

(i) Master-Slave JK flip flops using NAND Gates.

ii) Master-Slave D flip flops using NAND Gates.

iii) Master-Slave T flip flops using NAND Gates.

Procedure:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Apply the clock pulse, inputs and verify the output with the corresponding truth
table.

Result:
Realized Master-Slave JK, D and T flip flops using NAND Gates and Verified the output.
 b) Realize the following shift registers using IC 7474/7495
(i) SISO (ii) SIPO (iii)) PISO (iv) PIPO (v) Ring (vi) Johnson counter

Aim: To realize the following shift registers using IC7495 (i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v)
RING (vi) JOHNSON COUNTER

Components required:
1. Trainer Kit
2. 7495 IC, 7404 IC
3. Patch cards

Theory:
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are
a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of
the next flip-flop. All the flip-flops are driven by a common clock, and all are set or reset
simultaneously. The serial in/serial out shift register accepts data serially – that is, one bit at a time
on a single line. It produces the stored information on its output also in serial form. The serial
in/parallel out shift register accepts data serially – that is, one bit at a time on a single line. It produces
the stored information on its output in parallel form. The parallel in/serial out shift register accepts
data in parallel. It produces the stored information on its output also in serial form. The parallel
in/parallel out shift register accepts data in parallel. It produces the stored information on its output
in parallel form.
Procedure
(i) Serial In Parallel Out
 Connections are made as per circuit diagram.
 Apply the data at serial i/p
 Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
 Apply the next data at serial i/p.
 Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new
data applied will appear at QA.
 Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register.

(ii) Serial In Serial Out

 Connections are made as per circuit diagram.
 Load the shift register with 4 bits of data one by one serially.
 At the end of 4th clock pulse the first data ‘d0’ appears at QD.
 Apply another clock pulse; the second data ‘d1’ appears at QD.
 Apply another clock pulse; the third data appears at QD.
 Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD. Thus the data
applied serially at the input comes out serially at QD

(iii) Parallel In Parallel Out

 Connections are made as per circuit diagram.
 Apply the 4 bit data at A, B, C and D.
 Apply one clock pulse at Clock 2 (Note: Mode control M=1).
 The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

(iv) Parallel In Serial Out

 Connections are made as per circuit diagram.
 Apply the desired 4 bit data at A, B, C and D.
 Keeping the mode control M=1 apply one clock pulse. The data applied at A, B, C and D will
appear at QA, QB, QC and QD respectively.
 Now mode control M=0. Apply clock pulses one by one and observe the data coming out
serially at QD.

LEFT SHIFT
 Connections are made as per circuit diagram.
 Apply the first data at D and apply one clock pulse. This data appears at QD.
 Now the second data is made available at D and one clock pulse applied.
 The data appears at QD to QC and the new data appears at QD.
 Step 3 is repeated until all the 4 bits are entered one by one.
 At the end 4th clock pulse the 4 bits are available at QA, QB, QC and QD.
JOHNSON COUNTER

Procedure-
 Connections are made as per the circuit diagram.
 Apply the data 1000 at A, B, C and D respectively.
 Keeping the mode M = 1, apply one clock pulse.
  Now the mode M is made 0 and clock pulses are applied one by one and the truth table
is verified.
 Above procedure is repeated for Johnson counter also.

Result:
The different operations such as SISO, SIPO, PISO, PIPO, Ring Counter and Johnson
counter operations were studied using 7495 and their corresponding truth tables were
verified.
 Experiment No. 8
a) Design Mod N Synchronous UP/DOWN Counter using 7476 JK Flip-flop
b) Mod-N Counter using IC7490/7476
c) Synchronous Counter using IC 74192

Aim: To Design Mod – N Synchronous UP Counter & DOWN Counter using 7476 JK Flip-flop

Components required:
 Trainer Kit
 IC 7490, 7410, 7400, 7408, 7476, 7432, 74192
 Patch cards

Theory: A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable
of progressing in increasing order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of the counter is controlled
by up/down signal. When this signal is high counter goes through up sequence and when up/down
signal is low counter follows reverse sequence.

Design Steps:
 Write the truth-table or state diagram.
 From truth-table/state-diagram, derive the state transition table.
 Decide the no. and type of flip-flops to be used.
 Using the corresponding excitation tables, derive the input and output equations and
simplify using K-maps.
 Using the derived simplified input and output expressions with flipflops, draw the circuit
diagram.

Procedure:
 Connections are made as per circuit diagram.
 Clock pulses are applied simultaneously at the clock I/Ps of all 7476 ICs used in the circuit
and the O/P is observed at the outputs of ICs 7476.
 Truth table is verified.
Pin Diagram
Realization of Mod – N synchronous Up and down counter using 7476

Realize a MOD-N Asynchronous counter using IC 7490

Pin Details of IC7490

Mod- 10 Counter

TruthTable

Clk QD QC QB QA
down
0 X X X X
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 0 0 0 0
Procedure:

 Circuit connections are made as shown in the figure.

 14th pin is connected to clock input and outputs are taken fromQ0, Q1, Q2 and Q3.
 As the clock pulses are applied, the output counts from 0000(0) to 1001(9) and then resets
back to 0000(0) and counts again till 1001(9).
MOD-8 COUNTER

Truth Table

Clk QD QC QB QA
down
0 X X X X
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1

Procedure:
 Circuit connections are made as shown in the figure.
 14th pin is connected to clock input and outputs are taken fromQ0, Q1, Q2 and Q3.
 As the clock pulses are applied, the output counts from 0000(0) to 0111(7) and then resets
back to 0000(0) and counts again till 0111(7).

Realize a MOD-N Synchronous Counter using IC 74192

Pin Details of IC-74192
MOD-6 COUNTER:

Truth Table:
Clk QD QC QB QA
down
0 X X X X
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 0 0 0
Procedure:

 Circuit connections are made as shown in the figure.

 14th pin is connected to clock input and outputs are taken fromQ0, Q1, Q2 and Q3.
 As the clock pulses are applied, the output counts from 0000(0) to 0101(5) and then resets
back to 0000(0) and counts again till 0101(5).

Result: As per the logical functions mod N counter are designed and verified
 EXPERIMENT 9

DESIGN ACTIVE SECOND ORDER BUTTERWORTH LOW PASS AND HIGH PASS
FILTERS

a) ACTIVE LOW PASS FILTER

AIM: To Design a second order Butterworth active low pass filter for a given cut-
offfrequency
COMPONENTS: IC‟s-LM741
Resistors-15k, 27k,
1.5k(2), 10kΩ.Capacitors-
0.1µF
EQUIPMENTS: Bread board
DC Power supply 0-30V, +/- 12V
Function generator, Cathode Ray Oscilloscope (CRO).

THEORY: A filter is frequency selective circuit that passes a specified band of

frequencies and blocks signals of frequencies outside this band. Filters may be
classified as follows. Analog & Digital, Passive & Active, Audio frequency & Radio
frequency filters. Depending on the elements used in construction, filters may be
classified as passive and active.
Elements used in passive filters are: Resistors, Capacitors and Inductors, and in active
filters Op-amps or Transistors are used along with resistors and capacitors. There are many
advantages of using active filters:

a) Since opamp is used in the construction of active filter, there is

flexibility in gainand frequency adjustment.
b) Since opamp input impedances is infinite, no loading problem on
filtercharacteristics.
c) This is applicable over a wide range of frequency.
d) Active filters are more economical than passive filters because of
cheaper opampsand absence of inductors.

Applications: Radio, Television, Telephone, Radar, Space satellites and biomedical equipments.The Most commonly
used filters are
 1) Low pass filters,
2) High pass filters,
3) Band pass filters, and
4) All pass filters.

CIRCUIT DIAGRAM:

Fig1: Circuit of second order active low pass filter

DESIGN:
Let Vcc = 12V;
Let the cut-off freq, fC =1KHz;
Voltage gain, Av = 1.586;
Av=1+ (Rf /R1) Let
Rf =15KΩ,
1.586=1+ (15k/R1)
Therefore R1=27KΩ

Assume R=R2=R3
Also Assume C = C1 = C2 = 0.1µF
Therefore, fC =1/2RC
Let fc=1 KHz
fc = 1/2πR(0.1µF)
R = 1.5kΩ
Therefore, R = R2 = R3 =1.5K.
PROCEDURE:
 1. Test the components and rig up the circuit as shown in the fig1.
2. Keeping the input voltage 1V (p-p) constant, vary the frequency of the signal from 100
Hz upto 5 kHz.
3. Record the output voltage for each of these frequencies.
4. Tabulate the output voltage and calculate the gain in dB.
5.Plot the graph of gain in dB v/s frequency as shown in fig2 on a semi-log sheet
anddetermine the cut-off frequency.
6. Compare the theoretical and practical values of the cut-off frequency.

TABULAR COLUMN:
Vin =1V (p-p)
Gain in db=20log (V0/Vin)
Roll of factor=(x-y)/ (20log(fc/f1))

Frequency in Hz Vo in volts Gain = Vo/Vin Gain(db) =

20log(Vo/Vin)
dB

EXPECTED GRAPH:

Fig2: Ideal graph of second order active low pass filter

RESULT:

Cut-off frequency (theoretical) = 1 KHz

Cut-off frequency (practical) = KHz
Roll-off factor (theoretical) = -40dB/ Decade
Roll-off factor (practical) = dB

b) ACTIVE HIGH PASS FILTER

AIM: To Design a second order Butterworth active high pass filter for a given cut-off
frequency
COMPONENTS: IC‟s-LM741
Resistors-15k, 27k, 1.5k
Capacitors-0.1μF
EQUIPMENTS: Bread board
Power supply DC 0-30V, +/- 12V
Function generator, Cathode Ray Oscilloscope(CRO).

CIRCUIT DIAGRAM:

Fig3:circuit of second order active high pass filter

PROCEDURE:

1. Test the components and rig up the circuit as shown in the fig3.
2. Keeping the input voltage 1V(p-p) constant, vary the frequency of the input signal
 from 100Hz up to 100 kHz.
3. Record the output voltage for each of these frequencies.
4. Tabulate the output voltage and calculate the gain in dB.
5. Plot the graph of gain in dB v/s frequency as shown in fig4 on a semi-log sheet
anddetermine the cut-off frequency.
6. Compare the theoretical and practical values of the cut-off frequency.

DESIGN:
Let Vcc = 12V;
The cut-off frequency, fC =1 KHz;
Voltage gain, Av = 1.586;
Av=1+(Rf\R1)
Let Rf =15KΩ,
Therefore R1=27KΩ
The Cut-off frequency
Assume R=R2=R3
Also Assume C = C1 = C2 = 0.1µF
Therefore, fC =1/2RC
fc = 1/2πR(0.1µf)
1 KHz = 1/2πR (0.1µF)
We get, R = 1.5KΩ Therefore,
R = R2 = R3 =1.5K




TABULAR COLUMN:
Vin =1V (p-p)
Gain in db=20log (V0/Vin)
Roll of factor=(x-y)/ (20log (fc/f1))
 Frequency in Hz Vo in volts Gain=Vo/Vin Gain(db) =
20log(Vo/Vin)
dB

EXPECTED GRAPH:

Fig4: second order active low pass filter

RESULT:

Cut-off frequency (theoretical) = 1 KHz

Cut-off frequency (practical) =
KHz Roll-
off factor (theoretical) =
dB Roll-off
factor (practical) = 40 dB/
Decade
 Experiment No.10: a) Astable Multivibrator using IC 555 Timer
Aim: To Design a Astable Multivibrator using IC – 555 timer to generate symmetricalsquare wave
of given frequency & find duty cycle.

Components Required: IC 555 Timer, resistors, power supply (0 - 30V), dual

power supply, Signal generator, CRO.

Pin Diagram of NE 555

Circuit Diagram:

Theory:

IC 555, as Astable multivibrator generates rectangular pluses and by suitably modifying

the circuit the square wave can be generated. The Multivibrator keeps on switching b/w 2 states
by itself and it does not need any external triggering. The circuit diagram is as shown in the
figure. If the time taken by capacitor is equal to the time for discharge then the TON= TOFF, it is
called symmetrical Astable Multivibrator and if TON not equal to TOFF i.e time taken for
charging is not equal to the time taken for discharging then its an unsymmetrical Astable
multivibrator.
Working:
Initially when the output is high capacitor C starts charging towards Vcc through RA
and RB. However as soon as the voltage across the capacitor equals 2/3Vcc, comparator1
triggers the flip-flop and the output switches to low state. Now capacitor C discharges through
RB and the transistor Q1. When voltage across C equals 1/3 Vcc, comparator 2’s output triggers
the flip-flop and the output goes high. Then the cycle repeats.The capacitor is periodically
charged and discharged between 2/3 Vcc and 1/3 Vcc respectively. The time during which the
capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output remains high and is
given by
tc = 0.693 *(RA +RB) *C
where RA and RB are in ohms and C is in Farads. Similarly the time during which the capacitor
discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by
td =0.693 * RB *C
Thus the total time period of the output waveform is
T = tc +td = 0.693 * (RA +2*RB) * C

Design:
Let f =1KHz,
DutyCycle75%
D = T1/(T1+T2) = T1/ T (Total Time Period)
T= 1/f =1msec
Where T = 0693 (Ra + 2Rb) C
Let C= 0.1
T1 = 0.75 T = T1 +T2T2 = T - T1
= 1msec – 0.75msec
=0.25msec.
From the equation for T2 we have
Rb = T2 / (0.693 x C) = 3.6 KΩ (3.3 KΩ)
=0.75msec/ (0.693 x 0.1 µF)

Ra + Rb = T1/(0.693 x C)
= 0.75msec/ (0.693 x 0.1 µF)
Ra + 3.6 KΩ =10.82 KΩ
Ra = 10.82 KΩ – 3.6 KΩ
Ra = 7.2 KΩ (6.8 KΩ)
Rb = 3.3KΩ

Procedure:
 Connection are made as shown with all designed values.
 Output waveform V0 and capacitive waveform Vc are noted.
 To get symmetrical square wave output.
Typical Graph:

Result:

Experiment No. 10: b) Monostable Multivibrator using IC 555 Timer

Aim : To Design a Monostable Multivibrator using IC – 555 timer for a given pulse width

Components Required: IC 555 Timer, resistors, power supply (0 - 30V), dual

power supply, Signal generator, CRO.

Circuit Diagram:
Design:
Given Tp = 1 m sec

Tp =1.1RaC
Assume C = 0.1Ra = Tp/1.1C Ra= 9.1 KΩ (10 KΩ)

Procedure:
 Circuit connections are made as shown.
 With Vi applied, V0 and VC waveform are noted.
 To find minimum amplitude for triggering the MMV, Vi amplitude is
reducedtill output vanishes.
 The condition of f(max) = 1/Tp is observed for triggering input.

Typical Graph:

Result:
 Experiment No.11 DESIGN AND TEST REGULATED POWER
SUPPLY

Aim: The purpose of the experiment is to design a +5 V DC regulated power supply delivering up to 1A of
current to the load.

COMPONENTS USED
30 MHz Dual Channel Cathode Ray Oscilloscope 3
MHz Function Generator
0-30 V dc dual regulated power supply4 ½
digit Digital Multimeter
230 V/ 9 V, 1A Step down transformer
1N4007 Diode
IC 7805
Resistor 100Ω, ¼W
Electrolytic Capacitor 1000µF/25V
Ceramic Capacitor 0.33 µF, 0.1 µF
Breadboard and Connecting wires BNC
Cables and Probes

THEORY
 Every electronic circuit is designed to operate off of supply voltage, which is usually constant.
 A regulated power supply provides this constant DC output voltage and continuously holds the
output voltage at the design value regardless of changes in load current or input voltage.
 The power supply contains a rectifier, filter, and regulator.
 The rectifier changes the AC input voltage to pulsating DC voltage.
 The filter section removes the ripple component and provides an unregulated DC voltage to the
regulator section.
 The regulator is designed to deliver a constant voltage to the load under varying circuit conditions.
 The two factors that can cause the voltage across the load to vary are fluctuations in input voltage
and changes in load current requirements.
 Load regulation is a measurement of power supply, showing its capacity to maintain a constant
voltage across the load with changes in load current.
 Line regulation is a measurement of power supply, showing its capacity to maintain a constant output
voltage with changes in input voltage.
 DESIGN
Design a 5 V DC regulated power supply to deliver up to 1A of current to the load with 5% ripple. The
input supply is 50Hz at 230 V AC.
Selection of Voltage regulator IC:
Fixed voltage linear IC regulators are available in a variation of voltages ranging from -24V to +24V. The
current handling capacity of these ICs ranges from 0.1A to 3A. Positive fixed voltage regulator ICs have the
part number as 78XX.
The design requires 5V fixed DC voltage, so 7805 regulator IC rated for 1A of output current is selected.
Selection of Bypass Capacitors:
The data sheet on the 7805 series of regulators states that for best stability, the input bypass capacitor
should be 0.33µF. The input bypass capacitor is needed even if the filter capacitor is used. The large
electrolytic capacitor will have high internal inductance and will not function as a high frequency bypass;
therefore, a small capacitor with good high frequency response is required.
The output bypass capacitor improves the transient response of the regulator and the data sheet recommends a
value of 0.1µF.
Dropout voltage
The dropout voltage for any regulator states the minimum allowable difference between output and input
voltages if the output is to be maintained at the correct level. For 7805, the dropout voltage at the input of the
regulator IC is Vo +2.5 V.
Vdropout = 5+2.5 = 7.5V
Selection of Filter Capacitor:
The filter section should have a voltage of at least 7.5V as input to regulator IC. That is

Vdc = 7.5 V

Figure 1: Output wave shape from a full-wave filtered rectifier

Ripple voltage = ΔV = Vr
Two figures of merit for power supplies are the ripple voltage, Vr, and the ripple factor, RF. RF
= Vr(rms) / Vdc
 Vdc = 2Vm/π = 0.636 Vm

Vr = IL x Toff/C can be solved for the value of C.

The ripple frequency of the full-wave ripple is 100 Hz. The off-time of the diodes for 100 Hz ripple is assumed
to be 85%. Toff = 8.5mS.
C = IL x Toff / Vr =

Selection of Diodes:
1N4007 diodes are used as it is capable of withstanding a higher reverse voltage, PIV of 1000V whereas
1N4001 has PIV of 50V.

Selection of Transformer:
Maximum unregulated voltage, Vunreg(max) = Vdropout + Vr =
Two diodes conduct in the full-wave bridge rectifier, therefore peak of the secondary voltage must be two
diode drops higher than the peak of the unregulated DC.
Vsec(peak) = Vunreg(max) + 1.4V =

Vsec(rms) = 0.707 x Vsec(peak) =

The power supply is designed to deliver 1A of load current, so the secondary winding of the transformer needs
to be rated for 1A.

CIRCUIT DIAGRAM

Figure 2
 PRACTICE PROCEDURE

1. Power Supply
1. Connect the circuit as shown in Figure 2.
2. Apply 230V AC from the mains supply.
3. Observe the following waveforms using oscilloscope
(i) Waveform at the secondary of the transformer
(ii) Waveform after rectification
(iii) Waveform after filter capacitor
(iv) Regulated DC output

Result:

Figure 3 observed waveforms

 Experiment No.11 Design and test an audio amplifier by connecting a microphone
input and observe the output using a loud speaker.
Aim: To design and test an audio amplifier by connecting a microphone input and observe the output using a
loud speaker.

Components

1. LM386
2. 10uF / 16V capacitor
3. 470uF / 16V
4. 0.047uF / 16V Polystar Flim Capacitor
5. 10R ¼ Watt
6. 12V Power Supply unit
7. 8 Ohms / .5 Watt Speaker
8. Capsule or Electret Microphone
9. .1uF capacitor
10. 10k 1/4th Watt Resistor
11. Bread Board
12. Hook up wires

Theory: You must have seen someone speaking on the MIC and the amplified voice coming from the speaker,
how this is possible? Is there any circuitry between MIC and speaker of we can directly connect Microphone
with speaker to get it working? In this circuit, we learn to build a simple Microphone to Speaker system, in
which input sound is given to the MIC and we hear the amplified version from the speaker.

What is a microphone?
The microphone is a transducer device which converts sound energy into electrical energy. Microphones are
often referred to a MIC. A microphone is used to capture some sort of sound and produce an electrical signal
according to it.

LM386 Audio Amplifier IC

Circuit Diagram
 Circuit diagram

Bread board connections

Procedure

1. Construct the circuit as in a breadboard.

2. Remove the R2 and use a potentiometer to adjust the gain of the microphone.
3. Connect a long wire across Speaker and keep it at larger distance from the microphone. The feedback will
be lower.
4. Use additional filters to get clean sound output.
5. Use proper low ripple power supply unit.

Result: Amplified audio at the (output)speaker is observed whenever some low sound is witnessed near
microphone.