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D D

Power-Up/Down Sequence
1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.

2. The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.
3. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
4. For power down, reversing the ramp-up sequence is recommended.

C C

PLT_RST#

VDDR3(3.3VGS) AND
PCH GATE
PLT_RST_VGA# PERSTB GPU
PCIE_VDDC(0.95V)
GPIO50 DGPU_HOLD_RST

VDDR1(1.5VGS) GPIO54 DGPU_PWR_EN

TACH0/GPIO17 DGPU_PWROK

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)
NOT DGPU_PWR_EN#

PERSTb
+3VS +3VS_VGA
REFCLK MOS 1
B B

Straps Reset +3VS +0.95VS_VGA +1.8VS +1.8VS_VGA

Regulator 2 MOS 5
Straps Valid
B+ +VGA_CORE +1.5VS +1.5VS_VGA
PWM 4 MOS 3
Global ASIC Reset

T4+16clock

CPU part

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/01/20 Deciphered Date 2015/01/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TOPAZ_NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B012P
Date: Tuesday, August 05, 2014 Sheet 41 of 55
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