Scribd
Upload
13 views

Expt 2_2024!25!2-Input NAND - NOR Gate (1).Docx

The document outlines an experiment for B.Tech students in VLSI Design, focusing on the preparation of CMOS layouts for two-input NAND and NOR gates using 0.12µm technology. It includes objectives such as simulating the gates with and without capacitive load and analyzing rise and fall times. Additionally, it provides requirements, observations, and questions related to the design and comparison of the two gates.

Uploaded by

jmandar1322
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
13 views

Expt 2_2024!25!2-Input NAND - NOR Gate (1).Docx

The document outlines an experiment for B.Tech students in VLSI Design, focusing on the preparation of CMOS layouts for two-input NAND and NOR gates using 0.12µm technology. It includes objectives such as simulating the gates with and without capacitive load and analyzing rise and fall times. Additionally, it provides requirements, observations, and questions related to the design and comparison of the two gates.

Uploaded by

jmandar1322
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

Pimpri Chinchwad Education Trust’s

Pimpri Chinchwad College of Engineering


Department of Electronics and Telecommunication Engineering

Experiment No: 2
Academic Year: 2024- 2025 Year: B.Tech (A, B, D) Semester: I
Course: VLSI Design Course Code: BET7425

TITLE: Prepare CMOS layout for NAND, and NOR gates in selected technology, draw the
layout of the same, simulate with and without capacitive load, and comment on rise and
fall times.

OBJECTIVES OF THE EXPT.:

1.​ To prepare the CMOS layout of two-input NAND and NOR gate in 0.12µm
technology, draw the layout, simulate with and without capacitive load, comment on
rise and fall times, and compare both gates.

CO and PO MAPPED: CO: 2 PO: 4, 5 PSO: 1, 2

REQUIREMENTS:
1.​ Microwind 3.9 backend tool for layout design

STUDY OF TWO-INPUT NAND & NOR GATE

NAND and NOR are universal gates; any gate can be designed using these gates, but the
NAND gate is faster than the nor gate and requires less area. Hence, NAND is preferred over
the NOR gate. If both inputs of the NAND gate are at ‘1’, then its output is ‘0’; otherwise,
output is ‘1’.In CMOS design, the NAND gate consists of two NMOS in series connected to
two PMOS in parallel. The schematic diagram of the CMOS NAND gate is shown below.
​
Logic symbol Truth-Table Circuit Layout

​
​
Pimpri Chinchwad Education Trust’s
Pimpri Chinchwad College of Engineering
Department of Electronics and Telecommunication Engineering

If both inputs of NOR gate is at ‘0’ then its output is ‘1’, otherwise the output is ‘0’. In
CMOS design, the NOR gate consists of two PMOS in series connected to two NMOS in
parallel. The schematic diagram of CMOS NOR gate is shown below.

Logic symbol Truth-Table Circuit Layout

Schematic and Stick Diagrams of NAND and NOR gate

●​ NAND GATE

Schematic Stick Diagram


Pimpri Chinchwad Education Trust’s
Pimpri Chinchwad College of Engineering
Department of Electronics and Telecommunication Engineering

●​ NOR GATE

Schematic Stick Diagram

OBSERVATIONS:

For NAND gate layout design

Rise Time:

Fall Time:

Power dissipation:

Commutation point:

Operating frequency:

For NOR gate layout design

Rise Time:

Fall Time:

Power dissipation:
Pimpri Chinchwad Education Trust’s
Pimpri Chinchwad College of Engineering
Department of Electronics and Telecommunication Engineering

Commutation point:

Operating frequency:

Comparison between NAND and NOR logic Gates

COMMENTS AND CONCLUSION:

___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________

QUESTIONS:
Pimpri Chinchwad Education Trust’s
Pimpri Chinchwad College of Engineering
Department of Electronics and Telecommunication Engineering

1.​ Design a 2-input NAND gate with a schematic and stick diagram using the
conventional method
2.​ Design a 2-input NOR gate with a schematic and stick diagram using the
conventional method

REFERENCES:

You might also like