Explore the full ebook collection and download it now at textbookfull.

com

Automatic Analog IC Sizing and Optimization

Constrained with PVT Corners and Layout Effects
1st Edition Nuno Lourenço

https://textbookfull.com/product/automatic-analog-ic-sizing-
and-optimization-constrained-with-pvt-corners-and-layout-
effects-1st-edition-nuno-lourenco/

OR CLICK HERE

DOWLOAD EBOOK

Browse and Get More Ebook Downloads Instantly at https://textbookfull.com

Click here to visit textbookfull.com and download textbook now
 Your digital treasures (PDF, ePub, MOBI) await
Download instantly and pick your perfect format...

Read anywhere, anytime, on any device!

Musical Sound Effects Analog and Digital Sound Processing

1st Edition Reveillac

https://textbookfull.com/product/musical-sound-effects-analog-and-
digital-sound-processing-1st-edition-reveillac/

textbookfull.com

Discrete Optimization in Architecture Architectural amp

Urban Layout 1st Edition Machi Zawidzki (Auth.)

https://textbookfull.com/product/discrete-optimization-in-
architecture-architectural-amp-urban-layout-1st-edition-machi-
zawidzki-auth/
textbookfull.com

Recent Advances in Control and Filtering of Dynamic

Systems with Constrained Signals Ju H. Park

https://textbookfull.com/product/recent-advances-in-control-and-
filtering-of-dynamic-systems-with-constrained-signals-ju-h-park/

textbookfull.com

Circuits and Electronics: Hands-on Learning with Analog

Discovery John Okyere Attia

https://textbookfull.com/product/circuits-and-electronics-hands-on-
learning-with-analog-discovery-john-okyere-attia/

textbookfull.com
Four Corners Level 1 Teacher s Edition with Complete
Assessment Program Jack C. Richards

https://textbookfull.com/product/four-corners-level-1-teacher-s-
edition-with-complete-assessment-program-jack-c-richards/

textbookfull.com

Grid Layout in CSS Interface Layout for the Web 1st

Edition Eric A. Meyer

https://textbookfull.com/product/grid-layout-in-css-interface-layout-
for-the-web-1st-edition-eric-a-meyer/

textbookfull.com

Jamming and rheology : constrained dynamics on microscopic

and macroscopic scales 1st Edition Liu

https://textbookfull.com/product/jamming-and-rheology-constrained-
dynamics-on-microscopic-and-macroscopic-scales-1st-edition-liu/

textbookfull.com

Sizing and selecting air pollution control systems First

Edition Cross

https://textbookfull.com/product/sizing-and-selecting-air-pollution-
control-systems-first-edition-cross/

textbookfull.com

Mechatronics and Automatic Control Systems Proceedings of

the 2013 International Conference on Mechatronics and
Automatic Control Systems ICMS2013 1st Edition Wego Wang
(Eds.)
https://textbookfull.com/product/mechatronics-and-automatic-control-
systems-proceedings-of-the-2013-international-conference-on-
mechatronics-and-automatic-control-systems-icms2013-1st-edition-wego-
wang-eds/
textbookfull.com
Nuno Lourenço
Ricardo Martins
Nuno Horta

Automatic Analog IC
Sizing and Optimization
Constrained with PVT
Corners and Layout
Effects
Automatic Analog IC Sizing and Optimization
Constrained with PVT Corners and Layout Effects
Nuno Lourenço Ricardo Martins
•

Nuno Horta

Automatic Analog IC Sizing

and Optimization
Constrained with PVT
Corners and Layout Effects

123
Nuno Lourenço Nuno Horta
Instituto de Telecomunicações, Instituto Instituto de Telecomunicações, Instituto
Superior Técnico Superior Técnico
Universidade de Lisboa Universidade de Lisboa
Lisbon Lisbon
Portugal Portugal

Ricardo Martins
Instituto de Telecomunicações, Instituto
Superior Técnico
Universidade de Lisboa
Lisbon
Portugal

ISBN 978-3-319-42036-3 ISBN 978-3-319-42037-0 (eBook)

DOI 10.1007/978-3-319-42037-0

Library of Congress Control Number: 2016945775

© Springer International Publishing Switzerland 2017

This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar
methodology now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publication does not imply, even in the absence of a specific statement, that such names are exempt from
the relevant protective laws and regulations and therefore free for general use.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
authors or the editors give a warranty, express or implied, with respect to the material contained herein or
for any errors or omissions that may have been made.

Printed on acid-free paper

This Springer imprint is published by Springer Nature

The registered company is Springer International Publishing AG Switzerland
To Alina and Íris
Nuno Lourenço

To my little girls, Nádia, Joana and Daniela

Ricardo Martins

To Carla, João and Tiago

Nuno Horta
Preface

Over the past few decades, very large scale integration technologies have been
widely improved, allowing the proliferation of consumer electronics and enabling
the steady growth of the integrated circuit (IC) market to an estimated value of over
$350 billion in 2016. The steady increase in performance of ICs in the recent past
has been mostly supported by an exponential growth in the density of transistors
while inversely reducing the transistors’ cost, as described by Moore’s law. Even
though it is still valid today, its end, as such an exponential law “can’t continue
forever” was already preconized by Moore itself, and is pushing for new techno-
logic advancements outside complementary metal-oxide-semiconductor (CMOS)
IC design. In the meanwhile, telecommunications, medical, and multimedia
applications extensively use of electronic devices where blocks of analog and
mixed-signal (AMS), digital processors and memory blocks are integrated together.
While AMS components in these system-on-a-chip (SoC) designs usually occupy
approximately 20 % of the die area, the design effort and respective design costs are
considerably higher in comparison to their digital counterpart. In this context, the
lack of mature automation tools for analog design has its share of blame in this SoC
design paradigm.
Generally the complexity in the design of analog circuits is not due to the
number of devices, but from their sensitivity to noise and the countless interactions
between them, e.g., parasitic disturbances, crosstalk, substrate noise, thermal noise,
etc. Plus, for smaller technology nodes with the increasing complexity of design
rules and physical effects, the impact of these interactions is even greater. Despite
the algorithms and techniques introduced in the last 25 years, analog IC design
automation tools still strive to keep up with the new challenges created by tech-
nological evolution. Therefore, designers’ exploration of the solution space keeps
on being mostly manual, and their knowledge and experience crucial in making
effective decisions at all stages of the analog design flow, creating additional risks
and elongating the time needed to complete the design. On the other hand, in the
digital IC design realm several mature electronic design automation (EDA) tools
and design methodologies are available, pushing the design productivity forward.

vii
viii Preface

Currently most of the low-level phases of the process are automated that help the
designers keeping up with the new capabilities offered by the technology and
making design reuse the commonplace. Since this difference in the level of
automation becomes critical when digital and analog circuits are integrated toge-
ther, the rising of efficient and state-of-the-art tools to boost analog designers’
productivity is an intensive research topic in both academia and industry.
The work presented in this book belongs to the scientific area of electronic
design automation and addresses automatic sizing of analog ICs. The developed
multi-objective design methodology for automatic analog IC sizing was imple-
mented in the tool AIDA-C. In AIDA-C, the usage of state-of-the-art multi-
objective multi-constraint optimization engines enables the exploration of circuit
design trade-offs. Process variation effects on circuit’s performance are accounted
with user-defined worst-case corners, and circuit’s performance evaluation is done
with industrial circuit simulators, e.g., Mentor Graphics’ ELDO®, Synopsys’
HSPICE®, or Cadence’s Spectre®, ensuring that the developed automatic circuit
sizing is compliant with the accuracy requirements of analog designers. In addition,
layout effects are included in the sizing-flow to decrease the number of independent
sizing and layout iterations required to obtain a post-layout correct design. To
further enhance AIDA-C, a model for first-order interactions between design
variables and circuit performance, the Gradient Model, derived using machine
learning techniques, is used to guide and accelerate the optimization process. The
proposed approach was validated with both classical and new analog circuit
structures for a several design processes, i.e., 130-nanometer, 180-nanometer, and
350-nanometer design kits, showing its validity and generality.
This work would not have been possible without the contribution, and the
support and valuable discussions on circuits, layout and optimization, of Ricardo
Póvoa, António Canelas, Frederico Rocha, and Ricardo Lourenço.
Finally, the authors would like to express their gratitude for the financial support
that made this work possible. The work developed in this book was supported in
part by the Fundação para a Ciência e a Tecnologia (Grant FCT-SFRH/BPD/
104648/2014, Grant FCT-SFRH/BD/86608/2012, Research project DISRUPTIVE
EXCL/EEI-ELC/0261/2012 and Research project UID/EEA/50008/2013) and by
the Instituto de Telecomunicações (Research project OPERA-PEst-OE/EEI/
LA0008/2013).
This book is organized in eight chapters.
Chapter 1 presents a brief introduction to analog IC design automation, with
special emphasis to automatic circuit sizing and optimization taking into account
layout effects and random variations. The motivation to address automatic analog
IC design is given, then, a well-accepted design flow for analog ICs that is the
starting point for the methodology proposed in this book is described.
Chapter 2 presents a study of the available tools for analog design automation,
overviewing state-of-the-art sizing optimization, robust design and layout-driven
approaches. Valuable information can be gathered from them, such as algorithms
and evaluation methods.
Preface ix

Chapter 3 introduces the developed automatic flow for analog IC design and
particularly the general description of the developed methodology providing more
detail about the inputs and interfaces of AIDA-C.
Chapter 4 describes the multi-objective optimization techniques used in
AIDA-C, addressing the non-dominated sorting genetic algorithm II (NSGA-II),
multi-objective simulated annealing (MOSA) and multi-objective particle swarm
optimization (MOPSO) algorithms. The enhancements made by using machine
leaning techniques, i.e., the Gradient model, are also explored.
Chapter 5 studies the results obtained with the proposed IC sizing approach with
different parameters for the optimization kernel, the impact of considering nominal
or worst-case conditions in the evaluation of the circuits, and also, the advantages of
enhancing the optimization kernels with the gradient model. Also, two amplifiers
and an oscillator are used to compare the performance of the three optimization
kernels (NSGA-II, MOSA MOPSO).
Chapter 6 presents two new methodologies to include layout effects in the sizing
optimization loop: the floorplan-aware approach, which is a method to include
layout’s geometric properties in the optimization with negligible impact in the
performance; and the layout-aware approach that accounts for the parasitic effects.
Chapter 7 presents the results obtained with the proposed analog layout-aware
sizing approach, by considering the circuit’s floorplan and layout induced para-
sitics. The efficiency of the methodology is proved in the successful design and area
improvement of four design cases: a single-stage folded cascode amplifier with bias,
a single-stage amplifier with gain enhancement using voltage combiners, a
two-stage Miller amplifier, and a two-stage folded cascode amplifier, for a
130-nanometer design process.
In Chap. 8, the closing remarks and future directions for the continuous
development of AIDA-C are outlined.

Lisbon, Portugal Nuno Lourenço

Ricardo Martins
Nuno Horta
Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Analog IC Design Automation . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Robustness in Analog IC Design. . . . . . . . . . . . . . . . . . . 3
1.1.2 Computer Assisted Analog IC Design . . . . . . . . . . . . . . . 5
1.2 Analog IC Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Automatic Analog Circuit-Level Sizing . . . . . . . . . . . . . . . . . . . 7
1.4 Contributions to the State-of-the-Art . . . . . . . . . . . . . . . . . . . . . 8
1.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Previous Works on Automatic Analog IC Sizing . . . . . . . . . . ..... 13
2.1 Analog IC Sizing Automation: An Historical Perspective . . ..... 13
2.2 Optimization-Based Circuit Sizing . . . . . . . . . . . . . . . . . . ..... 14
2.2.1 Optimization Techniques Applied to Analog Circuit
Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 Circuit’s Performance Evaluation . . . . . . . . . . . . . . . . . . 16
2.2.3 Commercial Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Robust Circuit Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 Worst-Case Optimization . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.2 Commercial Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 Layout-Aware Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Summary of the Automatic Circuit Sizing Approaches . . . . . . . . . 26
2.5.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3 AIDA-C Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1 AIDA Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 AIDA-C Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.1 Setup and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.2 Circuit Optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

xi
xii Contents

3.3 AIDA-C’s Analog IC Design Flow . . . . . . . . . . . . . . . . . . . . . . 43

3.3.1 Circuit Sizing Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.2 Layout-Aware Sizing Setup (Optional). . . . . . . . . . . . . . . 48
3.3.3 Graphical User Interface. . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.4 Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.5 Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4 Multi-objective Optimization Kernel . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1 Circuit Sizing as Multi-objective Optimization Problem . . . . . . . . 63
4.2 Optimization Kernel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.2.1 NSGA-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2.2 MOSA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2.3 MOPSO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2.4 Multi-kernel Algorithms. . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3 Enhancing the Optimization with Machine Learning . . . . . . . . . . 77
4.3.1 Sampling the Design Space Using DOE. . . . . . . . . . . . . . 77
4.3.2 Gradient Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5 AIDA-C Circuit Sizing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1 Evolutionary Parameters Impact . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1.1 Crossover and Mutation Rates . . . . . . . . . . . . . . . . . . . . 87
5.1.2 Population Size and Number of Generations . . . . . . . . . . . 91
5.2 Comparing the Evaluation Strategies . . . . . . . . . . . . . . . . . . . . . 94
5.2.1 Amplifier with Gain Enhancement Using VCs . . . . . . . . . 95
5.2.2 Fully Differential Telescopic Amplifier. . . . . . . . . . . . . . . 95
5.3 Gradient Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.1 Folded Cascode Amplifier . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.2 Amplifier with Gain Enhancement Using VCs . . . . . . . . . 99
5.3.3 Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.4 Comparison of the Rival Kernels for Analog IC Sizing
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.4.1 Single-Stage Amplifier with Gain Enhancement
Using VCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.4.2 Two-Stage Miller Amplifier . . . . . . . . . . . . . . . . . . . . . . 108
5.4.3 LC-Voltage Controlled Amplifier . . . . . . . . . . . . . . . . . . 112
5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6 Layout-Aware Circuit Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1 Motivation for Layout-Aware Circuit Sizing . . . . . . . . . . . . . . . . 121
6.2 Floorplan-Aware Circuit Sizing . . . . . . . . . . . . . . . . . . . . . . . . . 124
Contents xiii

6.2.1 Floorplan-Aware Flow . . . . . . . . . . . . ....... . . . . . . . 124

6.2.2 Analog Module Layout Generator . . . . ....... . . . . . . . 126
6.2.3 Floorplanner . . . . . . . . . . . . . . . . . . . ....... . . . . . . . 129
6.3 Layout-Aware Circuit Sizing. . . . . . . . . . . . . ....... . . . . . . . 134
6.3.1 Electromigration-Aware Global Router. ....... . . . . . . . 135
6.3.2 Parasitic Devices Extraction . . . . . . . . ....... . . . . . . . 136
6.3.3 Back-Annotation and Simulation of the Parasitics . . . . . . . 141
6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . ....... . . . . . . . 145
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... . . . . . . . 145
7 AIDA-C Layout-Aware Circuit Sizing Results. . . . . . . . . . . . . . . . . 147
7.1 Single Stage Folded Cascode Amplifier with Bias . . . . . . . . . . . . 147
7.2 Two-Stage Miller Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.2.1 Floorplan-Aware Design . . . . . . . . . . . . . . . . . . . . . . . . 150
7.2.2 Layout-Aware Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.3 Two-Stage Folded Cascode Amplifier . . . . . . . . . . . . . . . . . . . . 165
7.4 Single Stage Amplifier with Gain Enhancement Using VCs . . . . . 168
7.4.1 Floorplan-Aware Sizing . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.4.2 Layout-Aware Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
7.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
8.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
8.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Abbreviations

AIDA Analog IC Design Automation

AMG Analog Module Generator
AMOSA Archive-based Multi-Objective Simulated Annealing
AMS Analog- and/or Mixed-Signal
CAD Computer-Aided Design
CMOS Complementary Metal-Oxide-Semiconductor
DOE Design of Experiments
DRC Design-Rule Check
EDA Electronic Design Automation
EM Electromigration
FOM Figure Of Merit
GA Genetic Algorithm
GDS Graphic Database System
GUI Graphical User Interface
HDL Hardware Description Language
IC Integrated Circuit
LDE Layout Dependent Effect
LDS Layout Description Script
LHS Latin Hypercube Sampling
LNA Low-Noise Amplifier
LP Linear Programming
LVS Layout-Versus-Schematic
MC Monte Carlo
MIM Metal-Insulator-Metal
MOEA Multi-Objective Evolutionary Algorithm
MOM Metal-Oxide-Metal
MOO Multi-Objective Optimization
MOPSO Multi-Objective Particle Swarm Optimization
MOSA Multi-Objective Simulated Annealing
NSGA Non-dominated Sorting Genetic Algorithm

xv
xvi Abbreviations

OTA Operational Transcondutance Amplifier

POF Pareto Optimal Front
PVT Process, Voltage and Temperature
RF Radio Frequency
SA Simulated Annealing
SO Single-Objective
SoC System-on-a-Chip
SVM Support Vector Machine
UMC United Microelectronics Corporation
VCO Voltage Controlled Oscillator
VLSI Very Large Scale Integration
XML Extensible Markup Language
List of Figures

Figure 1.1 Digital versus analog design automation reality [10]. . . . . . .. 3

Figure 1.2 Common methods to measure the effects of variation around
the nominal circuits’ performance . . . . . . . . . . . . . . . . . . .. 4
Figure 1.3 Hierarchical level and design tasks of design flow
architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6
Figure 2.1 Automatic circuit sizing approaches. a Knowledge-based.
b Optimization-based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2.2 Nominal simulation-based circuit sizing and optimization . . . . 20
Figure 2.3 Variation-aware automatic circuit sizing and optimization . . . . 20
Figure 2.4 Layout-aware automatic circuit sizing and optimization . . . . . 24
Figure 3.1 AIDA overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.2 AIDA-C architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3.3 Pareto front illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.4 Design flow using AIDA-C. . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3.5 AIDA-C design structure . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.6 Single-ended two-stage Miller amplifier. a Parameterized
netlist (circuit.cir). b Schematic. . . . . . . . . . . . . . . . . . . . .. 45
Figure 3.7 AC testbench showing analysis and measures section
(testbench.cir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 46
Figure 3.8 AC testbench for corners showing.alter section
(testbench.corners.cir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3.9 DC measures for ELDO™ AC testbench (testbench*.cir) . . . . 47
Figure 3.10 Extract of the draft of circuit setup (design.xml) . . . . . . . . . . 48
Figure 3.11 Completed of circuit setup (design.xml) . . . . . . . . . . . . . . . . 49
Figure 3.12 Graphical representation of a template showing the relative
location of the devices. (Reprinted from Integration,
the VLSI Journal, 48, Nuno Lourenço, António Canelas,
Ricardo Póvoa, Ricardo Martins, Nuno Horta,
Floorplanaware analog IC sizing and optimization based
on topological constraints, 183–197, Copyright (2015), with
permission from Elsevier) . . . . . . . . . . . . . . . . . . . . . . . . .. 50

xvii
xviii List of Figures

Figure 3.13 Part of the XML description of the layout guides (floorplan.
xml), showing the constructs and illustrating the hierarchy,
with part of the sub-floorplan file for partition
P1A shown inline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50
Figure 3.14 AIDA GUI—Main panel . . . . . . . . . . . . . . . . . . . . . . . . .. 51
Figure 3.15 AIDA Optimizer setup controls. a Sizing settings.
b Objectives and constraints. c Variable ranges.
d Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52
Figure 3.16 AIDA-C—Manual edit tool. . . . . . . . . . . . . . . . . . . . . . . .. 55
Figure 3.17 AIDA typical plus corners monitoring plots.
a Convergence plot. b Historic front plot . . . . . . . . . . . . . .. 56
Figure 3.18 Reuse: changing the topology and reusing the previous
solutions as starting point. a Convergence plot. b Historic
front plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 58
Figure 3.19 Reuse: changing the topology and (re)sizing from scratch.
a Convergence plot. b Historic front plot . . . . . . . . . . . . . .. 59
Figure 3.20 Reuse: moving to another technology. . . . . . . . . . . . . . . . .. 59
Figure 3.21 Reuse: (re)sizing in another technology. a Convergence plot.
b Historic Front plot . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
Figure 4.1 Schematic of the simple differential amplifier
and testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 64
Figure 4.2 Algorithms implemented in AIDA-C’s
optimization kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 67
Figure 4.3 Fronts for multiple ranks, and crowding distance
illustration for solution B . . . . . . . . . . . . . . . . . . . . . . . . .. 70
Figure 4.4 Particle update in PSO . . . . . . . . . . . . . . . . . . . . . . . . . . .. 74
Figure 4.5 Different methods to redistribute elements in the parallel
multi-kernel approach. a Shuffle. b Best. c Sorted . . . . . . . .. 76
Figure 4.6 Latin hypercube design with 2 variables and 5 levels.
a Design with poor space-filling. b Design with good
space-filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 80
Figure 4.7 Perturbation p.d.f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 84
Figure 4.8 Gradient rules in the mutation operator. . . . . . . . . . . . . . . .. 85
Figure 5.1 Single-ended folded cascade amplifier; a schematic;
b test-bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 88
Figure 5.2 POFs for various crossover rates (32 elem, 200 gen) . . . . . .. 90
Figure 5.3 POFs for various mutation % (32 elem, 200 gen) . . . . . . . .. 90
Figure 5.4 Single stage amplifier with gain enhancement using
voltage combiners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 91
Figure 5.5 Dispersion of the POF limits: a Maximum FOM for various
P/G setups; b Maximum GDC for various P/G setups . . . . .. 93
Figure 5.6 10 POF obtained with P = 128 and G = 1000 . . . . . . . . . . .. 94
Figure 5.7 POF obtained using the 3 design strategies T, TC and C . . .. 95
List of Figures xix

Figure 5.8 Fully differential telescopic amplifier schematic: a bias;

b amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 97
Figure 5.9 2D Projections of the 3D POF obtained using T and TC . . .. 98
Figure 5.10 AIDA-C (for 60,000, 4,000 and 2,000 generations)
versus AIDA-C GM (for 2,000 generations) . . . . . . . . . . . . . 100
Figure 5.11 AIDA-C versus AIDA-C + GM for 20 different initial
populations (for 2,000 generations) . . . . . . . . . . . . . . . . . . . 100
Figure 5.12 Amplifier with gain enhancement using voltage combiners
POF with gradient model . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 5.13 Schematic and test-bench of the 7.9 GHz LNA . . . . . . . . . . . 101
Figure 5.14 LNA Pareto fronts considering the typical specifications . . . . . 103
Figure 5.15 LNA Pareto fronts considering the corner specifications . . . . . 103
Figure 5.16 Pareto fronts for the different runs of NSGA-II, MOPSO
and MOSA for Runset I . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 5.17 Pareto fronts for the different runs of NSGA-II, MOPSO
and MOSA for Runset II . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 5.18 Evolution of the best FOM, GBW, and IDD with the number
of simulations for the 10 run. e and f show the number
of runs without feasible solutions. a Runset I—best figure
of merit. b Runset II—best figure of merit. c Runset I—best
bandwidth. d Runset II—best bandwidth. e Runset I—best
power of consumption. f Runset II—best power
of consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 5.19 2-stage Miller amplifier schematic . . . . . . . . . . . . . . . . . . . . 108
Figure 5.20 Pareto fronts for the different runs of the NSGA-II, MOPSO
and MOSA on the Two-Stage amplifier problem
for Runset I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 5.21 Pareto fronts for the different runs of the NSGA-II,
MOPSO and MOSA on Two-Stage amplifier problem
for Runset II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 5.22 Evolution of the best FOM, GBW, and IDD with the number
of simulations in the Two-Stage amplifier runsets.
e and f show the number of runs without feasible solutions.
a Runset I—best figure of merit. b Runset II—best figure
of merit. c Runset I—best bandwidth. d Runset II—best
bandwidth. e Runset I—best current consumption.
f Runset II—best current consumption . . . . . . . . . . . . . . . . . 111
Figure 5.23 Schematic of the LC-VCO . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 5.24 Progression of the Pareto front with the number
of simulations for the different runs of the NSGA-II,
MOPSO and MOSA for Runset I . . . . . . . . . . . . . . . . . . . . 114
Figure 5.25 Progression of the Pareto front with the number
of simulations for the different runs of the NSGA-II,
MOPSO and MOSA for Runset II . . . . . . . . . . . . . . . . . . . . 114
xx List of Figures

Figure 5.26 Evolution of the best P, PN, and FOM with the number
of simulations in the LC-VCO runsets. a Runset I—best
power consumption. b Runset II—best power consumption.
c Runset I—best phase noise. d Runset II—best phase noise.
e Runset I—best figure of merit. f Runset II—best
figure of merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 5.27 LC-VCO multi-objective optimization result for corner
conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 6.1 Traditional design flow: iterations between electrical
and physical design phases . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 6.2 Optimization based layout-aware sizing flow . . . . . . . . . . . . . 123
Figure 6.3 Floorplan-aware evaluation flow . . . . . . . . . . . . . . . . . . . . . 124
Figure 6.4 A set of placement solutions for the same template
and same sizing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 6.5 Analog Module Generator architecture . . . . . . . . . . . . . . . . . 126
Figure 6.6 Example of transistors produced by the AMG: a Folded
transistor of 4 fingers with connections over the device;
b Folded transistor with 22 fingers, 2 rows and connections
outside the device; c Merge of 2 transistors, one with
2 fingers, the other with 10, with both gates and sources
connected; d Interdigitated of two transistors with 6 fingers;
e Common-centroid of 2 transistors with
16 fingers each . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 6.7 Example of passive devices produced by the AMG.
a MOM capacitor. b MIM capacitor.
c Polysilicon resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 6.8 B*-Tree and Slicing-Tree showing the flexibility
of the non-slicing structure for different sizes . . . . . . . . . . . . 129
Figure 6.9 Multiple B*-Trees extracted from the floorplans . . . . . . . . . . 130
Figure 6.10 Devices generated using the AMG and corresponding
bounding box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 6.11 Multiple floorplan packing for a sizing solution: a, b,
c B*-Trees; d placement for the B*-Tree (a) with an area
of 361.7 µm2; e placement for the B*-Tree (b) with an area
of 634.7 µm2; f placement for the B*-Tree (c) with an area
of 448.6 µm2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 6.12 Best placement showing the devices’ layout. Reprinted from
Integration, the VLSI Journal, 48, Nuno Lourenço, António
Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Horta,
Floorplanaware analog IC sizing and optimization based on
topological constraints, 183–197, Copyright (2015), with
permission from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 6.13 Layout-aware evaluation flow . . . . . . . . . . . . . . . . . . . . . . . 134
List of Figures xxi

Figure 6.14 Global routing procedure: a Schematic highlighting

the illustrated nets; b Netlist and generic electric-currents
associated to each terminal; c EM-aware wiring topology
and d global routing. The wires’ widths are function
of the electric-current imposed on them . . . . . . . . . . . . . . . . 137
Figure 6.15 Different capacitances considered in the 2.5-D model . . . . . . . 139
Figure 6.16 Extracted capacitors and shapes considered: a transistor
MOSFET M1 zoomed from the floorplan; b Transistor’s
shapes considered to compute the capacitance gate-source
Cgs; c Transistor’s shapes considered to compute the
capacitance gate-drain Cgd; d Transistor’s shapes considered
to compute the capacitance drain-source Cds; Some Clateral
components were illustrated, the total parasitic capacitance is
the sum of all partial parasitic components (e) between
a device’s terminal and a path of the global routing,
and, on (f), between terminals of a different devices. . . . . . . . 140
Figure 6.17 Parasitic interconnect resistance computed
by square counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 6.18 p2 model for the wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 6.19 Wiring topology for net N2 . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 6.20 Parasitic netlist for net N2: a N2: wires parasitic RC devices;
b N2: terminal-bulk capacitors; c N2: resistors and bulk
capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 6.21 Parasitic netlist coupling capacitances: terminal-terminal,
terminal-wire and wire-wire . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 7.1 Schematic of the single-ended folded cascode
amplifier with bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 7.2 Floorplan template for the single-ended folded cascode
amplifier with bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 7.3 POF obtained with floorplan-aware sizing of the folded
cascode amplifier with bias . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 7.4 Floorplan of the 4 designs for the folded cascode amplifier
with bias marked in the corners’ POF: Point 1 to Point 4.
All floorplans placed at the same scale . . . . . . . . . . . . . . . . . 149
Figure 7.5 Schematic of the two-stage Miller amplifier . . . . . . . . . . . . . 150
Figure 7.6 Top-level floorplans for the two-stage Miller: a floorplan T1;
b floorplan T2; c floorplan T3. . . . . . . . . . . . . . . . . . . . . . . 151
Figure 7.7 Floorplans for partition P1 of the two-stage Miller amplifier:
a floorplan P1A; b floorplan P1B; c floorplan P1C;
d floorplan P1D. Reprinted from Lourenço [3], Copyright
(2015), with permission from Elsevier . . . . . . . . . . . . . . . . . 152
xxii List of Figures

Figure 7.8 Floorplan T3c for the two-stage Miller amplifier obtained
from the combination of T3 with P1c. Reprinted
from Lourenço [3], Copyright (2015), with permission
from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 7.9 Fronts obtained with 5 runs for the four scenarios high-
lighting the WCPF. Reprinted from Lourenço [3], Copyright
(2015), with permission from Elsevier . . . . . . . . . . . . . . . . . 153
Figure 7.10 WCPF fronts for the 4 scenarios, identifying the most
frequent floorplans in the scenario with the 12 floorplans.
Reprinted from Lourenço [3], Copyright (2015), with
permission from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 7.11 Pareto fronts for the new specifications of the two-stage
Miller amplifier, obtained with 3 runs for the four scenarios,
highlighting the WCPF. Reprinted from Lourenço [3],
Copyright (2015), with permission from Elsevier . . . . . . . . . . 155
Figure 7.12 WCPF fronts for the 4 scenarios, identifying the floorplans
most used in the scenario with the 12 floorplans for the new
specifications. Reprinted from Lourenço [3], Copyright
(2015), with permission from Elsevier . . . . . . . . . . . . . . . . . 156
Figure 7.13 Placement for the designs showing a gain of 55 dB in all
scenarios: a Sum of devices’ area; b T1a; c T3c;
d All (all layouts are shown in the same scale).
Reprinted from Lourenço [3], Copyright (2015),
with permission from Elsevier . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 7.14 Floorplan and layout-aware optimization POFs . . . . . . . . . . . 160
Figure 7.15 Layout for the 51 dB designs: a Layout for the 53 dB
solution of the traditional simulation-based sizing, obtained
using AIDA-L; b Layout obtained using the layout-aware
flow, with only global routing for the 51 dB solution.
c Layout after the detailed routing . . . . . . . . . . . . . . . . . . . . 161
Figure 7.16 Layout for the 75 dB (d–f) designs: a Layout for the 75 dB
solution of the traditional simulation-based sizing, obtained
using AIDA-L; b Layout obtained using the layout-aware
flow, with only global routing for the 75 dB solution;
c Layout after the detailed routing . . . . . . . . . . . . . . . . . . . . 162
Figure 7.17 Floorplan, layout-aware and layout-aware after floorplan
corner optimization POFs . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 7.18 Schematic of the two-stage folded cascode amplifier.
Reprinted from Lourenço [2], Copyright (2016), with
permission from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 7.19 Floorplan templates for the two-stage folded cascode
amplifier. Reprinted from Lourenço [2], Copyright (2016),
with permission from Elsevier . . . . . . . . . . . . . . . . . . . . . . . 166
List of Figures xxiii

Figure 7.20 Traditional and Layout-aware optimization POFs. Reprinted

from Lourenço [2], Copyright (2016), with permission from
Elsevier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 7.21 a Layout obtained from traditional design (fails specs in post
layout) and b Layout obtained from layout-aware
(post-layout correct). Reprinted from Lourenço [2],
Copyright (2016), with permission from Elsevier . . . . . . . . . . 168
Figure 7.22 Schematic of the single stage amplifier with gain
enhancement using VCs. Reprinted from Lourenço [2],
Copyright (2016), with permission from Elsevier . . . . . . . . . . 169
Figure 7.23 Floorplan template and manual layout for the single stage
amplifier with gain enhancement using VCs: a Floorplan
template; b Manual layout . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 7.24 AIDA screenshot showing the solution obtained using
the floorplan-aware sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 7.25 Floorplan templates for the single stage amplifier
with gain enhancement using VCs. Reprinted from Lourenço
[2], Copyright (2016), with permission from Elsevier . . . . . . . 172
Figure 7.26 Pareto sets for the single stage amplifier with gain
enhancement using VCs. Reprinted from Lourenço [2],
Copyright (2016), with permission from Elsevier . . . . . . . . . . 172
Figure 7.27 Layout for the single stage amplifier solutions shown
in Table 7.15. a Nominal, b worst case, c worst-case
and layout-aware. Reprinted from Lourenço [2],
Copyright (2016), with permission from Elsevier . . . . . . . . . . 173
Figure 8.1 AIDA-C in analog IC design flow . . . . . . . . . . . . . . . . . . . . 178
List of Tables

Table 2.1 Overview of layout-aware sizing tools . . . . . . . . . . . . . . . . .. 25

Table 2.2 Summary of advantages and shortcomings of the techniques
applied to circuit sizing tools . . . . . . . . . . . . . . . . . . . . . . .. 26
Table 2.3 Summary of circuit sizing tools . . . . . . . . . . . . . . . . . . . . . .. 27
Table 4.1 Parameters ranges for the differential amplifier example . . . . .. 65
Table 4.2 Objectives and specifications for the differential amplifier
example as commonly defined by the analog designer . . . . . . . 65
Table 4.3 fm(x) and gj(x) for the differential amplifier example. . . . . . . . . 65
Table 4.4 Association between range values and DOE’s level . . . . . . . . . 78
Table 4.5 DOE’s matrix for full factorial design . . . . . . . . . . . . . . . . . . 78
Table 4.6 DOE’s matrix for fractional factorial design with x2
non-elementary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 79
Table 4.7 DOE’s matrix for fractional factorial design with x1
non-elementary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 4.8 Main-effect obtained from the full factorial design . . . . . . . . . . 81
Table 4.9 Main-effect obtained from the fractional factorial designs . . . . . 81
Table 4.10 Extraction of gradient rules for DC Gain . . . . . . . . . . . . . . . . 82
Table 4.11 Extraction of gradient rules for GBW. . . . . . . . . . . . . . . . . . . 82
Table 4.12 Set of gradient rules for DC Gain . . . . . . . . . . . . . . . . . . . . . 83
Table 4.13 Set of gradient rules for GBW . . . . . . . . . . . . . . . . . . . . . . . 83
Table 5.1 Single-ended folded cascode amplifier variable ranges . . . . . . . 88
Table 5.2 Single-ended folded cascode amplifier specifications . . . . . . . . 89
Table 5.3 Single stage amplifier with gain enhancement using VCs:
variable and ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 91
Table 5.4 Single stage amplifier with gain enhancement using VCs:
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 92
Table 5.5 Summary of the corner and typical plus corner run illustrated
in Fig. 5.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 5.6 Fully differential telescopic amplifier: variable’s ranges . . . . . . 97
Table 5.7 Fully differential telescopic amplifier: specifications . . . . . . . . . 97
Table 5.8 Summary of the synthesis results . . . . . . . . . . . . . . . . . . . . . . 98

xxv
xxvi List of Tables

Table 5.9 Single-ended folded cascode amplifier: specifications II . . . . . . 99

Table 5.10 Gradient rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 5.11 AIDA-C versus AIDA-C + GM (2,000 generations). . . . . . . . . 100
Table 5.12 LNA variable ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 5.13 LNA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 5.14 Considered corner cases conditions . . . . . . . . . . . . . . . . . . . . 103
Table 5.15 LNA worst case measures for corner results . . . . . . . . . . . . . . 104
Table 5.16 Variables and ranges for the 2-stage Miller
amplifier optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 5.17 Objectives and specifications for the 2-stage
Miller amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 5.18 Objectives and specifications for the LC-VCO design . . . . . . . 113
Table 5.19 Variables and ranges for the LC-VCO design . . . . . . . . . . . . . 113
Table 5.20 Solutions details for all corner cases . . . . . . . . . . . . . . . . . . . 117
Table 5.21 Summary of the most competitive LC-VCO solutions,
showing other SOA results . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 6.1 Post-layout measures: partial and complete extraction
with AIDA and with Mentor Graphics’ Calibre® . . . . . . . . . . . 144
Table 7.1 Variables and ranges for the single-ended folded cascode
amplifier with bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 7.2 Objectives and specifications for the single-ended folded
cascode amplifier with bias . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 7.3 Variables and ranges for the two-stage Miller amplifier . . . . . . 151
Table 7.4 Objectives and specifications for the two-stage
Miller amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 7.5 Experimental results for the four scenarios, reprinted
from Lourenço [3], Copyright (2015), with permission
from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 7.6 Pre and post-layout simulation of the two-stage amplifier
designs around 55 dB obtained using the floorplan-aware
sizing flow, reprinted from Lourenço [3], Copyright (2015),
with permission from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 7.7 Specifications and objectives for the 200 MHz two
stage amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 7.8 Design Variables and Ranges for the for the 200 MHz
two stage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 7.9 Pre/Post-Layout Simulation for nominal case for the 200 MHz
two stage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 7.10 Pre/post-layout simulation for worst-case for the 200 MHz
two stage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 7.11 Variables and ranges for the two-stage folded
cascode amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
List of Tables xxvii

Table 7.12 Performance comparison for the traditional and layout-aware

optimizations, reprinted from Lourenço [2], Copyright (2016),
with permission from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 7.13 Variables and ranges for the single stage amplifier with gain
enhancement using VCs, reprinted from Lourenço [2],
Copyright (2016), with permission from Elsevier . . . . . . . . . . . 169
Table 7.14 Specifications for the single stage amplifier with gain
enhancement using VCs, reprinted from Lourenço [2],
Copyright (2016), with permission from Elsevier . . . . . . . . . . . 170
Table 7.15 Performance of the single stage amplifier for solution
with lowest power in each optimization stage, reprinted
from Lourenço [2], Copyright (2016), with permission
from Elsevier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Chapter 1
Introduction

In the last decades very large scale integration technologies have been widely
improved, allowing the proliferation of consumer electronics and enabling the steady
growth of the IC market from $10 billion in 1980 to an estimated value of over than
$350 billion in 2016 [1]. The steady increase in performance of ICs in the recent past
has been mostly supported by an exponential growth in the density of transistors
while inversely reducing the transistors’ cost, as described by Moore’s law [2].
Moore’s law is a law of economics not physics, and Moore itself already preconized
its end, as such an exponential law “can’t continue forever” and is pushing for new
technologic advancements outside complementary metal-oxide-semiconductor
(CMOS) IC design, but it is still valid today.
In this context, the increasing need of faster, optimized and reliable electronic
devices urges their cost-effective development to efficiently meet customers’
demand under highly competitive time-to-market pressure [3]. Moreover, the
design of such complex multimillion transistor ICs is only possible because
designers are assisted by computer aided design (CAD) and design automation tools
that support the design process.

1.1 Analog IC Design Automation

As analog ICs are difficult to design and reuse, designers have been replacing analog
circuits by digital computing whenever possible. Hence, most of the high-level
functions are implemented using digital or digital signal processing, however analog
and radio frequency (RF) circuitry is needed to interface with the real world, and
some functionalities that are intrinsically analog [3, 4] are listed below:
• Sensing the system inputs: The signals of a sensor, microphone or antenna has
to be detected or received, amplified and filtered, to enable digitalization with
good signal-to-noise and distortion ratio. Typical applications of these circuits
are in sensor interfaces, telecommunication receivers or sound recording;

© Springer International Publishing Switzerland 2017 1

N. Lourenço et al., Automatic Analog IC Sizing and Optimization Constrained
with PVT Corners and Layout Effects, DOI 10.1007/978-3-319-42037-0_1
2 1 Introduction

• Converting analog signals to digital signals: Mixed-signal circuits such as

sample-and-hold, analog-to-digital converters, phase-locked loops and fre-
quency synthesizers provide the interface between the input/output of a system
and digital processing parts of a system-on-chip (SoC);
• Converting the digital output back to analog: The signal from digital pro-
cessing must be converted and strengthened to analog so the signal can be
conducted to the output with low distortion;
• Provide and regulate power: Voltage/current reference circuits and crystal
oscillators offer stable and absolute references for the sample-and-hold,
analog-to-digital converters, phase-locked loops and frequency synthesizers;
• The implementation at transistor level of the digital gates: The last kind of
analog circuits are the extremely high performance digital circuits. As exem-
plified by microprocessors that are custom sized, as analog circuits, to achieve
highest speed and lowest power consumption.
Telecommunications, medical and multimedia applications make extensive use
of electronic devices where blocks of analog and mixed-signal (AMS), digital
processors and memory blocks are integrated together [5]. The growth in
Medical/Health, automotive, LED lighting, and energy management for buildings is
likely to keep analog needs growth. In 1980, analog ICs represented 32 % of total
IC shipments, that value increased to 49 % in 2010, and is forecast to grow to 57 %
of total IC shipments by 2018 [6]. In this context, the development and improve-
ment of CAD tools that increase analog designers’ productivity is an urgent need.
In the digital IC design several mature electronic design automation (EDA) tools
and design methodologies are available that help the designers keeping up with the
new capabilities offered by the technology, and, making circuit reuse usual, leading
to an increased design productivity. Currently almost all low-level phases of the
process are automated. The system is described in a hardware description language
(HDL) such as VHDL or Verilog, either at the behavioral level or at the structural
level. High-level synthesis tools attempt to synthesize the behavioral HDL
description into a structural representation. Logic synthesis tools then translate the
structural HDL specification into a gate-level netlist, and semi-custom layout tools
(place and route) map this netlist into a correct-by-construction mask-level layout
based on a cell library specific for the target technology process.
Research interest is moving in the direction of system synthesis where a
system-level specification is translated into hardware–software co-architecture with
high-level specifications for hardware, software and interfaces. Reuse methodolo-
gies and platform-based design methodologies are also being developed to reduce
even further the design effort for complex systems. The level of automation is far
from the push-button stage, but the developments are keeping up reasonably well
with the circuits’ complexity supported by the technology [3, 4].
On the other hand, and despite the algorithms and techniques introduced in the
last 25 years, analog IC design automation tools strive to keep up with the new
challenges created by technological evolution [4, 7–9]. Designers’ exploration of
the solution space is mostly manual, elongating the time needed to complete the
1.1 Analog IC Design Automation 3

Fig. 1.1 Digital versus analog design automation reality [10]

design task. Generally the complexity of designing analog circuits’ is not due to the
number of devices, but from the countless interactions between them. Plus, for
smaller technology nodes with the increasing complexity of design rules and
physical effects, the impact of these interactions is even greater.
Due to the nature of the signals handled, analog circuits are more sensitive to
parasitic disturbances, crosstalk, substrate noise, supply noise, thermal noise, etc.,
and the variety of schematics and diversity of devices’ sizes and shapes are much
larger [4, 8]. The result of this automation deficit is that, while analog parts in a SoC
occupy only approximately 20 % of the global circuit area, as shown in Fig. 1.1,
the design effort is considerably higher in comparison to the design effort of the
digital section.
This difference in the level of automation between analog and digital design is
because analog is, in general, less systematic, more heuristic and knowledge
intensive than the digital counterpart, and becomes critic when digital and analog
circuits are integrated together. As the analog automation tools do not progress at
the same pace of technology, knowledge and experience of the designer is always
crucial for making decisions at all stages of the analog design flow.
In short, the development time of analog blocks is considerably higher when
compared to the development time of the digital one. The three main reasons for the
larger development time are: there is a lack of effective EDA tools; analog circuits
are being integrated using technologies optimized for digital circuits; and, analog
blocks are difficult to reuse because they are more sensitive to surrounding circuitry,
environmental and process variations than their digital counterpart [3, 4].

1.1.1 Robustness in Analog IC Design

As mentioned, despite the advantages that new fabrication technologies bring to

systems’ performance, the huge increase in device density did not came only with
4 1 Introduction

benefits. This is especially true for analog circuits. The reduced size and high
density of devices in modern ICs add new challenges to analog designers, as the
effects of non-idealities and variability of the fabrication process parameters in both
space and time became more significant. This phenomenon affects devices in dif-
ferent chips but also devices within the same chip, and is solved by robust circuit
design with several compensatory techniques [11] to ensure that the vast majority of
the fabricated circuits will work according to specifications.
The most common techniques for analog design centering are Monte Carlo
Simulation, process, voltage and temperature (PVT) Corners and Worst Case
Corners. Monte Carlo simulation executes many simulations by applying random
variations to circuit’s and process’ parameters, making a stochastic sampling of the
behaviors of the circuit in real world conditions. PVT Corner is a worst-case
approach where the circuit is simulated over multiple combinations of extreme
process parameters, voltage supply and temperature variations. Another kind of
worst case approach is the worst case corners, which are the set of environment and
process parameters that lead to the worst case value for performance figures.
Figure 1.2 illustrates 8 corners cases obtained by considering 3 values for power
supply, operating temperature and process parameters, together with a set of Monte
Carlo samples around the nominal performance for performance figures P1 and P2,
and the worst case corners for each performance (higher is better) [12].
Layout-induced parasitic effects are also more and more significant, having the
potential to affect noticeably the performance of the sized circuit. To overcome the
increasing impact of layout parasitic effects in circuit’s performance, sizing and
layout design phases tend to overlap. The integration of layout generation or
layout-related data in the sizing optimization process helps to account for the effects
of such non-idealities and parasitic disturbances earlier in the design flow, reducing
the number of iterations required to achieve designs that meet post-layout specifi-
cations. It is also important to note that careful layout considerations, like sym-
metry, matching, isolation, proximity, thermal balancing, etc., really help to
mitigate some of the problems introduced by the spatial variability [13–15].

Fig. 1.2 Common methods

Nominal
to measure the effects of
PVT Corners
variation around the nominal
Monte Carlo Samples
circuits’ performance
Worst Case Corners
P2
Worst P2

Worst P1
P1
1.1 Analog IC Design Automation 5

1.1.2 Computer Assisted Analog IC Design

The systems’ complexity and the extremely competitive markets obligate the use of
CAD tools to enhance the design process. Today’s analog design environment is
made of CAD tools for analog IC design editing, evaluation and verification that are
mature and fully deployed in the industrial environment, the following list some
examples:
• Simulation tools: ADiT, Questa and Eldo [16]; HSPICE, nanosim and HSim
[17]; Spectre [18]; SMASH [19].
• Layout edition: Virtuoso Layout Editor [18]; IC Station Layout [16]; Galaxy
Custom Designer LE [17].
• Design rule verification and layout extraction: DIVA and Assura [18]; Hercules
[17]; CALIBRE [16].
• Integrated platforms like Mentor Graphics IC design Manager [16] or Cadence
Virtuoso Analog Design Environment [18].
The time required to manually implement an analog project is usually of weeks
or months, which is in opposition to the market pressure to accelerate the release of
new and high performance ICs. To address all these difficulties and solve the
problems, EDA tools are a solution increasingly strong and solid. Some commercial
automation solutions began to emerge as the result of the research efforts in this
field, such as ADA’s Genius product line and Magma Titan that were integrated in
Synopsys (2004 and 2012 respectively) [17], the circuit optimizer feature of
Cadence’s Virtuoso Custom Design Platform GXL [18], Solido’s Fast PVT, Fast
Monte Carlo and High-Sigma Monte Carlo [20] or MunEDA’s WiCkeD™ [21].
Even if applicable only at cell level, analog components with 10–100 devices [8],
they increase the automation level of the analog design environment.
Despite its fundamental aid to designers, the automation options are limited and
the ones available are not usually used by the majority of the designers. These tools
should play a key role in analog IC design productivity, as they speed up the design
process and increase tractability. However, the lack of mature and robust
automation tools still leads to handcrafted design, and analog design automation is
still a topic of intensive research effort.

1.2 Analog IC Design Flow

Before proceeding into analog IC circuit design automation details, a brief overview
on the analog design flow is first provided. Due to the nature of analog design, it is
difficult to identify one unique design flow. Nevertheless, a typical and well
accepted design flow for AMS ICs was proposed by Gielen and Rutenbar in [4]. It
consists of a series of top-down topology selection and circuit sizing steps and
bottom-up layout generation and extraction steps. Before passing between any of
6 1 Introduction

More Specification Layout

Abstract

System Circuit-Level
Level
Backtracking Topology

Layout-Aware Circuit Sizing

Selection
Validation Verification
...
...

Redesign
Redesign Tradicional
Circuit Sizing Extraction
Circuit
Level
Layout
Verification
Backtracking Generation
Validation

Redesign Devices (Models &Characterization)

Device
Level
Specification Layout
More Top-Down Electrical Bottom-Up Physical
Concrete Synthesis Synthesis

Fig. 1.3 Hierarchical level and design tasks of design flow architectures

the hierarchy levels, in both top-down and bottom-up path, verification is performed
to ensure the specifications are met. The design flow is illustrated in Fig. 1.3,
considering only system-level and cell-level without the loss of generality.
On the top-down path, the Topology Selection is the process where a set of
blocks and the connections between them in defined in order to implement the input
specifications of the current hierarchy level. In the Circuit Sizing task, the
higher-level specifications are translated in the specifications for each of the blocks.
Block specifications may be the definition of the DC Gain and Bandwidth for an
amplifier, or the sizes of the transistors, depending on the models used in that
abstraction level. The sizing is then verified to ensure the fulfillment of the input
specifications. Then, the specifications for each block are passed to the next level of
the hierarchy, and the process is repeated until the layout of the innermost block is
done. At this point, the bottom-up flow is executed. First, the layout of the current
level is generated from the layouts of the deeper hierarchy, then, the layout is
extracted to a model suitable for verification. When the top-most level verification
is complete, the system is designed. It is important to note that any of the many
verification stages throughout the design cycle may detect potential problems, with
the design failing to meet the target specifications. In that case, backtracking and
redesign will be needed.
The number of hierarchy levels depends on the complexity of the system being
handled and there are no generally accepted representations. The same authors in
[22] defined the cell-level and system-level, where the cell-level was defined as
analog components with 10–100 devices, examples of such circuits are OTAs,
Random documents with unrelated
content Scribd suggests to you:
 The Project Gutenberg eBook of Whist; or,
Bumblepuppy? Thirteen Lectures Addressed to
Children
 This ebook is for the use of anyone anywhere in the United
States and most other parts of the world at no cost and with
almost no restrictions whatsoever. You may copy it, give it away
or re-use it under the terms of the Project Gutenberg License
included with this ebook or online at www.gutenberg.org. If you
are not located in the United States, you will have to check the
laws of the country where you are located before using this
eBook.

Title: Whist; or, Bumblepuppy? Thirteen Lectures Addressed to

Children

Author: John Petch Hewby

Release date: February 8, 2017 [eBook #54135]

Most recently updated: October 23, 2024

Language: English

Credits: E-text prepared by Emmy, MFR, and the Online

Distributed Proofreading Team (http://www.pgdp.net)
from page images digitized by the Google Books
Library Project (http://books.google.com and
generously made available by Internet Archive
(https://archive.org)

*** START OF THE PROJECT GUTENBERG EBOOK WHIST; OR,

BUMBLEPUPPY? THIRTEEN LECTURES ADDRESSED TO CHILDREN
***
 The Project Gutenberg eBook, Whist or Bumblepuppy, by John
Petch Hewby

Note: Images of the original pages are available through Internet

Archive. See
https://archive.org/details/whistorbumblepu00unkngoog

WHIST
OR
BUMBLEPUPPY
THIRTEEN LECTURES ADDRESSED
TO CHILDREN.

BY
 PEMBRIDGE.
“Ingenuas didicisse fideliter artes
Emollunt mores, nec sinuisse feros.”—The Newcomes.

Revised and Enlarged Edition.

London:
FREDERICK WARNE & CO.,
Bedford Street, Strand.

MUDIE & SONS,

15 Coventry Street, W.
1895.

·
LONDON:
PRINTED BY GEO. W. JONES,
35 ST. BRIDE ST., E.C.
·
WHIST; OR BUMBLEPUPPY?
———
“We have been rather lengthy in our remarks on this
book, as it is the best attempt we have ever seen to
shame very bad players into trying to improve, and also
because it abounds with most sensible maxims, dressed
up in a very amusing and palatable form.”—The Field.
“‘Whist; or Bumblepuppy?’ is one of the most
entertaining and at the same time one of the soundest
books on Whist ever written. Its drollery may blind some
readers to the value of its advice; no man who knows
anything about Whist, however, will fail to read it with
interest, and few will fail to read it with advantage. Upon
the ordinary rules of Whist ‘Pembridge’ supplies much
sensible and thoroughly amusing comment. The best
player in the world may gain from his observations, and a
mediocre player can scarcely find a better counsellor.
There is scarcely an opinion expressed with which we do
not coincide.”—Sunday Times.
“Lectures on the points most essential to the
acquisition of a complete knowledge of the game. The
lessons here given will well repay perusal.”—Bell’s Life.
“All true lovers of Whist will give a hearty welcome to
this work. It is a small book, but full of weighty matter.
We have not space to analyse the positive rules laid down
by ‘Pembridge’ for the guidance of those who wish to
qualify as Whist players. Suffice it to say that they are all
sound, and most of them worth committing to
memory.”—Sportsman.
“It would be very easy to write at greater length than
we have done in praise of ‘Pembridge’s’ little book. But
we have said enough to indicate its nature and scope;
and we feel sure that any of our readers who may meet
with it will endorse our verdict that it is a real addition to
the literature of Whist.”—Australasian.
 CONTENTS.
page
LECTURE I.—Introductory 1
LECTURE II.—The Lead 11
LECTURE III.—The Play of the Second, Third, and Fourth Hand 26
LECTURE IV.—Discarding, and its Difficulties 32
LECTURE V.—The Discard from the Strongest Suit (Part I.; Part II.) 46
LECTURE VI.—The Eleven Rule 55
LECTURE VII.—The Peter and its Peculiarities 59
LECTURE VIII.—False Cards, Logic, Luck 69
LECTURE IX.—Whist as an Investment 74
LECTURE X.—On Things in General 81
LECTURE XI.—Thinking 93
LECTURE XII.—Temper 99
LECTURE XIII.—Deterioration of Whist, its Causes and Cure 105
BUMBLEPUPPY IN EXCELSIS 111
THE DOMESTIC RUBBER, Double Dummy 113
EPILOGUE I. 115
EPILOGUE II. 117
 PREFACE.
——
These remarks are addressed to the young, in the hope that when
they arrive at man’s estate they will use their best endeavours to do
away with Law 91.
To the present generation, already acquainted with “the Game,” I
should no more presume to offer advice than I should presume to
teach my lamented Grandmother to suck eggs, if she were still alive.
“To instruct them, no art could ever reach,
No care improve them and no wisdom teach.”
Proverbs, chap. 27, v. 22.
 LECTURE I.
——
INTRODUCTORY.
——
“Vacuis committere venis
Nil nisi lene decet.”—Eton Grammar.
“Those that do teach young babes
Do it with gentle means and easy tasks.”—Shakespeare.

A s, humanly speaking, you will probably play something for the

next fifty years, should you select either Whist or Bumblepuppy,
[1] it will be as well for your own comfort—the comfort of others is a
minor consideration[2]—to have some idea of their general
principles; but first you must decide which of these two games you
intend to play, for though they are often confounded together, and
are both supposed to be governed by the same ninety-one laws and
a chapter on etiquette, they differ much more distinctly than the
chalk and cheese of the present day. Professor Pole in his “Theory of
Whist,” Appendix B, has made a very skilful attempt (by modifying
the maxims of Whist) to make the two games into a kind of
emulsion. I was rather taken with this, and having been informed
that the most incongruous materials will mix, if you only shake them
together long enough, I have given this plan a fair trial, and failed.
It may be that I had not sufficient patience and perseverance, but
the principal cause of failure I found to be this: the Bumblepuppist,
like Artemus Ward’s bear, “can be taught many interesting things but
is unreliable;” he only admires his own eccentricities, and if a person
of respectable antecedents gets up a little pyrotechnic display of
false cards for his own private delectation, the Bumblepuppist utterly
misses the point of the joke, he fails even to see that it is clever: if
such a comparison may be drawn without offence, he doesn’t
consider that what is sauce for the goose is sauce for the gander.
In the face of this difficulty, I should recommend you to treat
them as separate games: as you go down in one scale and up in the
other they closely approximate; that extremes meet is a law of
nature, and between the worst Whist and the best Bumblepuppy it is
almost impossible to draw the line.
Other elementary forms, protozoa for instance, are often so much
alike that it is difficult to decide whether they are plants or animals;
but representative specimens of each game, beyond being found at
the same table, (in scientific slang, having the same habitat,) have
scarcely one point in common, you might just as reasonably mistake
horse-radish for beef.
If you elect Whist (I shall refer to the laws later on) begin by
learning the leads, and the ordinary play of the second, third and
fourth hand, which you will find in any Whist Book;[3] this can be
done in a few days; then after cutting for partners (see note to Law
14) as soon as the cards are dealt, not before (see note to Law 45),
(1) Take up your hand;
(2) Count your cards (see notes to Laws 42
& 46);
(3) Sort them into suits;
(4) Look them over carefully;
(5) Fix firmly in your memory not only the
trump suit but the trump card, then
(6) Give your undivided attention to the
table, it is there and not in your hand
the game is played;
 (7) See every card played in the order it is
played;[4]
(8) When you deal, place the trump card
apart from the rest of the suit, that
you may know at once which it is.
N.B.—Knowing is always better than the very best thinking, and
generally much more easy: by these simple means you get rid at
once and for ever of all such childish interruptions as “draw your
card!” “who led?” “what are trumps?” “show me the last trick!” and
so ad infinitum, which, by their constant repetition, not merely worry
and annoy the rest of the table, but tend to destroy any clue to the
game that you yourself might otherwise possess.
It is a good plan to sit clear of the table, and then if you are
constrained to drop a few cards, they at any rate fall on the floor,
where they cannot be called.
So far, I have assumed your object to be Whist; if your end and
aim is Bumblepuppy, you need do none of these things; you can
learn the leads and the recognised play—more or less imperfectly—
in a few years by practice, or you can leave them unlearned;
“Build by whatever plan caprice decrees,
With what materials, on what ground you please.”
Cowper.

ignorance imparts variety to the game, and variety is charming. You

can set all laws at defiance, and if any one objects—after much
wrangling—you can refer the matter in dispute to the Westminster
Papers,[5] and hang it up for a month certain: (this is a better plan
than writing to the Field, for there you only get a week’s respite).
Should you be in any doubt whether Whist or the other game is
your vocation, the first half-dozen times you play make it a rule
never to look at the last trick—
“Things that are past are done with.”—Shakespeare.
and if at the end of that time you find the difficulty insuperable, give
up, as hopeless, all idea of becoming a Whist player.

Notes on some of the Laws.

“Vir bonus est quis?
Qui consulta patrum, qui leges jaraque servat.”—Eton Grammar.

I have mentioned that there are ninety-one laws. The wording of

the first is not strictly accurate; it ought to be “The rubber is
generally the best of three games,” for though I myself have never
seen more than four, it may consist of any number, as the following
decisions show:
Decision A.—The rubber is over when one side has won two
games and remembers it has done so: this memory must be brought
to bear before the other side has won two games and remembers it
has done so.
Decision B.—If a game is forgotten, it is no part of the losers’ duty
to remind the winners of the fact.
Law 5.—This law is clear enough; still the first time you revoke
and are found out, if your opponents hold honours and you have
nothing scored—however many you have made by cards—they will
claim a treble: you should be prepared for this. The claim is wrong,
but in spite of that—possibly because of it—“they all do it.”
Law 7.—Decision.—You must call your honours audibly, but you are
not obliged to yell because your adversaries are quarrelling.
Law 14.—Always get hold of the cards before cutting, and place a
high card at one end of the pack and a low one at the other, then
cut last and take either card you prefer: by this means you select
your partner, this is an admirable coup and tends to the greatest
happiness of the greatest number (Note A, page 2) but it must be
executed with judgment, for if you are detected your happiness will
not be increased, rather the reverse. Some purists, anxious to be on
the safe side, only keep an eye on the bottom card, and take it when
it suits them.
Law 34.—Until the last few years, after you had cut the cards into
two distinct packets, if the dealer thought fit to knock one of them
over, leave a card on the table, or drop half-a-dozen or so about, it
was a mis-deal on the ground that these proceedings were opposed
to one or other of the next two laws, 35 and 36, but the latest
decision is that the dealer can maltreat the pack in any way he likes
and as often as he likes, and compel you to keep on cutting de die in
diem.
Old Decision.—“You cannot make your adversary cut a second
time; when you left a card on the table it could not be said that
there was a confusion in the cutting, it is a mis-deal.”
New Decision.—“There is nothing in the laws to make this a mis-
deal. The play comes under the term ‘Confusion of the cards,’ and
there must be a fresh deal.”
If you see a potent, grave, and reverend seignior carefully
lubricating his thumb with saliva, don’t imagine he is preparing it for
deglutition, he is only about to deal. Even if he should swallow it,
why interfere? he will not hurt you; it is not your thumb. Should you
suffer from acute hyperæsthesis you can follow the example of an
old friend of mine, who once rose from the table in his terror, and
returned armed with a large pair of black kid gloves which he wore
during the remainder of the seance: though the effect was funereal
—not to say ghastly—it was attended with the best results in this
case, but it is just as likely to lead to ill-feeling, and therefore to be
deprecated. Leave the matter to time! Apart from the cards being
glazed with lead, a single pack has been found to contain a fifth of
an ounce of arsenic, and there is no known antidote. Even if not
immediately fatal, the practice must be very deleterious. A whist
enthusiast with a greater turn for mathematics than I can lay claim
to, has counted from six to seven thousand bacteria on each square
centimetre of a playing card, and makes this ghastly deduction: “it is
really dreadful to reflect upon the colony of microbes which a person
who moistens his thumb before dealing may convey into his mouth,
and thence into his system.”—Standard, Nov. 2nd, 1893. “Everything
comes to the man who can wait,” and while you are waiting always
sit on the dealer’s right.
Law 37.—An incorrect or imperfect pack is a pack containing
duplicates or more or less than fifty-two cards, but it is neither
incorrect nor imperfect because you think fit to place any number of
your own cards in the other pack, or to supplement them with one
from it. Vide Laws 42, 46.
Law 42.—If you take one card from the other pack, it is clear that
you subject yourself to a penalty; if you take more than one the
matter is not so clear; possibly you may gain by it; should you wish
to have the point settled, any time you have a bad hand add the
other pack to it; then complain that you have sixty-five cards, throw
them up, claim a new deal under Rule 37, and see what comes of it.
Law 45.—Taking up your cards during the deal has one advantage,
that if you can get your hand sorted and begin to play without
waiting for the dealer, you save time, and time is reported to be
money. To counter-balance this there are two attendant
disadvantages, you prevent the possibility of a mis-deal, and any
card exposed by your officiousness gives the dealer the option of a
new deal.
Law 46.—Under this law it is manifest that—the other hands being
correct—your hand may consist of any number of cards from one to
thirteen, and if you once play to a trick—however many you may be
short—you will have to find them or be responsible for them. See
Law 70.
Law 91.—If this law, which is the main cause of inattention and
innumerable improper intimations, were abolished, Whist would be
greatly improved; and I have never met with a good Whist player
who was not of the same opinion.
 The chapter on etiquette is good sense and good English, and is
worthy of much more attention than is usually given to it.
In addition to their ambiguity and sins of commission, there is
also a sin of omission; there is no limit as to time, and it seems
desirable there should be; I would suggest—as allowing the
hesitating player reasonable latitude—one of those sand glasses,
supposed to be useful for boiling an egg; there is no sense in giving
him time enough to addle his egg.
Though these laws appear more difficult of access than I had
imagined, they are not the laws of which the only copy was
destroyed by Moses; I have seen them myself in Clay, Cavendish,
and the “Art of Practical Whist,” and if you are unable to get any of
these works from Mudie’s, there are copies of each in the British
Museum, Great Russell Street, Bloomsbury.
Before or immediately after breakfast is the best time to play;
then, if ever, the intellect is clear, the attention undistracted; in the
afternoon you are exhausted by the labours of the day, and your
evenings should be devoted to the morrow’s lessons or a quiet nap
(not the round game of that ilk).
 LECTURE II.
——
THE LEAD.
——
“Dux nobis opus est.”—Eton Grammar.

“I pray thee now lead.”—Shakespeare.

T he play of the entire hand often depends upon the very first card
led, and the confidence your partner has that your lead is
correct; whatever then your original lead may be, let it be a true and
—as far as you can make it so—a simple lead: never lead an
equivocal card—that is one which may denote either strength or
weakness—if you can, lead a card about which no mistake is
possible.[6] With the original lead, follow the books and lead your
strongest suit; if you have nothing at all, do as little mischief as you
can; in this pitiable condition the head of a short suit—as a knave or
a ten—is better than the lowest or lowest but one of five to the nine;
your partner, when he sees the high card led, knows at once
(assuming he knows anything) that he will have to save the game
himself if it can be saved, and will take the necessary steps to that
end. Though there is ancient and modern authority for this,[7] I am
perfectly aware that (according to the latest theory) it is heresy; I
am also aware, and the reflection gives me quite as much pain as
the heresy does, that leading a long weak suit with a bad hand and
no cards of re-entry is a losing game:
“Such courses are in vain
Unless we can get in again.”

to lead your longest suit when you are neither likely to get the lead
again, nor to make a trick in it if you do, is a “short and easily
remembered rule,” but is apt to bring its followers to grief; if I do so,
I know perfectly well that after the game is over I shall probably be
left with the two long cards of that suit, or I may have an
opportunity of discarding one or both of them before that crisis
arrives, but this is not the slightest consolation to me.
While on the subject of heresy, I may as well refer to another
lead which has a special orthodoxy of its own. In all suits of four or
more, containing no sequence, unless headed by the ace, you either
lead the lowest, or, if you wish particularly to exhibit your knowledge
of the game, the lowest but one; but from king, knave, ten, &c., you
lead the ten, and if your object is a quiet life, you will continue to do
so; if you want to make tricks the advantage of the lead is not so
clear: if the second player holds ace, queen, &c., or queen and
another, you drive him into playing the queen, and so lose a trick,
which if you had led your lowest in the usual way, you might not
have done.[8]
Against this you have the set off that by leading the ten you
insure having the king-card of the suit in the third round, but it is
scarcely worth your while to go through so much to get so little; for
such a lead pre-supposes your partner to have neither ace, queen,
nor nine, and it is two to one that he holds one of them; if your
partner’s best card is below the nine, the tricks you will make will be
like angels’ visits, few and far between, whatever you lead; and why
you should take such a desponding view of an unplayed suit I am
not aware. The advantage of opening a suit in which you hold
tenace is not so great as to oblige you to handicap it by sending the
town-crier round with a bell to proclaim what that tenace is; late in
the hand it is often advisable to lead the knave.
With ace and four small cards and a bad hand, when weak in
trumps, I have found, from long experience, the ace to be a losing
lead, and being distinctly of the impression that for the ordinary
purposes of life, 13/4 = 2, as I am not always anxious to proclaim
the exact number of my suit, I generally lead a small one.
 I am aware that the suit does not always go twice, or even once;
but that is the fault of the cards, not of the equation.
Of course, if, for any wise purpose, you feel you must have one
trick, take it at the first opportunity, irrespective of Cocker or any
other authority.
N.B.—When you, second, third, or fourth player have won the first
trick, whatever you may think, you are not the original leader, and
your lead then should be guided by your own hand; if it is a bad one
you are under no compulsion to open a suit at all, one suit is already
open, go on with that; if it also is a bad one, one bad suit is a less
evil than two bad suits, or opening a doubtful one in the dark; return
through strength up to declared weakness, or if it was your partner
who led, why should you show a suit unless you hold a good
sequence or strong trumps? Return his suit, yours will be led
sometime; whatever you won the trick with, he is in a better position
to defend himself as third player than if he had to lead it again
himself.
In returning your partner’s lead, if you had originally three, you
return the higher of the two remaining cards; in returning through
your adversary’s lead, if you hold the third best and another, play the
small one, for your partner may hold the second best single and they
would fall together.
Whenever you hold a suit with one honour in it, to lead that suit,
if you can avoid it, is about the worst use you can make of it. Should
you fail to see this, devote ten minutes—not when you are playing
whist, but on some wet half-holiday or quiet Sunday afternoon—to
thinking the matter over; even if you have a suit of king, queen to
three, why not be quiet? If anybody else opens the suit you will
probably make two tricks, if you open it yourself, probably one;
there is no hurry about it, you can always do that, but why you
should go out of your way to lead a suit in which you hold four to
the knave or five to the ten is incomprehensible.
 It is not generally known (or if it is, it is never acted on, which
comes to the same thing) that neither in the ninety-one laws of
whist, nor in any of its numerous maxims, are you forbidden to play
the third round of a suit, even though the best card is notoriously
held by your opponent. It is a common delusion to fancy that when
a suit is declared against you, you can prevent it making by leading
something else, whereas you merely postpone the evil day, and do
mischief in the interval. Many feeble whist-players are unwilling ever
to let their opponents make a single trick; now this is unnecessarily
greedy; under no circumstances, at short whist, is it imperative to
make more than eleven. Allow your adversary to have two, it
amuses him and does not hurt you.
“It is less mischievous, generally, to lead a certain
losing card, than to open a fresh suit in which you are
very weak.”—What to Lead, by Cam.

With trumps declared against you be particularly careful how you

open new suits; surely when you have just succeeded in knocking
your partner on the head in one suit, you might give him till the next
hand to recover himself, instead of trying to assault him again the
very next time you get the lead.[9]
Changing suits is one of the most constant annoyances you will
have to contend against; queer temper, grumbling, logic, and so on,
if sometimes a nuisance, are sometimes altogether absent, but the
determination to open new suits for no apparent reason—unless a
feeble desire on the part of the leader to see how far the proceeding
will injure his partner can be called a reason—is chronic.
Never[10] lead a singleton unless you are strong enough in
trumps to defeat any attempt either of your adversaries or your
partner to get them out, in which case it might be as well to lead
them yourself; whether you lead a sneaker or wait for others to play
the suit, the chance of ruffing is much the same, and the certainty of
making a false lead, and the nearly equal certainty of deceiving your
partner are avoided.
 When a singleton comes off it may be nice, it is certainly naughty;
when on the other hand you have killed your partner’s king, and he
has afterwards got the lead, drawn the trumps, and returned your
suit, should the adversaries make four or five suits in it, you must
not be surprised if he gives vent to a few cursory remarks. To
succeed with a singleton, (1) your partner must win the first trick in
the suit, (2) he must return it at once, (3) on your next opening
another unknown suit, he must again win the trick, and the odds
against these combined events coming off are something
considerable. Per contra, he will probably be beaten on the very first
round, and even if he is not, it is extremely likely that he will either
lead trumps—unless he is aware of your idiosyncracy, when he will
never know what to do—for what he naturally imagines is your
strong suit, or open his own; at the same time, just as there are
fagots and fagots, so there are singletons and singletons, and a
queen or knave is by no means such a villainous card as anything
below a seven. “The very worst singleton is the king.”—Cam.
With five trumps and no cards, lead a trump: you have made a
true lead, you have led not merely your strongest suit, but a very
strong suit, and if your partner has nothing, you will lose the game
whatever you play, but you will lose it on that account, and not
because you led a trump; if you open any of the plain suits you will
make a false lead, and it is two to one that the adversaries hold any
of them against your partner. You will often be told by the very
people who will tell you to lead from five small cards in a plain suit,
that to lead a trump from five is too dangerous, but if you inquire in
what way it is too dangerous, and receive any satisfactory reply, you
will succeed in doing what I have never done.
With five trumps and other cards, a fortiori lead a trump.
Towards the end of the game, you will find it laid down by some
authorities that if you hold nothing and have an original lead, you
should lead your best trump; now if that trump is of sufficient size to
warn your partner that it is your best, this lead may not, under the
circumstances, be much more injurious than any other; but an
original trump lead is usually supposed to indicate great strength
either in trumps, or in plain suits, and if your partner infers from the
size of your trump that your lead is from strength, and acting on
that inference returns it, it is about the most murderous lead that
can be made; having been two or three times the victim of such a
lead is almost as good a reason for not returning trumps as sudden
illness or not having one.
If he holds seven tricks in his own hand he can make them at any
time, and any attempt of yours, however able, to deceive him at the
outset will (to say the least of it) not assist him in doing so.
Why add an additional element of confusion to the game? Why
should your partner have to say to himself as well as “Strong cards
or strong trumps?” “Perhaps nothing at all.” He is compelled to wait
about to see what is the meaning of this lead, time is lost, and an
opportunity let slip which may never recur. The Bumblepuppist will
here observe that time was made for slaves; but the apophthegms
on this subject are more numerous and contradictory than he is
aware of.
As a general principle, with the original lead and a very bad hand,
it is advisable to efface yourself as much as possible. In such a case,
I always have a strong desire to get under the table—I don’t know
that it is contrary to either the laws or the etiquette of whist to do so
—and I firmly believe it is a better course than leading the trey of
trumps; at any rate it is not for the weak hand to dictate how the
game should be played; and to step boldly to the front and lead a
small trump from two, without a trick behind it, is in my opinion the
height of impertinence.
At certain states of the score it may be imperative, in order to
save the game, that you should place all the remaining cards, but
that is another matter altogether, and if you want to go into it, read
Clay on the subject (page 85), though he nowhere suggests that you
should commence operations by placing thirty-eight unknown cards.
 If your partner has led you a trump, and you—holding ace,
queen, to four or more—have made the queen, return the ace; if
you are playing Bumblepuppy return a small one, your partner
thinking the ace is against him, is almost certain to finesse and lose
a trick—then call him names. The reason assigned by the perpetrator
of this return is that as he originally held four he is compelled to play
the lowest, and it curiously exemplifies his inability to apply even the
little knowledge he is possessed of.
With ace, king only, it is customary to lead first the ace and then
the king; there is no authority for such a lead,[11] and nothing to be
gained by it, except that by leading in this way you probably prevent
your partner from signalling in the suit, but if you like to burden
yourself with a useless anomaly, you can make a note of it. We
started with the hypothesis, that, in the ordinary course of nature,
you have fifty years before you, and if you wish to embitter and
shorten those years, you will invariably lead the lowest but one of
five—it may be, and I am informed is, useful among a few assorted
players, “chock-full of science,” but it is caviare to the general[12]
and (unlike Wordsworth’s Creature)—
“Too bright and good
For human nature’s daily food.”[13]

For my part I only think it expedient to show five when, with

reasonable strength on the part of my partner, I have a fair prospect
of bringing in the suit.[14]
It is often better to keep the knowledge of mere length of suit
religiously to yourself. Length and strength are not always the same
thing; why are giants generally so weak about the knees? Length is
often only one element of strength and a very poor one at that,
though it may be of use indirectly. With four or five low cards and an
observant opponent, it is occasionally a good plan to bottle up the
smallest. I have known this missing link so to prey upon that
opponent’s mind as to cause him to forget matters of much greater
importance.
 In bumblepuppy all this is entirely different, you can lead anything
you like, in any way you like; here the safest lead is a long weak
suit, the longer and weaker it is, the less is your partner able to do
you a mischief. With a weak partner, strengthening cards are either
futile or dangerous: as he will in all probability at once disembowel
himself, the result of leading them is on all fours with the Japanese
Hari Kari; whereas if you lead him a small card he will finesse into
his boots.
You should also be very particular to lead the lowest but one of
five,[15] it creates confusion, and under cover of that confusion you
may make a trick or two. From this point of view you will often find
the lead of the middle card of your suit extremely effective.
As to play false cards for the purpose of deceiving your partner is
considered clever, a very little practice will enable you to play them
with facility. With all deference to Bret Harte, for ways that are dark,
the Heathen Chinee is not particular, and for tricks that are vain, the
Caucasian can give him points.
“For when he’d got himself a name
For fraud and tricks, he spoil’d his game;
And when he chanced to escape, mistook,
For art and subtlety, his luck.”

The ability to play false cards is not a proof of intelligence. (“Cunning

is often associated with a low type of intellect.”—Report of
Inspector-General of Military Prisons.)[16]
If you read your Natural History, you will find it is the weaker
animals which betake themselves to anomalous modes of defence;
though the cuttle-fish and the skunk may be much looked up to in
their respective domestic circles, they are quite out of place at the
whist-table.
It is also usual with ace to five or more trumps to lead the ace,
and if you see—by killing your partner’s king, or by his failing to play
one—that he has no more, to try something else, for you can change
the suit as often as you please. It is a fine mental exercise for your
partner to recollect the remaining cards of four unfinished suits, all
going simultaneously.
I often think, when I see this game in full blast, that whist-players
are not sufficiently grateful to Charles the Sixth, or whatever other
lunatic invented playing cards, for having limited himself to four
suits; he might have devised six—but the idea is too horrible. “In the
time of Charles the Sixth there were five suits.”—Field. This not only
proves my ignorance but my position, for if five suits have been tried
and found too much for human endurance, then six would
manifestly have been quite too awful! Q.E.D.
Welcome to our website – the ideal destination for book lovers and
knowledge seekers. With a mission to inspire endlessly, we offer a
vast collection of books, ranging from classic literary works to
specialized publications, self-development books, and children's
literature. Each book is a new journey of discovery, expanding
knowledge and enriching the soul of the reade

Our website is not just a platform for buying books, but a bridge
connecting readers to the timeless values of culture and wisdom. With
an elegant, user-friendly interface and an intelligent search system,
we are committed to providing a quick and convenient shopping
experience. Additionally, our special promotions and home delivery
services ensure that you save time and fully enjoy the joy of reading.

Let us accompany you on the journey of exploring knowledge and

personal growth!

textbookfull.com