Name of Program Bachelor of Technology (Computer Science Engineering)

CSET105 Digital Design L T P C

Owning School/Department School of Computer Science Engineering and 3 0 2 4
Technology
Pre-requisites/Exposure -

Course Outcomes (COs)

On completion of this course, the students will be able to:

CO1: Identify appropriate truth table and examine gate level implementation from combinational logic
function.
CO2: Build sequential circuits.
CO3: Experiment with the circuit diagram for combinational and sequential logic using Verilog.

CO-PO/PSO Mapping

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
CO1 1 2 1 3
CO2 1 2 1 1 3
CO3 3 2 2

1=weakly related 2= moderately related 3=strongly related

Course Contents:

Module I: 10 lecture hours

Digital Logic, Analog v/s Digital Systems, Data Representation, Binary Number System, Decimal
Number System, Octal Number System, Hexa-Decimal Number System, Binary Arithmetic,
Unsigned and Signed Numbers, Signed Magnitude, 1’s Complement, 2’s Complement, Fixed- and
Floating-Point Numbers, Weighted Codes, BCD Code, Basic Logic Gates, Universal Logic Gates,
Truth Table

Module II: 10 lecture hours

Laws of Boolean Algebra, Reduction of Boolean Expression using Boolean Laws, Conversion of
Boolean Expression to Logic Diagram, Conversion of Logic Diagram to Boolean Expression, Boolean
Function Representation using SoP and PoS form, Standard Sum of Products, Standard Product of
Sum, Two Variable K-Map, Implicants, Prime Implicants and Essential Prime Implicants, Three
Variable K- Map, Four Variable K-Map, Don’t Care Condition, Design and Analysis of
Combinational Circuits, Half Adder, Full Adder and Carry Propagation, Subtractor, Four Bit Binary
Adder-Subtractor, Excess- 3, Gray Code, Parity, Hamming Code, Binary Multiplier, Magnitude
Comparator, Multiplexer, Implement Boolean Function using Mux, DeMultiplexer, Implement Full
Subtractor using De-Mux.

Module III: 10 lectures hours

4 * 2 Encoder, Octal to Binary Encoder, Priority Encoder, 2*4 Decoder, Implement Full Adder using
Decoder, BCD to 7-segment Display Decoder, Sequential Circuits, Sequential v/s Combinational
Circuits, Clock, SR Latch, D Latch, Edge Trigger and Level Triggered, SR Flip Flop Circuit Diagram,
SR Flip Flop Truth Table, SR Flip Flop Characteristic Table, SR Flip Flop Excitation Table, JK Flip
Flop Circuit Diagram, JK Flip Flop Truth Table, JK Flip Flop Characteristic Table, JK Flip Flop
Excitation Table, Race Around Condition, Master Slave JK Flip Flop, D Flip Flop, T Flip Plop, State
Diagram, State Equation and State Table, Mealy State Machine, Moore State Machine, State
Reduction, State Assignment, ASM Chart, Analysis using JK Flip Flop.
Module IV: 12 lecture hours

Register, Parallel Register, Shift Registers, Bi-Directional Shift Register, Universal Shift Register,
Counter, Asynchronous v/s Synchronous Counter, Ripple Counter (UP, DOWN, UP/DOWN),
Synchronous Counter (UP, DOWN, UP/DOWN), Ring Counter, Johnson’s Counter, Programmable
Logic, Types of PLDs, Architecture of PROM, PLA Architecture, PAL Architecture, System on Chip
Design, Logic Synthesis in Quantum Computing.

Studio Work / Laboratory Experiments:

In this course students will start with basic digital components such as Arithmetic and logical
operation, Memory etc. Then finally design soft IP. The Lab will use Altera Quartus prime Lite tool
for design and FPGA Altera DEII utilize for physical implementation.

Text Books :
1. Mano, M. Morris. Digital Design: with an Introduction to the Verilog HDL, VHDL and System
Verilog. 6th ed. Pearson, 2018. ISBN 978- 0134549897.

Reference Books :
1. Wakerly, John F. Digital Design: Principles and Practices. 5th ed. Prentice Hall, 2008. ISBN
9780134460093.

Assessment Scheme:

Components of Course Evaluation Percentage Distribution

Mid-Term 20%
End Semester Examination 40%

Quiz 5%
Certification 5%
Continuous Lab Evaluation 30%

Total 100%

Note: Certification subjected to Approval

Lecture Wise Plan

Lecture Topics (duration)

1. Digital Logic (20), Analog v/s Digital Systems (15), Simple Numerical
Examples on Analog v/s Digital Systems (10)
2. Data Representation (20), Binary Number System (20), Simple Conversions
and Numerical Exercises (5)
3. Decimal Number System (15), Octal Number System (15), Hexa-Decimal
Number System (10), Conversion Exercises (5)
4. Binary Arithmetic (20), Unsigned and Signed Numbers (15), Numerical
Exercises on Arithmetic Operations (10)
5. Signed Magnitude (10), 1’s Complement (15), Numerical Exercises on 1’s
Complement (20)
6. 2’s Complement (20), Numerical Exercises on 2’s Complement (25)

7. Fixed- and Floating-Point Numbers (25), Numerical Exercises on Fixed- and

Floating-Point Representations (20)
8. Weighted Codes (15), BCD Code (15), Numerical Exercises on Weighted and
BCD Codes (15)
9. Basic Logic Gates (20), Universal Logic Gates (15), Truth Table Construction
and Exercises (10)
10. Complex Numerical Exercises on Binary Arithmetic, Signed Numbers, and
Complements (45)
11. Advanced Numerical Exercises (45)

12. Buffer Lecture 1

13. Revision Lecture 1 and Class Assessment 1

14. Laws of Boolean Algebra (20), Reduction of Boolean Expression using Boolean
Laws (25)

15. Conversion of Boolean Expression to Logic Diagram (20), Conversion of Logic

Diagram to Boolean Expression (25)

16. Boolean Function Representation using SoP and PoS form (20), Standard Sum of
Products (15), Standard Product of Sum (10)

17. Two Variable K-Map (20), Implicants, Prime Implicants, and Essential Prime
Implicants (25)

18. Three Variable K-Map (20), Four Variable K-Map (15), Don’t Care Condition (10)

19. Design and Analysis of Combinational Circuits (20), Numerical Exercises on K-

Maps (25)

20. Half Adder, Full Adder, and Carry Propagation (20), Subtractor (15), Numerical
Exercises on Adders and Subtractors (10)
21. Four Bit Binary Adder-Subtractor (15), Excess-3 (15), Gray Code (15)

22. Parity (15), Hamming Code (15), Binary Multiplier (15)

23. Magnitude Comparator (15), Multiplexer (15), Numerical Exercises on Multiplexers

(15)

24. DeMultiplexer (15), Implement Full Subtractor using De-Mux (15), Numerical
Exercises on De-Mux (15)

25. Buffer Lecture 2

26. Revision Lecture 2 and Class Assessment 2

27. 4 * 2 Encoder (15), Octal to Binary Encoder (15), Priority Encoder (15)

28. 2*4 Decoder (20), Implement Full Adder using Decoder (15), BCD to 7-segment
Display Decoder (10)

29. Sequential Circuits (20), Sequential v/s Combinational Circuits (25)

30. Clock (10), SR Latch (15), D Latch (20)

31. Edge Trigger and Level Triggered (15), SR Flip Flop Circuit Diagram (15), SR Flip
Flop Truth Table (15)

32. SR Flip Flop Characteristic Table (15), SR Flip Flop Excitation Table (15), JK Flip
Flop Circuit Diagram (15)

33. JK Flip Flop Truth Table (15), JK Flip Flop Characteristic Table (15), JK Flip Flop
Excitation Table (15)

34. Race Around Condition (15), Master Slave JK Flip Flop (15), D Flip Flop (15)

35. T Flip Flop (15), State Diagram (15), State Equation and State Table (15)

36. Mealy State Machine (15), Moore State Machine (10), State Reduction (10), State
Assignment (10)

37. Buffer Lecture 3

38. Revision Lecture 3 and Class Assessment 3

39. Register (20), Parallel Register (25)

40. Shift Registers (20), Bi-Directional Shift Register (25)

41. Universal Shift Register (20), Numerical Exercises on Shift Registers

42. Counter (20), Asynchronous v/s Synchronous Counter (25)

43. Ripple Counter (UP, DOWN, UP/DOWN) (20), Numerical Exercises on

Ripple Counter (25)
44. Synchronous Counter (UP, DOWN, UP/DOWN) (20), Numerical Exercises
on Synchronous Counter (25)
45. Ring Counter (20), Johnson’s Counter (20), Numerical Exercises on Counters
(5)
46. Programmable Logic (20), Types of PLDs (15), Numerical Exercises on
Programmable Logic (10)
47. Architecture of PROM (15), PLA Architecture (15), PAL Architecture (15)

48. System on Chip Design (20), Logic Synthesis in Quantum Computing (25)

49. Advanced Numerical Exercises on Counters and Registers (45)

50. Buffer Lecture 4

51. Revision Lecture 4 and Class Assessment 4