Microprocessor Architecture

Dr. Amin Danial

 References
❑ Triebel, Walter - 8088 and 8086 Microprocessors
Programming, Interfacing, Software, Hardware,
and Applications - (2013)
❑ Brey, Barry B - The Intel microprocessors with 64-
bit extensions architecture (8th ed-2009)
❑ S. K Sen - Understanding 8085 8086 Microprocessor
and Peripheral ICs (2009)
❑ A. Nagoor Kani - 8086 Microprocessors and its
Applications-Mc Graw Hill India (2013)
❑ Das, Lyla B - The X86 Microprocessors Architecture
and Programming 8086 to Pentium (2010)
 Microprocessor Architecture
MICROARCHITECTURE

• The microarchitecture of a processor is its internal

architecture, that is, the circuit building blocks that
implement the software and hardware architectures of
the 8088/8086 microprocessors.
• Due to the need for additional features and higher
performance, the microarchitecture of a microprocessor
family evolves over time. In fact, a new
microarchitecture is introduced for Intel’s 8086 family
every few years.
 Microprocessor Architecture
MICROARCHITECTURE
• The microarchitectures of the 8088 and 8086
microprocessors are similar. They both employ parallel
processing, that is, they are implemented with several
simultaneously operating processing units.
• The internal architecture of the 8088 and 8086
microprocessors contains two processing units:
– bus interface unit (BIU)
– execution unit (EU).
• Each unit has dedicated functions and both operate at the
same time. In essence, this parallel processing effectively
makes the fetch and execution of instructions independent
operations.
• This results in efficient use of the system bus and higher
performance for 8088/8086 microcomputer systems.
Microprocessor Architecture
MICROARCHITECTURE
 Microprocessor
Architecture
MICROARCHITECTURE
8086
 Microprocessor Architecture
MICROARCHITECTURE - BIU
• To implement these functions, the BIU contains the segment
registers, the instruction pointer, the address generation adder, bus
control logic, and an instruction queue.
• The BIU uses a mechanism known as an instruction queue to
implement a pipelined architecture.
• This queue permits the 8088 to prefetch up to 4 bytes (6 bytes for
the 8086) of instruction code. Whenever the queue is not full—that
is, it has room for at least 2 more bytes, and, at the same time, the
execution unit is not asking it to read or write data from memory,
the BIU is free to look ahead in the program by prefetching the
next sequential instructions. Prefetched instructions are held in the
first-in first-out (FIFO) queue.
• Whenever a byte is loaded at the input end of the queue, it is
automatically shifted up through the FIFO to the empty location
nearest the output.
 Microprocessor Architecture
MICROARCHITECTURE - BIU
• The bus interface unit is the 8088/8086’s connection to the outside
world.
• By interface, we mean the path by which it connects to external
devices.
• The BIU is responsible for performing all external bus operations, such
as instruction fetching, reading and writing of data operands for
memory, and inputting or outputting data for input /output peripherals.
• These information transfers take place over the system bus. This bus
includes an 8-bit bidirectional data bus for the 8088 (16 bits for the
8086), a 20-bit address bus, and the signals needed to control transfers
over the bus.
• The BIU is not only responsible for performing bus operations, it also
performs other functions related to instruction and data acquisition. For
instance, it is responsible for instruction queuing and address
generation.
 Microprocessor Architecture
MICROARCHITECTURE - BIU
• Since instructions are normally waiting in the
queue, the time needed to fetch many
instructions of the microcomputer’s program is
eliminated.
• If the queue is full and the EU is not requesting
access to data in memory, the BIU does not
need to perform any bus operations.
• These intervals of no bus activity, which occur
between bus operations, are known as idle
states.
 Microprocessor Architecture
MICROARCHITECTURE - EU
• The execution unit is responsible for decoding and executing
instructions.
• It consists of the arithmetic logic unit (ALU), status and control flags,
general- purpose registers, and temporary-operand registers.
• The EU accesses instructions from the output end of the instruction
queue and data from the general-purpose registers or memory.
• It reads one instruction byte after the other from the output of the
queue, decodes them, generates data addresses if necessary, passes
them to the BIU and requests it to perform the read or write operations
to memory or I/O, and performs the operation specified by the
instruction.
• The ALU performs the arithmetic, logic, and shift operations required by
an instruction.
• During execution of the instruction, the EU may test the status and
control flags, and updates these flags based on the results of executing
the instruction.
• If the queue is empty, the EU waits for the next instruction byte to be
fetched and shifted to the top of the queue.
 Microprocessor Architecture
SOFTWARE MODEL
• The purpose of developing a software model is to aid the
programmer in understanding the operation of the microcomputer
system from a software point of view. To be able to program a
microprocessor, one does not need to know all of its hardware
architectural features.
• What is important to the programmer is to know the various
registers within the device and to understand their purpose,
functions, operating capabilities, and limitations.
• Furthermore, it is essential that the programmer knows how
external memory and input/output peripherals are organized, how
information is arranged in registers, memory, and input/output,
and how memory and I/O are addressed to obtain instructions and
data.
Microprocessor Architecture
SOFTWARE MODEL
 Microprocessor Architecture
SOFTWARE MODEL

• The software architecture of the 8088/8086 microprocessor is as

follows:
• 8 general purpose registers
o AX - the accumulator register (divided into AH / AL).
o BX - the base address register (divided into BH / BL).
o CX - the count register (divided into CH / CL).
o DX - the data register (divided into DH / DL).
o SI - source index register.
o DI - destination index register.
o BP - base pointer.
o SP - stack pointer.
 Microprocessor Architecture
SOFTWARE MODEL
• Segment registers
– CS - points at the segment containing the current
program.
– DS - generally points at segment where variables are
defined.
– ES - extra segment register, it's up to a coder to define its
usage.
– SS - points at the segment containing the stack.

• Special purpose registers

– IP - the instruction pointer.
– Status Register (flags register) - determines the current
state of the microprocessor.
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION
• The 8088/8086 microcomputer supports 1Mbyte (220 𝑏𝑦𝑡𝑒𝑠) of external memory. This
memory space is organized from a software point of view as individual bytes of data
stored at consecutive addresses over the address range 00000h (𝟎𝟎𝟎𝟎𝟎𝟏𝟔 ) to FFFFFh
(𝑭𝑭𝑭𝑭𝑭𝟏𝟔 ).
• Therefore, memory in an 8088/8086- based microcomputer is actually organized as 8-bit
bytes, not as 16-bit words
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION
• The 8088/8086 can access any two consecutive bytes as a word of data.
In this case, the lower-addressed byte is the least significant byte of the
word, and the higher-addressed byte is its most significant byte (called
Little endian).

• Notice that the storage location at the lower address, 00724h, contains
the value 00000010b = 02h.
• The contents of the next-higher-addressed storage location, 00725h, are
01010101b =55h.
• These two bytes represent the word 0101010100000010h =5502h.
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION

Little endian: the least significant

byte is always stored in the lowest-
numbered memory location, and the
most significant byte is stored in the
1234H highest
Big endian: the most significant
byte is always stored in the lowest-
numbered memory location, and the
least significant byte is stored in the
highest
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION

• To permit efficient use of memory, words of data can be stored at

what are called even- or odd-addressed word boundaries.
• The least significant bit of the address determines the type of word
boundary. If this bit is 0, the word is at an even-address boundary,
that is, a word at an even-address boundary corresponds to two
consecutive bytes, with the least significant byte located at an even
address.
• For example, the follow word in has its least significant byte at
address 00724h. Therefore, it is stored at an even-address
boundary.
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION
• A word of data stored at an even-address boundary, such as 00000h, 00002h, 00004h, and
so on, is said to be an aligned word, that is, all aligned words are located at an address
that is a multiple of 2.
• On the other hand, a word of data stored at an odd-address boundary, such as 00001h,
00003h, or 00005h and so on, is called a misaligned word. Figure 5 shows some aligned
and misaligned words of data.

• Words 0, 2, 4, and 6 are examples of aligned-

data words,
• While words 1 and 5 are misaligned words.
• Notice that misaligned word 1 consists of byte
1 from aligned word 0 and byte 2 from aligned
word 2.
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION
Ex1: What is the data word shown in the following Figure? Express
the result in hexadecimal form. Is it stored at an even- or odd-
addressed word boundary? Is it an aligned or misaligned word of
data?
Solution:
The most significant byte of the word is stored at
address 0072Ch and equals:
11111101𝑏 = 𝐹𝐷ℎ
Its least significant byte is stored at address 0072Bh and is:
10101010𝑏 = 𝐴𝐴ℎ
Together the two bytes give the word:
11111101 10101010𝑏 = 𝐹𝐷𝐴𝐴ℎ
The address of the least significant byte is 0072𝐵ℎ =
0000 0000 0111 0010 1011𝑏, which odd-address bound and hence
it is a misaligned word of data
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION
• A double word corresponds to four
consecutive bytes of data stored in
memory; an example of double-
word data is a pointer. A pointer is
a two-word address element that is
used to access data or code in
memory.
• A pointer is a two-word address
element that is used to access data
or code in memory. The word of
this pointer that is stored at the
higher address is called the
segment base address, and the
word at the lower address is called
the offset.
• A double word is aligned if located at an address that is multiple of 4 (e.g. 00000h,
00004h, 00008h). Therefore, only double words 0 and 4 are aligned, whereas double
words 1,2,3, and 5) are misaligned.
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION

• The word of this pointer that is stored at the higher address is

called the segment base address, and the word at the lower address
is called the offset.

• The segment base address, which equals 0011101101001100b=3B4Ch.

• The offset part of the pointer is 0000000001100101b = 0065h
• The complete double word is 3B4C0065h.
 Microprocessor Architecture
SOFTWARE MODEL-MEMORY ADDRESS SPACE AND DATA ORGANIZATION

Ex2: How should the pointer with segment base address equal to A000h and offset
address 55FFh be stored at an even-address boundary starting at 00008h? Is the
double word aligned or misaligned?
Solution
• Storage of the two-word pointer requires four
consecutive byte locations in memory, starting at
address 00008h.
• The least-significant byte of the offset is stored
at address 00008h and is shown as FFh.
• The most significant byte of the offset, 55h, is
stored at address 00009h.
• The least significant byte of the segment
base address, 00h, at address 0000Ah
• The most significant byte of the segment
base, A0h, at address 0000Bh.
• Since the double word is stored in memory
starting at address 00008h, it is aligned
 Microprocessor Architecture
SOFTWARE-Data Types-Byte

• 8088/8068 can directly process 5 types of

data types, which are as follows:
1. Unsigned integer
2. Signed integer
3. Unpacked BCD
4. Packed BCD
5. ASCII
 Microprocessor Architecture
SOFTWARE-Data Types-Byte
• Byte-sized data are stored as unsigned and signed integers.

0 to 255

0 to 127
-128 to -1
Sign bit

• In the signed integer format, the leftmost bit represents the sign bit
of the number, as well as a weight of minus 128.
• For example, 80H represents a value of 128 as an unsigned
number; as a signed number, it represents a value of minus 128.
 Microprocessor Architecture
SOFTWARE-Data Types-Word

Unsigned Word 0 to 65535

Signed Word 0 to 32767 , -32768 to -1

With weight of -32768

 Microprocessor Architecture
SOFTWARE-Data Types-BCD
• The 8088/8086 can also process data that is coded as binary-coded
decimal (BCD) numbers.
• BCD data can be stored in either unpacked or packed form. For
instance, the unpacked BCD byte is a single BCD digit stored in the
four least significant bits, and the upper four bits are set to 0.
• A byte with packed BCD digits are two BCD numbers are stored in a
byte. The upper four bits represent the most significant digit of a two-
digit BCD number.

Packed BCD Unpacked BCD

 Microprocessor Architecture
SOFTWARE-Data Types

• Ex3: What value does the unsigned word integer 1000h

represent?
• Solution:
– First, the hexadecimal integer is converted to binary
form:
1000ℎ = 0001 0000 0000 0000𝑏
– Next, we find the value for the binary number:
0001 0000 0000 0000𝑏 = 212 = 4096
 Microprocessor Architecture
SOFTWARE-Data Types

Ex4: A signed word integer equals FEFFh . What

decimal number does it represent?
Solution
– Expressing the hexadecimal number in binary form gives:
𝐹𝐸𝐹𝐹ℎ = 1111 1110 1111 1111𝑏
– Since the most significant bit is 1, the number is negative
and is in 2′s complement form. Converting to its binary
equivalent by subtracting 1 from the least significant bit
and then complementing all bits gives:
𝐹𝐸𝐹𝐹ℎ = −0000 0001 0000 0001𝑏 = −257
 Microprocessor Architecture
SOFTWARE-Data Types
Ex5: The packed BCD data stored at byte address 01000h equal
10010001b. What is the two-digit decimal number?

Solution:
– Writing the value 10010001b as separate BCD digits
gives:
10010001𝑏 = 1001𝐵𝐶𝐷 0001𝐵𝐶𝐷 = 91
Microprocessor Architecture
SOFTWARE-Data Types

Information expressed in ASCII (American

Standard Code for Information
Interchange) can also be directly processed
by the 8088/8086 microprocessor.

𝐴𝑆𝐶𝐼𝐼 𝐶𝑜𝑑𝑒 = 𝐻1 𝐻0
𝐷7 𝐻1 𝐻0
EX6:
Thanks