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S Y S T E M AT I C D E S I G N O F A N A L O G C M O S C I R C U I T S

Using Pre-Computed Lookup Tables

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in
nanoscale-CMOS with this hands-on guide.

Expert authors present a sizing methodology that employs SPICE-generated lookup

tables, enabling close agreement between hand analysis and simulation.

Illustrates the exploration of analog circuit tradeoffs using the gm/ID ratio as a central
variable in script-based design flows, captured in downloadable Matlab code.

Includes over forty detailed worked examples, including the design of low-noise and
low-distortion gain stages, and operational transconductance amplifiers.

Whether you are a professional analog circuit designer, a researcher, or a graduate student,
this book will provide you with the theoretical know-how and practical tools you need to
acquire a systematic and re-use oriented design style for analog integrated circuits in modern
CMOS.

Paul G. A. Jespers is a Professor Emeritus of the Université Catholique de Louvain and a

Life Fellow of the IEEE.

Boris Murmann is a Professor of Electrical Engineering at Stanford University, and a Fellow

of the IEEE.

2
“Analog design generates insight, but requires expertise. To build up such expertise, analytic
models are used to create design procedures. Indeed, analytic models easily allow device sizing
from specifications. They lack accuracy, however. The models of present-day nanometer
MOS transistors have become rather complicated. On the other hand SPICE simulations do
provide the required accuracy but don’t generate as much insight. The use of SPICE-
generated lookup tables, as described in this book, provides an excellent compromise. The
accuracy is derived from SPICE and the design procedure itself is made through MATLAB
employing parameters like gm/ID. As a result a considerable amount of intuition can be built
up. Such design procedure is highly recommended to whoever wants to gain insight by doing
analog design, without losing the accuracy of real SPICE simulations.”

Willy Sansen, KU Leuven

“With the advent of sub-micron MOS transistors more than two decades ago, traditional
design based on the square-law model is no longer adequate. Alternatives such as ‘tweaking’
with SPICE or relying on more sophisticated device models do not provide the circuit insight
necessary for optimized design or are too mathematically complex.
The design methodology presented in this book overcomes these shortcomings. A focus
on fundamental design parameters – dynamic range, bandwidth, power dissipation – naturally
leads to optimized solutions, while relying on transistor data extracted with the simulator
ensures agreement between design and verification. Comprehensive design examples of
common blocks such as OTAs show how to readily apply these concepts in practice.
This book fixes what has been broken with analog design for more than twenty years. I
recommend it to experts and novices alike.”

Bernhard Boser, University of California, Berkeley

“The authors present a clever solution to capture the precision of the best MOSFET models,
current or future, in a comprehensive and efficient design flow compatible with nanometric
CMOS processes. In this book, you will also enjoy a wealth of invaluable information to
deepen your analog design skills.”

Yves Leduc, Polytech Nice Sophia

3
 SYSTEMATIC DESIGN OF
ANALOG CMOS CIRCUITS
Using Pre-Computed Lookup Tables
Paul G. A. Jespers
Université Catholique de Louvain, Belgium

Boris Murmann
Stanford University

4
 University Printing House, Cambridge CB2 8BS, United Kingdom

One Liberty Plaza, 20th Floor, New York, NY 10006, USA

477 Williamstown Road, Port Melbourne, VIC 3207, Australia

4843/24, 2nd Floor, Ansari Road, Daryaganj, Delhi – 110002, India

79 Anson Road, #06-04/06, Singapore 079906

Cambridge University Press is part of the University of Cambridge.

It furthers the University’s mission by disseminating knowledge in the pursuit of education, learning, and research
at the highest international levels of excellence.

www.cambridge.org

Information on this title: www.cambridge.org/9781107192256

DOI: 10.1017/9781108125840

© Cambridge University Press 2017

This publication is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing
agreements, no reproduction of any part may take place without the written permission of Cambridge University Press.

First published 2017

Printed in the United Kingdom by Clays, St Ives plc

A catalogue record for this publication is available from the British Library.

ISBN 978-1-107-19225-6 Hardback

Additional resources for this title are available at www.cambridge.org/Jespers

Cambridge University Press has no responsibility for the persistence or accuracy of URLs for external or third-party
internet websites referred to in this publication and does not guarantee that any content on such websites is, or will
remain, accurate or appropriate.

5
To my granddaughter Zérane

PGAJ

To my wife Yukiko

BM

6
 Contents
Symbols and Acronyms

1 Introduction
1.1 Motivation
1.2 The Analog Circuit Sizing Problem and the Proposed Approach
1.2.1 Square-Law Perspective
1.2.2 Capturing the Tradeoffs Using Lookup Tables
1.2.3 Generalization
1.2.4 VGS-agnostic design
1.2.5 Design in Weak Inversion
1.3 Content Overview
1.4 Prerequisites
1.5 Notation
1.6 References

2 Basic Transistor Modeling

2.1 The Charge Sheet Model (CSM)
2.1.1 The CSM Drain Current Equation
Example 2.1 Surface Potential Calculation
2.1.2 The Dependence of the Drain Current on the Drain Voltage
2.1.3 The Transconductance Efficiency gm/ID
2.2 The Basic EKV Model
2.2.1 The Basic EKV Equations
2.2.2 The Basic EKV Model for a Grounded-Source MOS Transistor
2.2.3 Strong and Weak Inversion Approximations of the EKV Model
2.2.4 Basic EKV Model Expressions for gm and gm/ID
2.2.5 EKV Parameter Extraction
Example 2.2 EKV Parameter Extraction for the CSM Device
2.3 Real Transistors
2.3.1 Real Drain Current Characteristics ID(VGS) and gm/ID
Example 2.3 EKV Parameter Extraction for Real Transistors
2.3.2 The Drain Saturation Voltage VDsat of Real Transistors
2.3.3 Impact of Bias Conditions on EKV Parameters

7
 2.3.4 The Drain Current Characteristic ID(VDS)
2.3.5 The Output Conductance gds
2.3.6 The gds/ID Ratio
2.3.7 The Intrinsic Gain
2.3.8 MOSFET Capacitances and the Transit Frequency fT
2.4 Summary
2.5 References

3 Basic Sizing Using the gm/ID Methodology

3.1 Sizing an Intrinsic Gain Stage (IGS)
3.1.1 Circuit Analysis
3.1.2 Sizing Considerations
3.1.3 Sizing for Given L and gm/ID
Example 3.1 A Basic Sizing Example
3.1.4 Basic Tradeoff Exploration
Example 3.2 Sizing at Constant gm/ID
Example 3.3 Sizing at Constant fT
Example 3.4 Sizing at Constant |Av0|
3.1.5 Sizing in Weak Inversion
Example 3.5 Sizing in Weak Inversion Given a Width Constraint
3.1.6 Sizing Using the Drain Current Density
Example 3.6 Sizing Using Contours in the JD and L Plane
3.1.7 Inclusion of Extrinsic Capacitances
Example 3.7 Iterative Sizing to Account for Self-Loading
3.2 Practical Common-Source Stages
3.2.1 Active Load
Example 3.8 Sizing a CS Stage with Active Load
Example 3.9 Large-Signal Characteristic of a CS Stage with Active Load
3.2.2 Resistive Load
Example 3.10 Sizing a CS Stage with Resistive Load
3.3 Differential Amplifier Stages
Example 3.11 Sizing a Differential Pair with Ideal Current Source Loads
Example 3.12 Sizing a Differential Amplifier with Current-Mirror Load
Example 3.13 Sizing a Differential Amplifier with Resistive Input Driver and
Resistive Loads
3.4 Summary
3.5 References

8
4 Noise, Distortion and Mismatch
4.1 Electronic Noise
4.1.1 Thermal Noise Modeling
4.1.2 Tradeoff between Thermal Noise, GBW and Supply Current
Example 4.1 Sizing of a Low-Noise IGS
4.1.3 Thermal Noise from Active Loads
Example 4.2 Choosing gm/ID of a p-Channel Load for Maximum Dynamic
Range
4.1.4 Flicker Noise (1/f Noise)
Example 4.3 Estimation of the Flicker Noise Corner Frequency
4.2 Nonlinear Distortion
4.2.1 Nonlinearity of the MOS Transconductance
4.2.2 Nonlinearity of the MOS Differential Pair
Example 4.4 Sizing a Differential Amplifier Based on Distortion Specs
4.2.3 Inclusion of the Output Conductance
Example 4.5 Sizing of a Resistively Loaded CS Stage with Low HD2
Example 4.6 Sizing of a Resistively Loaded CS Stage with Low HD2 and VDD
= 1.2 V
4.3 Random Mismatch
4.3.1 Modeling of Random Mismatch
4.3.2 Effect of Mismatch in a Current Mirror
Example 4.7 Random Mismatch Estimation in a Current Mirror
4.3.3 Effect of Mismatch in a Differential Amplifier
Example 4.8 Offset Drift Estimation
4.4 Summary
4.5 References

5 Practical Circuit Examples I

5.1 Constant Transconductance Bias Circuit
Example 5.1 Sizing of a Constant Transconductance Bias Circuit
5.2 High-Swing Cascoded Current Mirror
5.2.1 Sizing the Current Mirror Devices
5.2.2 Sizing the Cascode Bias Circuit
5.3 Low-Dropout Voltage Regulator
5.3.1 Low-Frequency Analysis
Example 5.2 Basic Sizing of an LDO
5.3.2 High-Frequency Analysis

9
 Example 5.3 Sizing the LDO’s Load Capacitance
5.4 RF Low-Noise Amplifier
5.4.1 Sizing for Low-Noise Figure
Example 5.4 Sizing the LNA for a Given Noise Figure
5.4.2 Sizing for Low-Noise Figure and Low Distortion
Example 5.5 Sizing the LNA for Minimum HD2
5.5 Charge Amplifier
5.5.1 Circuit Analysis
5.5.2 Optimization Assuming Constant Transit Frequency
5.5.3 Optimization Assuming Constant Drain Current
Example 5.6 Charge Amplifier Optimization (Constant ID)
5.5.4 Optimization Assuming Constant Noise and Bandwidth
Example 5.7 Charge Amplifier Optimization (Constant Noise and Bandwidth)
Example 5.8 Charge Amplifier Sizing
Example 5.9 Charge Amplifier Re-sizing for Smaller Area
5.6 Designing for Process Corners
5.6.1 Biasing Considerations
5.6.2 Technology Evaluation over Process and Temperature
Example 5.10 Constant Transconductance Bias Circuit Performance across
Process Corners
5.6.3 Possible Design Flows
Example 5.11 Design of a Charge Amplifier with Corner Awareness
5.7 Summary
5.8 References

6 Practical Circuit Examples II

6.1 Basic OTA for Switched-Capacitor Circuits
6.1.1 Small-Signal Circuit Analysis
6.1.2 Optimization Assuming Constant Noise and Bandwidth
Example 6.1 Optimization of the Basic OTA
Example 6.2 Sizing of the Basic OTA
6.1.3 Optimization in Presence of Slewing
Example 6.3 Sizing of the Basic OTA Circuit in Presence of Slewing
6.2 Folded-Cascode OTA for Switched-Capacitor Circuits
6.2.1 Design Equations
6.2.2 Optimization Procedure
Example 6.4 Sizing of the Folded-Cascode Output Branch

10
 Example 6.5 Optimization of the Folded-Cascode OTA
Example 6.6 Sizing the Folded-Cascode OTA
6.2.3 Optimization in Presence of Slewing
6.3 Two-Stage OTA for Switched-Capacitor Circuits
6.3.1 Design Equations
6.3.2 Optimization Procedure
Example 6.7 Optimization of the Two-Stage OTA
Example 6.8 Sizing the Two-Stage OTA
6.3.3 Optimization in Presence of Slewing
6.4 Simplified Design Flows
6.4.1 Folded-Cascode OTA
6.4.2 Two-Stage OTA
6.5 Sizing Switches
Example 6.9 Sizing a Transmission Gate Switch
6.6 Summary
6.7 References

Appendix 1 The EKV Parameter Extraction Algorithm

A.1.1 Review of Equations
A.1.2 Parameter Extraction Algorithm
A.1.3 Matlab Function XTRACT.m
A.1.4 Parameter Extraction Example
A.1.5 Matlab Function XTRACT2.m
A.1.6 Corner Parameter Extraction
A.1.7 Conclusion
A.1.8 References
Appendix 2 Lookup Table Generation and Usage
A.2.1 Lookup Table Generation
A.2.1.1 Configuration File
A.2.1.2 Generating Lookup Tables for a New Technology
A.2.2 Matlab Function lookup.m
A.2.3 Matlab Function lookupVGS.m
A.2.4 Lookup of Ratios with Non-monotonic Vectors
A.2.5 LookupVGS with Non-monotonic gm/ID Vector
A.2.6 Passing Design Variables to the Simulator
A.2.7 References
Appendix 3 Layout Dependence

11
 A.3.1 Introduction to Layout Dependent Effects (LDE)
A.3.2 Transistor Finger Partitioning
A.3.3 Width Dependence of Parameter Ratios
A.3.4 References
Index

12
 Symbols and Acronyms

Av
Small-signal voltage gain

Av0
Low frequency small-signal voltage gain

Aintr
Intrinsic gain

AVT
Pelgrom coefficient for threshold voltage mismatch

Aβ
Pelgrom coefficient for current factor mismatch

ACM
Advanced Compact Model

CLM
Channel Length Modulation

CSM
Charge Sheet Model

C
Capacitor value

Cox
Oxide capacitance per unit area

13
Cgb
Gate-to-bulk capacitance

Cgd
Gate-to-drain capacitance

Cgs
Gate-to-source capacitance

Cj
Junction capacitance

CC
Compensation capacitance

CMOS
Complementary Metal Oxide Semiconductor

Cself
Self-loading capacitance of an amplifier

D
Diffusion constant

DIBL
Drain-Induced Barrier Lowering

EKV
Enz, Krumenacher and Vittoz compact model

FO
Fan-out (ratio between load and input capacitances of a circuit)

f
Frequency in Hz

fc
Cutoff frequency (−3dB frequency)

fT

14
Transit frequency

fu
Unity gain frequency (where |Av| = 1)

gds
Output conductance

gm
Gate transconductance

gmk
kth derivative of ID with respect to VGS

gmb
Bulk transconductance

gms
Source transconductance

HD2, HD3
Fractional harmonic distortion of order 2, 3, …

i
Normalized drain current

IGS
Intrinsic Gain Stage

ID
DC drain current

IS
Specific current

ISsq
Square specific current (W = L)

ISu
Unary specific current (W = 1 μm)

15
JD
Drain current density (ID/W)

L
Gate length

N
Impurity concentration

n
Subthreshold slope factor

q
Normalized mobile charge density

qS, qD
Normalized mobile charge density at the source and drain

Qi
Mobile charge density

RHP
Right Half Plane

SVT0
Threshold voltage sensitivity factor with respect to VDS

SIS
Specific current sensitivity factor with respect to VDS

UT
Thermal voltage kT/q

VX
DC voltage component at node x

vx
AC voltage component at node x

vX

16
Total voltage at node x, vX = VX + vx

VEA
Early voltage

VI
DC component of input voltage

vi
AC component of input voltage

vI
Total input voltage vI = VI + vi

vid
Differential input voltage, AC component

VS, VG, VD
Source, gate and drain voltage with respect to bulk (DC)

VGS, VDS
Gate and drain voltage with respect to the source (DC)

vgs, vds
Incremental gate and drain voltage with respect to the source

vgs,pk, vds,pk
Incremental gate and drain voltage amplitude (sinusoid)

VP
Pinch-off voltage with respect to the bulk

VDsat
Drain saturation voltage

vsat
Saturation velocity of mobile carriers

VT
Threshold voltage

17
VOV
Gate overdrive voltage, VGS – VT

W
Transistor width

WI, MI, SI
Weak, moderate and strong-inversion

β
Current factor1 (μCoxW/L)

γ
Backgate effect parameter

γn, γp
Thermal noise factor for n-channel and p-channel devices2

μ
Mobility

μo
Low-field mobility

ρ
Normalized transconductance efficiency

ψS
Surface potential

ω
Angular frequency (2πf)

ωc
Angular cutoff frequency (2πfc)

ωT
Angular transit frequency (2πfT)

ωTi

18
Angular transit frequency considering only Cgs (instead of Cgg)

1 The symbol β is also used to denote the feedback factor in amplifier circuits. The
distinction is usually clear from the context.

2 The distinction from the backgate effect parameter γ is usually clear from the context.

19
 1
Introduction
◈

20
 1.1 Motivation
Since the 1960s, the square-law model for complementary metal-oxide-semiconductor
(CMOS) transistors has been used extensively to analyze and design analog and digital
integrated circuits. An advantage of the square-law equations is that they are easy to derive
from basic solid-state physics, algebraically simple and yet useful for gaining insight into basic
CMOS circuit behavior. As a result, the square-law model remains useful as a “warm-up
tool” for students in circuit design, and it is featured in all popular analog integrated circuit
textbooks (examples include [1], [2]).
On the other hand, it is well known that the square-law MOS model is plagued by
several limitations, especially when it comes to short-channel transistors:

Modern MOSFETs are impaired by numerous mobility degradation effects, related

to their short channel length, thin gate oxide and their generally more complex
structure and doping profiles. In strong inversion, with gate overdrive voltages (VGS –
VT) of several hundred millivolts, the error in the transconductance predicted by
square-law models with constant parameters is of the order of 20–60%.

In moderate inversion, with gate overdrive voltages below 150 mV, the square-law
model breaks down altogether and it may be in error by a factor of two or even more.
This deficiency applies to all MOSFETs, regardless of channel length. However, the
issue has become more pronounced with short channel devices, since moderate
inversion represents a design “sweet spot” for a variety of circuits in these technologies
[3]–[5].

In weak inversion (subthreshold operation), the current flows by diffusion (like in a

BJT) and the square-law model must be replaced with an exponential I–V
relationship.

The above-stated issues are clearly visible in Figure 1.1, which shows the current density plot
of a realistic 65-nm transistor, together with exponential and square-law approximations. The
exponential provides a reasonably good fit for very low VGS (weak inversion) and the
quadratic approximation begins to make sense a few hundred millivolts above the device’s
threshold voltage (vertical dashed line). The transition from weak to strong inversion should
ideally be smooth and continuous, but finding a physical relationship that bridges the
exponential and square-law approximations turns out to be non-trivial. In addition, at very

21
large VGS, the current density of the real device and the quadratic model diverge again due to
the mentioned mobility degradation effects.

Figure 1.1 Current density of a minimum-length n-channel device in 65-nm CMOS

technology versus VGS. The dotted vertical line corresponds to the device’s threshold
voltage (see Chapter 2 for further details).

The above-stated modeling limitations are a great nuisance when it comes to design,
since the square-law hand calculations described in textbooks typically won’t match
simulations for a classical flow (see Figure 1.2). Modern circuit simulation relies on complex
device models such as BSIM6 [6] or PSP1 [7], which are carefully crafted to reflect the “real”
device characteristic in Figure 1.1. The result is a significant disconnect between hand
analysis and simulation results, and consequently, designers tend to shy away from hand-
calculations and resort to a design style built on iterative and time-consuming SPICE-based
“tweaking.”

Figure 1.2 Typical analog circuit design flow based on square-law hand calculations
SPICE simulation using advanced models.

22
 There are several issues with the iterative simulation-based design of analog circuits. The
problem is that the designer loses insight about the tradeoffs as well as the ability to sanity-
check the results. While an equation-based design can reveal fundamental issues with a
topology and help the designer advance his or her circuit architecture, it is difficult to gain
knowledge about the fundamental limits of a circuit via repetitive sizing and simulation.
What used to be design now resembles reverse engineering, which is highly undesirable for
anyone who is interested in leading-edge innovation.
The second issue is that highly iterative design based on SPICE “tweaking” is typically
incompatible with the time-to-market pressure seen in today’s IC developments. As a
response to this problem, universities and EDA vendors have created solutions that look to
automate the iterative process, leveraging the vast amount of computing power available
today. The work of [8] provides an extensive reference list of such programs and categorizes
them as full design automation (FDA) tools. While an FDA approach can help overcome the
design time issue, it comes with the same problem as manual tweaking: It is even more
difficult for the designer to gain analytical insight and intuition, which is an important
ingredient for topology selection and innovation.
Taking a step back, we note that the key problem is not the equation set that describes
the circuit, which tends to be either amenable to manual derivation or available in standard
textbooks and publications. The main issue lies in linking the device sizing parameters
(geometries and bias currents) to the transistor’s representation within the circuit, typically in
form of a small-signal model. Therefore, while using FDA can be appropriate and justified in
some cases, it goes one step further than required, providing full automation at the expense of
analytical insight.
The design approach described in this book falls under the category of full design
handcrafting (FDH) [8]. It builds on classical hand analysis methods and eliminates the gap
between hand analysis and complex transistor behavior using SPICE-generated lookup tables
(see Figure 1.3). The tables contain the transistor’s equivalent small-signal parameters (gm,
gds, etc.) across a multi-dimensional sweep of the MOSFET’s terminal voltages. Since using
the lookup table data closely captures the behavior of the SPICE model, the approximation
issues of Figure 1.2 are eliminated and it is possible to achieve close agreement between the
desired specs and the simulated performance without iterative tweaking. Though in some
cases the calculations can literally be done by hand, it is usually more efficient to implement
the design flow through a computer script. In this book, we chose the popular Matlab®
environment for designing such scripts.

23
 Figure 1.3 Analog circuit design flow used in this book.

It is worth noting that the outlined approach does not resemble the “SPICE in the loop”
approach [9], [10] advocated in the 1980s. The main differences are: (1) The lookup tables
are created once and stored permanently; they do not get updated with each circuit simulation
run. (2) The design scripts tend to use abstract and simplified circuit models. This often
means that the designer does not need to worry about auxiliary circuits that may be required
to get a SPICE simulation to work. For example, it is possible to create a design script that
evaluates the small-signal performance of an amplifier under the assumption that the bias
point is perfectly set. How exactly that bias point is established can be determined later, after
studying the first-order performance tradeoffs.
To implement the design flow of Figure 1.3, we need the following ingredients:

A convenient way to generate and access the lookup table data. The generation of the
proposed lookup table format is described in Appendix 2. Examples on how to access
and use the stored data are given throughout this book (including an introductory
example in Section 1.2.2).

A suitable way to translate the design problem into a script that helps us study the key
tradeoffs and ultimately computes the final device sizes. Most of this book is
dedicated to this part of the flow. By means of examples, we study design problems of
varying complexity and the derived scripts can form the basis for future design
problems that the reader will encounter.

A key aspect of the proposed methodology is that we interpret and organize the lookup table
data based on the transistor’s inversion level, employing the transconductance efficiency gm/ID
as a proxy, and key parameter for design. This metric captures a device’s efficiency in
translating bias current to transconductance and spans nearly the same range in all modern
CMOS processes (~3…30 S/A). When combined with other figures of merit (gm/Cgg, gm/gds,
etc.), thinking in terms of gm/ID allows us to study the tradeoffs between bandwidth, noise,
distortion and power dissipation in a normalized space. The final bias currents and device

24
sizes follow from a straightforward de-normalization step using the current density (ID/W).
We will take a first look at this normalized design approach in Section 1.2.2.
The idea of gm/ID-based design was first articulated by Silveira, Jespers et al. in 1996
[11]. Since then, the approach has been continuously refined through academic research (see
e.g. [12]–[17]) and is being taught at various universities. Several companies known to the
authors have integrated lookup table based design into their design environments. These
efforts were driven by the first set of graduates being exposed to the methodology in school.
Despite this growing popularity, much needs to be done to make the approach accessible to a
broader community and specifically those engineers who have not acquired the material at the
university. The goal of this book is to provide a comprehensive resource that will accomplish
this.
It is important to note that several other authors have made contributions toward a
design methodology that follows the spirit of full design handcrafting with bridges between
hand analysis and simulation. Among them are the inversion coefficient (IC) based flows by
Binkley [18], Enz [19], and Sansen [20] as well as the 2010 gm/ID-centric book by Jespers
[21]. The main difference between these works and the present book is that they are still
based on analytical device models. Instead of working with purely numerical lookup table
data, these methodologies assume that the transistor characteristics can be fit to model
equations (typically EKV [22]) that are more complex than the square-law model, but not too
complex to be included in a design script environment. This approach is certainly workable
for today’s mainstream technologies, but we decided to go with a sizing approach that is
agnostic to the increasingly complex physical behavior of nanoscale transistors. Despite this
goal, we still make use of the EKV model to build intuition, but won’t use it to compute the
ultimate device sizes. This approach is made transparent in Chapters 2–4.

25
 1.2 The Analog Circuit Sizing Problem and the
Proposed Approach
Before outlining the remainder of this book, we feel that it is important to provide a short
(and simplified) walk-through of the proposed design methodology. For this purpose, we
assume that the reader is familiar with CMOS square-law design and we use the
shortcomings of the square law to motivate our approach.
Generally, the types of analog circuits that we consider in this book fall into the class-A
category, which means that they are operated with constant bias current. A basic example is
the differential pair shown in Figure 1.4, which is usually part of a larger circuit (not shown
for simplicity). Sizing the circuit in Figure 1.4 means that the designer must find suitable
values for

the bias current ID;

the device width W;

the channel length L.

For this introduction, we will assume that through some design process, we determined that
the differential pair should implement a certain transconductance (gm). How does this
requirement translate into values for ID, W and L? We will initially approach this question
using simple square-law expressions and then refine our treatment to arrive at the proposed
methodology.

Figure 1.4 Differential pair.

26
27
 1.2.1 Square-Law Perspective
Ideally, we would like to have an equation that relates all relevant parameters of the above
example with one another. The square-law model used in standard textbooks provides such
an expression [1]:

(1.1)

Even though this formula is inaccurate for modern devices, it clarifies a basic, and generally
important, point: there are an infinite number of choices for W, L and ID that all lead to the
design goal of realizing a certain value of gm. To continue, we need a feel for the tradeoff that
we are making by picking one of these many solutions.
To make progress, let us articulate what we would ideally like to achieve: We want to
meet the design goal using the lowest possible current and the smallest possible transistor
size. In absence of any other constraints (to be considered in later chapters), this immediately
implies that we should use the smallest available channel length L (for example, Lmin = 60 nm
for the technology used in this book).
The remaining question is whether we should minimize the current or the device width.
Note that achieving both simultaneously is not possible, since the product W×ID is fixed. To
think about this tradeoff systematically, we introduce two figures of merit that relate the
design objective (gm) to the variables that we want to minimize:

(1.2)

Using the standard textbook square-law expressions [1], we can write these figures of merit
as:

(1.3)

(1.4)

Here, is the quiescent point gate overdrive voltage of the transistor.

Physically, large VOV means that the channel is more strongly inverted, i.e. more inversion
charge is present underneath the gate.
The key observation from the above equations is that the gate overdrive controls how
efficiently we employ current (ID) or device width (W) to generate the desired

28
transconductance. The designer can pick a large VOV to arrive at a small device width or a
small VOV to minimize the current. Thus, the gate overdrive voltage can be viewed as a
“knob” (see Figure 1.5) that fully defines the sizing tradeoff. Also, note that once VOV has
been chosen, the required device current (for a given gm) follows directly from (1.3); no
technology-specific parameters are needed (assuming the square law holds).

Figure 1.5 The gate overdrive voltage VOV is a “knob” that lets us control the tradeoff
between gm/ID and gm/W.

In addition, the choice of VOV sets the minimum VDS for which the transistor remains
saturated (VDsat = VOV for a square-law device) and it also determines the circuit’s linearity
[23]. It is therefore not surprising that the gate overdrive is among the most important
parameters used in square-law centric circuit optimization. For example, the seminal work by
Shaeffer and Lee [24] studied the relationship between the gate overdrive voltage and the
bandwidth, noise and linearity of a low-noise amplifier (LNA). It was found that the tradeoff
between these performance metrics is fixed once a certain VOV is chosen.
Unfortunately, and as already discussed in Section 1.1, the square-law model has become
obsolete for design with modern MOS transistors. To see this, consider Figure 1.6, which
plots the figures of merit of (1.2) for a minimum-length n-channel device in 65-nm CMOS.
For reasons discussed in Chapter 2, the square-law expressions fit reasonably well only for a
narrow range of gate overdrives in strong inversion (say VOV = 0.2…0.4 V). Thus, (1.3) and
(1.4) do not accurately link VOV with gm/ID and gm/W and the expressions are consequently
unsuitable for design in the given 65-nm technology.

29
Discovering Diverse Content Through
Random Scribd Documents
 EDWARD N. LAWTON.
Edward N. Lawton, son of Isaac and Mary Ann Lawton, was born
in Newport, R. I., Jan. 15, 1847. He attended the public schools of
that city in his youth. He enlisted as a recruit and was assigned to
Battery H, First Rhode Island Light Artillery, Feb. 27, 1865. He
reported to the battery at Fort Tracy, Va., in front of Petersburg, Va.,
and was present with his battery at the battle before that place April
2, 1865, where he exemplified all the attributes that constitute a good
soldier. He was mustered out with the battery June 28, 1865.
He is a member of Charles E. Lawton Post, No. 5, of Newport, R. I.
He served two years as junior vice commander, and declined further
advancement. He is also a member of Battery H First Rhode Island
Light Artillery Veteran Association. He was a brave soldier, and,
consequently, is a good citizen.
 EDWIN NORTHROP.
Edwin Northrop was born in Fishkill, N. Y., Dec. 15, 1838, his
father being Jonas Northrop, of Bradford, Yorkshire County,
England, who came to this country in the year 1830, at the age of
nineteen. His mother, Ann Gaunt, was a native of Leeds, England.
Comrade Northrop received a common school education, and at
the age of seventeen was apprenticed to learn wool sorting, and
continued in this calling until his entrance into the service.
Comrade Northrop married Sarah Kyle, daughter of John
Ballantine, of Blackstone, Mass., and four children were the fruit of
this union.
At the commencement of the War of the Rebellion he made an
ineffectual attempt to enlist in a company then forming in
Woonsocket for the Second Rhode Island Infantry, afterwards
designated as Company I, but so eager at that time were the young
men of that town to enroll themselves among the defenders of the
Union, that before Comrade Northrop’s turn came to enter the
armory, it was announced that the roll was complete, and he was
debarred the honor of enrolling his name with a company that won
fame and renown in the annals of the history of the State.
Aug. 25, 1862, after making careful provision for his little family,
he enlisted in Battery H, First Rhode Island Light Artillery. He was
mustered into service with his battery Oct. 14, 1862, and served
faithfully and continuously with it until its final muster out June 28,
1865.
Soon after his return from the army he learned the dyer’s art,
which calling he has since followed. He worked at his trade in
Blackstone, Mass., leaving there in 1867, and settling in Norwalk,
Conn. While here he became intensely interested in the principles of
the Grand Army of the Republic, and was largely instrumental in the
organization of Buckingham Post, No. 12, at that place. He was
adjutant of the post from 1881 to 1883, and again in 1885, and its
commander in 1884. He was aide-de-camp on the staff of
Department Commander Ira E. Hicks, in 1882, and served the
department as assistant mustering and inspecting officer.
In 1886 he removed with his family to Dalton, Mass., and here
again took up the work of the Grand Army. He took an active part in
organizing Hancock Post, No. 187, Department of Massachusetts. He
was elected junior vice commander in 1887–8, senior vice
commander 1889, commander 1890, and was also appointed post
historian. His wife is an earnest working member of Hancock
Woman’s Relief Corps, No. 133, of the Department of Massachusetts.
He was aide-de-camp to Department Commander Myron P.
Walker; served as inspector and mustering officer, and was elected
an alternate to the National Encampment in 1888.
On his removal to Kenyon, R. I., 1892, where he is employed by E.
Kenyon & Sons, he became interested with the comrades of Burnside
Post, No. 2, of Shannock, and before joining the post was, for
services rendered, voted an honorary member. He is now (in 1894)
commander of the post. He has received many testimonials of the
esteem in which he is held by his comrades of Buckingham and
Hancock posts, which he values very highly.
He is also a Free Mason, having joined the order in 1868, at
Norwalk, Conn.
 ORVILLE BALCOM.
[This sketch was received too late to be placed in the list of sergeants.]
Sergt. Orville Balcom, son of William and Eliza Doty (Thomas)
Balcom, was born in the town of Cumberland, R. I., in 1841. His
parents removed to Attleboro, Mass., when he was six years of age.
During his youth he attended the public schools of Attleboro. He was
mustered as a private into Battery H, First Rhode Island Light
Artillery, Oct. 14, 1862. He was subsequently promoted to corporal
and sergeant. In the battles before Petersburg and at Sailor’s Creek
he performed every service incumbent upon him with credit to
himself and likewise to the battery. He was mustered out of service
June 28, 1865. He is a member of Battery H Veteran Association, and
is connected with various societies in Attleboro, and enjoys the
esteem and confidence of the citizens of that town.
 OTIS P. SNELL.
Otis P. Snell, son of Barney and Rebecca Snell, was born in
Cranston, R. I., in the year 1832. After he became a lad his parents
removed to Smithfield, R. I., where Otis attended the district school
in the fall and winter months, and assisted his father on the farm
during the remainder of the year. He subsequently worked in a
cotton mill for a time.
In the War of the Rebellion he enlisted in Battery H, First Rhode
Island Light Artillery, Sept. 6, 1862, and was mustered into service
Oct. 14, 1862. He participated with his battery in all the battles in
which it was engaged, and proved himself a good soldier.
Since his return from the army Comrade Snell has worked in a
cotton mill, but is now (1894) employed on a farm near Georgiaville,
R. I. He is a member of Battery H Veteran Association. He is held in
high esteem by his old comrades and his fellow townsmen.
 JOHN TAFT.
John Taft, son of John and Jane (Moore) Taft, was born in
Ireland June 5, 1832. He attended a private school in his youth. He
afterwards emigrated to the United States, and located in Natick, R.
I.
On the 20th of February, 1865, he enlisted as a recruit and was
assigned to Battery H, First Rhode Island Light Artillery. He
reported to the battery at Patrick’s Station, Va., Feb. 24, 1865. In the
battles before Petersburg and at Sailor’s Creek he evinced great
courage and proved to be reliable in every emergency. He was
mustered out with the battery at Providence, R. I., June 28, 1865.
Comrade Taft married Jane Rafferty, daughter of John and Mary
Rafferty. Two children have been born to them, namely, Thomas and
Joseph P. Taft. Our comrade is an esteemed member of Reno Post
No. 6, of East Greenwich, R. I., where he now resides, and is honored
and respected by his fellow townsmen.
 WILLIAM H. TASKER.
William H. Tasker, son of William and Annie (Carroll) Tasker,
was born in Providence, R. I., Nov. 12, 1842. His father served as a
soldier in the Mexican War, and was especially commended by his
superior officer for bravery in battle. The subject of our sketch
attended school in his youth in the city of Providence and also in the
town of Johnston, R. I. In the Fall of 1862 he enlisted in the navy as
an able seaman, and was assigned to the United States gunboat Iris.
He was subsequently promoted to signal quartermaster for good
conduct, and afterwards to quartermaster. After serving his time in
the navy he was mustered out, and shortly afterwards enlisted as a
private in Battery H, when it was stationed near Fort Tracy at
Petersburg, March 7, 1865. In the battles before Petersburg, and also
at Sailor’s Creek, he displayed good conduct in action, and was
finally mustered out with his battery June 28, 1865.
Comrade Tasker is a member of Slocum Post, No. 10, of
Providence, and is also a member of Farragut Naval Association,
having served as lieutenant, lieutenant-commander, and commander
in that association. He is connected with Battery H Veteran
Association. He is now a resident of Rehoboth, Mass., having
purchased the Bowen farm, and is therefore a respected tiller of the
soil, honored and respected in the community.
 CHARLES D. VAUGHN.
Charles D. Vaughn, son of John and Catherine (Danforth)
Vaughn, was born in Providence, R. I., July 17, 1836. He attended the
public schools of that city in his youth. At the breaking out of the
Rebellion he enlisted as a private in Company C, First Rhode Island
Detached Militia, May 2, 1861. He participated with his regiment in
the battle of Bull Run, July 21, 1861, and was mustered out at the
expiration of his term of service, Aug. 2, 1861. He enlisted as a
private in Battery H, First Rhode Island Light Artillery, Feb. 23,
1864, and served with credit in the battery until its muster out of
service, June 28, 1865.
 ALBERT WELLS.
Albert Wells, son of Silas and Mary (Bowen) Wells, was born in
Exeter, R. I., March 21, 1830. He attended the public schools of this
place in his youth, also those in River Point and West Greenwich, R.
I. His parents removing to Sterling, Conn., he attended school there,
working a portion of the time in the Valentine mill in that town. His
parents subsequently removed to Central Village, Plainfield, Conn.,
in 1847, and afterwards, in 1848, to Griswold, Conn., where he
worked in Doane’s mill.
In 1849 Albert left home and went to Crompton to work in the
machine shop in that place. In 1851 he married Almira O. Johnson,
and subsequently went to West Greenwich where he worked on a
farm, and afterwards engaged as a contractor for ship timber for
Dexter Irons. In 1855 he took a contract for supplying ties for the
Providence, Hartford and Fishkill Railroad Company. In 1857 he was
a contractor for ship timber with the United States government.
Comrade Wells enlisted as a private in Battery H, First Rhode
Island Light Artillery, Aug. 5, 1862, and served honorably with the
battery until its muster out of service June 28, 1865.
Shortly after his return to Rhode Island he worked for a while in
the Liberty factory in West Greenwich, R. I. In 1866 he built a small
shingle mill in that place, and was afterwards engaged in furnishing
wood supplies for woolen mills. In 1877 he built a large mill farther
up the stream for the same purpose. In 1882 he removed to
Providence, R. I., and was employed in the Rhode Island Locomotive
Works, remaining there until 1889, when he engaged in the carriage
business for himself for one year, and then went to work in the repair
shop of the Union Railroad Company, where he has remained until
the present time (1894).
Comrade Wells is a member of Prescott Post, No. 1, of Providence,
and is also connected with Battery H Veteran Association.
 HENRY A. ALEXANDER.
Henry A. Alexander, son of James A. and Jerusha M. (Skinner)
Alexander, was born in Foxboro, Mass., on the 20th day of January,
1824. He attended the district school of that town in his youth, and
subsequently attended school in Natick, Mass. He afterwards learned
the business of a rubber worker, which calling he still follows.
He enlisted in Battery H, First Rhode Island Light Artillery, Sept.
25, 1862, and was mustered into service Oct. 14, 1862. Owing to
failing health he was transferred to the Veteran Reserve Corps Sept.
30, 1863. On his return from the army he located in his native town
(Foxboro), and is an honored member of E. P. Carpenter Post, No.
91, of the Department of Massachusetts, Grand Army of the
Republic. He is also a member of Fair Oaks Commandery No. 20, of
Natick, Mass. He is also connected with Battery H Veteran
Association.
 HORACE C. BRIGGS.
Horace C. Briggs, son of Silas and Robey Briggs, was born in the
town of Pittsfield, Oswego County, State of New York, on the 12th
day of May, 1829. His grandfather, Joseph Briggs, served in the
Continental Army in the Revolutionary War. During his youth the
subject of our sketch attended the district school in his native town.
Comrade Briggs enlisted in Battery H, First Rhode Island Light
Artillery, Sept. 9, 1862. During a portion of his term of service he was
on detached duty as an orderly for Lieut.-Col. J. Albert Monroe, of
the First Rhode Island Light Artillery, who was chief of artillery of
the Second Army Corps. He was mustered out of service with his
battery at Providence, R. I., June 28, 1865.
Comrade Briggs is a member of E. B. Piper Post, No. 157,
Department of Massachusetts. He has served as junior and senior
vice commander of his post, and is held in high esteem by his fellow
townsmen of Walpole, Mass., where he now resides. He is also a
member of Battery H Veteran Association.
ROSTER.
 Captains.
Charles H. J. Hamlin. First lieutenant and quartermaster, First
Rhode Island Light Artillery, Oct. 3, 1861; promoted to captain,
Battery H, May 16, 1862; never mustered; resigned, Sept. 27,
1862.
Jeffrey Hazard. Mustered Oct. 14, 1862; second lieutenant,
Battery A, First Rhode Island Light Artillery, Oct. 5, 1861;
promoted to first lieutenant and regimental adjutant; captain,
Battery H, Oct. 1, 1862; resigned, Aug. 17, 1863.
Crawford Allen, Jr. Mustered Oct. 1, 1863; second lieutenant,
Battery G, First Rhode Island Light Artillery, Nov. 7, 1861; first
lieutenant, Nov. 18, 1862; wounded May 3, 1863, at
Fredericksburg; appointed regimental adjutant; acting
adjutant-general, Artillery Brigade, Sixth Corps; captain,
Battery H, Sept. 30, 1863; brevet major, April 2, 1865, for
gallant and meritorious service before Petersburg, Va.; brevet
lieutenant-colonel, June 12, 1865; mustered out of service June
28, 1865.
 First Lieutenants.
Clement Webster. Mustered Oct. 14, 1862; resigned Feb. 7, 1863.
Charles F. Mason. Mustered Oct. 15, 1862; second lieutenant,
Battery A, First R. I. Light Artillery, Dec. 24, 1861; first
lieutenant, Oct. 1, 1862; transferred to Battery H, Oct. 15, 1862;
subsequently appointed aide on Colonel Tompkins’s staff;
resigned April 21, 1864.
George W. Blair. Mustered Feb. 6, 1863; private, First Rhode
Island Light Battery, May 2, 1861; discharged Aug. 6, 1861;
sergeant, Battery B, First Rhode Island Light Artillery, Aug. 13,
1861; first sergeant, Dec. 2, 1861; discharged Feb. 6, 1863; first
lieutenant, Battery I, to date from Feb. 2, 1863; battery never
organized; first lieutenant, Battery H, April 23, 1863; resigned
April 29, 1864.
Walter M. Knight. Mustered April 8, 1863; quartermaster-
sergeant, Battery F, First Rhode Island Light Artillery, Oct. 29,
1861; second lieutenant, Battery H, March 11, 1863; first
lieutenant, April 22, 1864; brevet captain, April 2, 1865, for
gallant and meritorious services before Petersburg, Va.;
mustered out of service, June 28, 1865.
Allen Hoar. Mustered Aug. 24, 1864; private, Battery G, First
Rhode Island Light Artillery, Dec. 2, 1861; sergeant, June 9,
1862; wounded slightly Sept. 17, 1862, at battle of Antietam,
Va.; second lieutenant, May 14, 1863; first lieutenant, Battery
H, Aug. 17, 1864; mustered out of service June 28, 1865.
 Second Lieutenants.
Kirby Steinhauer. Mustered Oct. 14, 1862; sergeant, Battery G,
First Rhode Island Light Artillery, Dec. 2, 1861; second
lieutenant, Battery H, June 4, 1862; first lieutenant, Battery D,
Feb. 8, 1863; resigned April 19, 1864, on account of disability.
Elmer L. Corthell. Mustered about Oct. 30, 1862; private,
Battery A, First Rhode Island Light Artillery, June 6, 1861;
transferred to Battery F, Oct. 31, 1861; sergeant, Oct. 31, 1861;
second lieutenant, Battery H, Oct. 11, 1862; first lieutenant,
Battery G, Nov. 6, 1863; captain, Battery D, Oct. 21, 1864;
mustered out of service July 17, 1865.
Walter M. Knight. See first lieutenant.
Benjamin H. Child. Mustered Jan. 8, 1864; private, Battery A,
First Rhode Island Light Artillery, June 6, 1861; slightly
wounded July 21, 1861, at battle of Bull Run; corporal, July 16,
1863; wounded slightly in head at battle of Antietam, Sept. 17,
1862; sergeant, Sept. 12, 1862; wounded severely in shoulder at
battle of Gettysburg, July 2, 1863; second lieutenant, Battery
H, Nov. 6, 1863; mustered Jan. 8, 1864; resigned Nov. 23,
1864, on account of wounds.
Samuel G. Colwell. Mustered Nov. 11, 1863; sergeant, Battery H,
Oct. 14, 1862; second lieutenant, Nov. 6, 1863; transferred to
Battery A, Nov. 14, 1863; resigned April 15, 1864, for physical
disability.
Anthony B. Horton. Mustered Dec. 20, 1864; private, Battery B,
First Rhode Island Light Artillery, Aug. 13, 1861; corporal,
March 25, 1862; sergeant, Dec. 1, 1862; re-enlisted, Feb. 8,
1864; first sergeant, Oct. 3, 1864; discharged, Dec. 19, 1864;
second lieutenant, Battery H, to date from Nov. 29, 1864;
mustered, Dec. 20, 1864; brevet first lieutenant, April 2, 1865,
for gallant and meritorious services before Petersburg, Va.;
mustered out of service June 28, 1865.
William B. Westcott. Mustered May 1, 1864; private, Battery G,
First Rhode Island Light Artillery, Dec. 2, 1861; sergeant, Dec.
2, 1861; quartermaster-sergeant, June 9, 1862; second-
lieutenant, Battery H, April 26, 1864; first lieutenant, Battery
B, March 2, 1865; mustered out of service June 12, 1865.
George Lewis. Enlisted as private in Battery E, First Rhode Island
Light Artillery, Sept. 24, 1861; mustered Sept. 30, 1861;
wounded slightly May 3, 1863, at Chancellorsville, Va.; lance
corporal, May 29, 1863; corporal, Sept. 4, 1863; re-enlisted,
Feb. 1, 1864; lance sergeant, April 9, 1864; sergeant, Oct. 20,
1864, to date from Oct. 4; second lieutenant, March 31, 1865;
assigned to Battery H, May 29, 1865; never reported or
mustered as such; mustered out June 14, 1865.
 First Sergeants.
George Messinger. Mustered Oct. 14, 1862; private, Battery A,
First Rhode Island Light Artillery, June 6, 1861; transferred
and promoted to first sergeant, Battery H, July 8, 1862;
appointed company clerk; reënlisted Jan. 4, 1864; mustered
out of service June 28, 1865.
Jacob B. Lewis. Mustered as sergeant, Oct. 14, 1862; sergeant,
Battery B, First Rhode Island Light Artillery, Aug. 13, 1861;
discharged Dec. 11, 1861; first sergeant, Battery H, Oct. 14,
1862; mustered out, June 28, 1865.
Charles E. Bonn. Mustered as corporal, Oct. 14, 1862; sergeant;
first sergeant; second lieutenant, Battery D, First Rhode Island
Light Artillery, April 26, 1864; first lieutenant, April 3, 1865;
breveted captain; mustered out of service July 17, 1865.
John Evans. Mustered as private, Jan. 6, 1863; first sergeant;
mustered out of service June 28, 1865.
John P. Campbell, 1st. Mustered as private, Oct. 14, 1862;
corporal; sergeant; first sergeant in December, 1864; mustered
out as such June 28, 1865.
 Quartermaster-Sergeants.
Jenckes B. Stevens. Mustered Oct. 14, 1862; mustered out of
service June 28, 1865.
Hezekiah Potter. Mustered as private, Oct. 14, 1862;
quartermaster-sergeant, March 28, 1864; second lieutenant,
Battery E, First Rhode Island Light Artillery, Oct. 21, 1864;
mustered Nov. 11, 1864; first lieutenant, June 12, 1865;
mustered out of service June 14, 1865.
Albert F. Allen. Mustered as sergeant, Oct. 14, 1862;
quartermaster-sergeant, Oct. 21, 1864; mustered out of service
June 28, 1865.
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