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DSD Project Report

The project report details the design and implementation of a stopwatch using Verilog on a Nexys 4 FPGA, featuring accurate timekeeping and user controls for start, stop, and reset functions. It outlines the system architecture, functional description, design implementation, FPGA constraints, and procedural steps for setup and testing. Future enhancements include additional features and optimizations for performance and compatibility with other FPGA platforms.

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Raja Saad
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22 views5 pages

DSD Project Report

The project report details the design and implementation of a stopwatch using Verilog on a Nexys 4 FPGA, featuring accurate timekeeping and user controls for start, stop, and reset functions. It outlines the system architecture, functional description, design implementation, FPGA constraints, and procedural steps for setup and testing. Future enhancements include additional features and optimizations for performance and compatibility with other FPGA platforms.

Uploaded by

Raja Saad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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UNIVERSITY OF ENGINEERING AND TECHNOLOGY, TAXILA

Digital Systems Design

PROJECT REPORT

Title: Complex Engineering Problem/Project

INSTRUCTOR
Dr. Abdul Rehman Aslam

SUBMITTED BY:
Hamza Bashir 21-CP-41
Raja Saad 21-CP-85
Shahzad Hussain 21-CP-105

DEPARTMENT OF COMPUTER AND ENGINEERING


Implementation of Stopwatch on Nexys 4 FPGA

Objective:
The objective of this project is to design a stopwatch using Verilog and seven-segment displays
for deployment on a Nexys 4 FPGA. The stopwatch should provide accurate timekeeping,
start/stop/reset functionality via push buttons, and display hours, minutes, seconds, and tenths
of a second.

1. System Architecture:
- The stopwatch design comprises three main modules: `top`, `stop_watch`, and
`seg_display_driver`.
- The `top` module serves as the top-level entity, integrating the stopwatch and display driver
modules.
- The `stop_watch` module handles core stopwatch functionality, including time counting,
start/stop control, and reset.
- The `seg_display_driver` module drives the seven-segment displays based on input time
values.

2. Functional Description:
- Timekeeping: Utilizes a 100 MHz clock signal for accurate time measurement.
- Display: Four seven-segment displays show hours, minutes, seconds, and tenths of a
second.
- Start/Stop/Reset:
- Start: Initiates stopwatch counting from 00:00:00.0 when pressed.
- Stop: Pauses stopwatch at the current time; resumes counting from the paused time upon
subsequent presses.
- Reset: Resets the stopwatch to 00:00:00.0 when pressed.
- Overflow Handling: The stopwatch wraps around at 99:59:59.9, resetting to 00:00:00.0
after reaching the maximum time.

3. Design Implementation:
- Button Debouncing: Implemented in the `stop_watch` module to ensure reliable
start/stop/reset operations.
- Clock Generation: Utilizes a clock divider to generate a 100 Hz signal from the 100 MHz
clock for precise timekeeping.
- Counter Logic: Maintains separate counters for hours, minutes, seconds, and tenths of a
second.
- BCD Conversion: Converts binary counter values to BCD format for display on seven-
segment displays.

4. FPGA Constraints:
- Clock Routing: The 100 MHz clock signal is routed to pin `E3` to ensure proper timing.
- IO Standards: All input and output signals are constrained to LVCMOS33 for
compatibility.
- Pin Assignments: Critical signals such as clock, reset, start, stop, and display outputs are
assigned to specific pins on the FPGA board.

5. Procedural Steps:
• Setup Hardware:
1. Connect the Nexys 4 FPGA board to a computer via USB.
2. Ensure the FPGA board is powered on and recognized by the computer.
• Open Development Environment:s
1. Launch the Vivado IDE or the preferred FPGA development software.
2. Create a new project and specify the FPGA device as Nexys 4.
• Project Configuration:
1. Import the Verilog source files containing the stopwatch design.
2. Define the clock constraints and IO standards in the project settings.
• Synthesis and Implementation:
1. Run synthesis to generate the RTL netlist.
2. Perform implementation to map the design to FPGA resources.
• Generate Bitstream:
1. Generate the bitstream file for configuring the FPGA.
2. Verify timing constraints and resolve any critical warnings or errors.
• Configure FPGA:
1. Download the generated bitstream onto the Nexys 4 FPGA board.
2. Verify proper functionality of the stopwatch on the FPGA board.
• Test Functionality:
1. Press the start button to initiate stopwatch counting.
2. Verify accurate timekeeping and display of hours, minutes, seconds, and tenths
of a second.
3. Test the stop and reset buttons to ensure proper functionality.

6. Conclusion:
- The Verilog design successfully meets all specified requirements outlined in the project
question.
- Through proper module organization, efficient coding practices, and adherence to FPGA
constraints, the stopwatch implementation achieves accurate timekeeping and reliable
functionality.
- The design demonstrates effective utilization of FPGA resources and provides a robust
foundation for further enhancements or integration into larger systems.

6. Future Enhancements:
- Integration of additional features such as lap timing, countdown mode, or user interface
enhancements.
- Optimization for resource usage or performance improvements.
- Compatibility with different FPGA platforms or expansion to support external interfaces.

Snap Before Stopwatch Start:

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