Design of an Advanced sEMG Processor

MASSACHUSETTS INSTI TUTE

for Wearable Robotics Applications OF TECHN0LOGY

by OCT 0 4 2019

Seong Ho Yeon LIBRARIES

ARCHIVES
B.S., Georgia Institute of Technology (2016)
B.S., Korea Advanced Institute of Science and Technology (2016)

Submitted to the Program in Media Arts and Sciences,

School of Architecture and Planning
in partial fulfillment of the requirements for the degree of
Master of Science in Media Arts and Sciences
at the

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

September 2019

oMassachusetts Institute of Technology 2019. All rights reserved.

Signature redacted
Author ..............................................
Program in Media Arts and Sciences,
August 5, 2019

Certified by........Signatureredacted ...............

Hugh Herr
Professor of Media Arts and Sciences
Thesis Supervisor

Accepted by....................Signatureredacted
Tod Machover
Academic Head, rogram in Med Arts and Sciences
 Design of an Advanced sEMG Processor
for Wearable Robotics Applications
by
Seong Ho Yeon

Submitted to the Program in Media Arts and Sciences,,

School of Architecture and Planning
on August 5, 2019, in partial fulfillment of the
requirements for the degree of
Master of Science in Media Arts and Sciences

Abstract
This thesis presents the design and evaluation of a surface electromyography(sEMG)
acquisition platform specialized for wearable robotic applications. While sEMG is
one of the best ways to interpret human muscle and neural activity, the research field
in wearable robotics has limitations in utilizing sEMG signals with commercially-
available sEMG acquisition platforms. These limitations include a large and bulky
electronics package, poor portability, insufficient electrode versatility, and limited re-
configurability. This thesis aims to present an effective design that provides solutions
to these many difficulties while insuring robustness and acquisition signal quality.
The thesis reasons and explains in detail every design decision and process among
the system development and manufacturing. The evaluation of the manufactured
system compared to a benchtop state-of-the-art sEMG recording platform is demon-
strated. Practical utility of the developed sEMG measurement system is also demon-
strated with a real world wearable robotic application.

Thesis Supervisor: Hugh Herr

Title: Professor of Media Arts and Sciences

3
4
 Design of an Advanced sEMG Processor
for Wearable Robotics Applications
by
Seong Ho Yeon

The following people served as readers for this thesis:

Signature redacted
Thesis Reader . .
Edward Boyden
Y. Eva Tan Professor in Neurotechnology at MIT
MIT Media Lab

Signature redacted
Thesis Reader ....
Joeseph A. Paradiso
Professor
MIT Media Lab
(

5
6
Acknowledgments
First of all, I wish to thank my mentor and advisor Dr. Hugh Herr for guiding

me throughout the whole journey of my Master's program and supporting me to

consistently pursue my own project. I am also deeply grateful to my thesis readers,

Dr. Edward Boyden and Dr. Joseph Paradiso, for their invaluable advice and support.

Also, I thank my friend and mentor Jean Francois (Jeff) Duval for technical men-

toring and critical design reviews. All of Jeff's inputs were extremely important and

improved the work's quality.

I also thank Jim Ewing, our very first test subject, for believing in me even when

the development process was arduous and time consuming. His support, patience,
and insight contributed enormously to the development of this work.

Thanks also to all of my colleagues within Biomechatronics. All of our discussions

helped me to remain focused on my thesis goals. Indeed, all of the time we spent

together in both work and play helped to inspire me to complete this thesis.

Lastly, I want to thank my parents and family for unconditional support and trust.

7
8
Contents

1 Introduction 19

1.1 Electromyography . . . . . . . . . . . . . . . . . . . . . . 19

.
1.2 M otivation . . . . . . . . . . . . . . . . . . . . . . . . . . 19

.
1.3 Purpose and Goal . . . . . . . . . . . . . . . . . . . . . . 22

.
1.4 O utline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

.
2 Design of Electronics Hardware 25

2.1 Design of Analog Front End (AFE) . . . . . . . . . . . . 27

.
2.1.1 Electrical Model of a Body-Electrode-AFE Interface . 27

2.1.2 Input Impedance of the AFE 28

2.1.3 Analog Filtering and Pre-processing 32

.

2.1.4 Input Signal Protection . . . . . . . 35

.

2.1.5 AFE Design Summary . . . . . . . 38

.

2.2 Design of Power Conditioning Architecture 40

.

2.2.1 Safety for Human Subject Trials . . 42

.

2.2.2 Power Input Flexibility . . . . . . . 43

.

2.2.3 System Robustness . . . . . . . . . 44

.

2.3 Design of Digital Processing Backend . . . 44

.

2.3.1 Digital Block Requirement . . . . . 44

.

2.3.2 Processor Selection . . . . . . . . . 46

.

2.4 System Integration . . . . . . . . . . . . . 47

.

9
3 Design of Supporting Softwares 51
3.1 Real-Time DSP of sEMG Signal ................. 52
3.1.1 Characteristics of sEMG Signal . . . . . . . . . . . . 52

.
3.1.2 Digital sEMG Processing for Wearable Robotics . . . 53

.
3.1.3 Design Consideration of Bandpass Filter . . . . . . . 54

.
3.1.4 Feature Extraction and Further Processing for Robotic A ppli-
cations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

.
3.2 Design of RTOS for Embedded System . . . . . . . . . . . . . . . . 63

.
3.2.1 Necessity and Requirement . . . . . . . . . . . . . . . . . . . 63

.
3.2.2 Process Scheduling and Context Management . . . . . . . . 65

.
3.2.3 Memory Management . . . . . . . . . . . . . . . . . . . . . . 66

.
3.2.4 Hardware Peripheral Control . . . . . . . . . . . . . . . . . . 68

.
3.3 User Interface Software . . . . . . . . . . . . . . . . . . . . . . . . . 69

.
3.3.1 Graphical User Interface . . . . . . . . . . . . . . . . . . . . 69

.
3.3.2 Real-Time Network I/O . . . . . . . . . . . . . . . . . . . . 70

.
4 System Evaluation 71
4.1 Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . 71
.
4.1.1 Differential Input Dynamic Range . . . . . . . . . . . . . . . 71
.

4.1.2 System Bandwidth . . . . . . . . . . . . . . . . . . . . . . . 72

.

4.2 Qualitative Comparison with a Commercial sEMG System . . . . . 73

.

4.2.1 Comparison Measurement Setup . . . . . . . . . . . . . . . . 73

.

4.2.2 Time Domain Signal Evaluation . . . . . . . . . . . . . . . . 80

.

4.2.3 Frequency Domain Signal Comparison . . . . . . . . . . . . 84

.

4.3 Utility Evaluation in Robotic Prosthesis Applications . . . . . . . . 88

.

4.3.1 Dynamic Measurement Interface for Prosthetic Socket . . . . 89

.

4.3.2 Analysis of sEMG Signal in Walking . . . . . . . . . . . . . 91

.

4.3.3 Control of Climbing Prosthesis System . . . . . . . . . . . . 92

.

4.3.4 Synchronized Motion Data Labeling . . . . . . . . . . . . . . 95

.

10
5 Discussions 101

5.1 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

A Hardware Schematics 103

B Bill of Materials 133

11
12
List of Figures

2-1 Layout of the developed sEMG system. . . . . . . . . . . . . . . . . . 25

2-2 Functional block diagram of the electronics hardware design. . . . . . 26

2-3 Electrical model of a body-electrode-AFE interface. . . . . . . . . . . 28

2-4 Simplified electrical model of a body-electrode-AFE interface. . . . . 29

2-5 Analog signal shielding methods comparison. . . . . . . . . . . . . . . 35

2-6 Result of sEMG measurements with varied of shielding schemes. . . . 37

2-7 AFE design summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2-8 Power conditioning block diagram of the hardware. . . . . . . . . . . 41

2-9 Power flow diagram among selected PMICs. . . . . . . . . . . . . . . 41

2-10 Isolation scheme of the AFE for a subject safety. . . . . . . . . . . . . 43

2-11 Rendering of the electronics hardware. . . . . . . . . . . . . . . . . . 47

2-12 Hardware sub-block function summary. . . . . . . . . . . . . . . . . . 48

3-1 General signal characteristics of sEMG signals. . . . . . . . . . . . . . 52

3-2 General post-processing pipeline of sEMG signals. . . . . . . . . . . . 54

3-3 Movement artifact power attenation with passband variation. . . . . . 56

3-4 Phase and magnitude responses of bandpass digital filters with pass-

band frequency of 80 ~ 400 Hz. . . . . . . . . . . . . . . . . . . . . . 58

3-5 Group delay responses of digital filters with passband frequency of 80

~ 400 H z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3-6 Phase and magnitude responses of bandpass digital filters with pass-

band frequency of 30 ~ 400 Hz. . . . . . . . . . . . . . . . . . . . . . 59

13
3-7 Group delay responses of bandpass digital filters with passband fre-
quency of 30 ~ 400 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3-8 Phase and magnitude responses of bandstop digital notch filters with
notch frequency of 60 Hz. . . . . . . . . . . . . . . . . . . . . . . . . 60

3-9 Group delay responses of bandstop digital notch filters with notch fre-
quency of 60 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3-10 Example utilization scenario of the sEMG system. . . . . . . . . . . . 64

3-11 Example process scheduling scheme of the RTOS. . . . . . . . . . . . 66

3-12 Example memory management scheme of the RTOS. . . . . . . . . . 67

3-13 Developed GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4-1 Dynamic range measurement setup. . . . . . . . . . . . . . . . . . . . 72

4-2 System evaluation setup with Ag/AgCl electrode interface. . . . . . . 75

4-3 System evaluation setup with dry electrode interface. . . . . . . . . . 75

4-4 Simultaneous sEMG measurement setup for comparison with a com-

mercial sEMG equipment. . . . . . . . . . . . . . . . . . . . . . . . . 77

4-5 Design of the bandpass filters for the equipment comparison. . . . . . 79

4-6 Measured raw and post-processed sEMG signals from the Refa-136
equipment and the manufactured sEMG system with Ag/AgCl electrode. 81

4-7 Measured raw and post-processed sEMG signals from the Refa-136
equipment and the manufactured sEMG system with custom dry metal
electrode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4-8 Power spectral density analysis with the Ag/AgCl electrode. . . . . . 85

4-9 Low-frequency noise analysis with the Ag/AgCl electrode. . . . . . . 86

4-10 Power spectral density analysis with the custom dry metal electrode. 87

4-11 Low-frequency noise analysis with with the custom dry metal electrode 88

4-12 Custom prosthetic liner with integrated fabric electrode. . . . . . . . 89

4-13 The manufactured sEMG system mounted on the socket with the
sEM G liner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14
4-14 Usage case of the developed sEMG system with a powered ankle pros-

th esis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4-15 Measured sEMG signals from the walking trial. . . . . . . . . . . . . 93

4-16 Conceptual block diagram of the robotic climbing ankle system. . . . 94

4-17 Usage cases of neurally-controlled robotic climbing ankle system in

real-w orld. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4-18 Measured sEMG signals from the climbing trial. . . . . . . . . . . . . 96

4-19 Measured joint positions actuated by the neural signals . . . . . . . . 97

4-20 Measured sEMG signals from the motion labeling trial. . . . . . . . . 98

15
16
List of Tables

1.1 Comparison of commercial sEMG systems. . . . . . . . . . . . . . . . 21

2.1 Symbols of the body-electrode-AFE model. . . . . . . . . . . . . . . . 28

2.2 Comparison of measured impedances of varied electrodes. . . . . . . . 30

2.3 Comparison of bio-potential acquisition frontend ICs. . . . . . . . . . 31

2.4 Review of analog filtering schemes in selected Biomechanics research

works. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.5 Required amplifier resources for different shielding methods. . . . . . 38

2.6 Specifications of the selected AFE components. . . . . . . . . . . . . 40

2.7 Processor tradeoff comparison. . . . . . . . . . . . . . . . . . . . . . . 46

2.8 Specifications of the selected MCU. . . . . . . . . . . . . . . . . . . . 46

2.9 Nominal specifications of the designed sEMG system. . . . . . . . . . 47

2.10 Selected core components of the designed sEMG system. . . . . . . . 49

3.1 International standard of sEMG filtering. . . . . . . . . . . . . . . . . 53

3.2 Digital filter pass band recommendations for sEMG processing. . . . . 57

3.3 Digital filter design method recommendations for sEMG processing. . 62

4.1 Dynamic range measurement result. . . . . . . . . . . . . . . . . . . . 72

4.2 System bandwidth measurement result. . . . . . . . . . . . . . . . . . 73

4.3 Specifications of the Refa-136 sEMG workstation. . . . . . . . . . . . 74

4.4 Specifications of the custom dry metal electrode. . . . . . . . . . . . . 76

4.5 sEMG measurement setup for comparison. . . . . . . . . . . . . . . . 78

4.6 Bandpass filters for the comparison of sEMG systems. . . . . . . . . . 78

17
4.7 Measured baseline noises for the comparison with the Ag/AgCl electrode 82
4.8 Measured baseline noises for the comparison with the custom dry metal
electrode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.9 sEMG measurement setup for the walking trial. . . . . . . . . . . . . 92
4.10 sEMG measurement setup for the climbing trial. . . . . . . . . . . . . 95
4.11 sEMG measurement setup for the motion labeling trial. . . . . . . . . 96

18
Chapter 1

Introduction

1.1 Electromyography

Electromyography (EMG) signals demonstrate collective motor unit action potentials

(MUAPs) of a muscle or muscles when they fire[l]. By analyzing the EMG signal

and estimated MUAPs, , we can extract valuable information for scientific inquiry,

as well as for the control of wearable robotics. Since C. J. De Luca[2] set common

standards for the use electromyography (EMG) in biomechanics research, surface

EMG (sEMG) has been a gold standard to estimate macroscale muscle activation non-

invasively.Many researchers have also utilized sEMG for volitional control of upper

and lower extremity prostheses, exoskeletons and orthoses[3][4].

1.2 Motivation

As sEMG has been the primary way to investigate human motor control in the biome-

chanics field, people have conducted a wide range of research on developing and im-

proving sEMG systems in many ways. Some of the major research and development

directions researchers have sought are as follows:

* Low-cost system development15][6]

* Improved analog signal conditioning[7][8]

19
 * Advancement in analog-front-end ASIC1911101

However, the knowledge acquired from the research field in advancing sEMG sys-
tem has not effectively been transferred to the research field of wearable robotics.
Rather, the research communities within the fields of biomechanics and wearable
robotics mainly utilize commercial sEMG systems for several reasons. First, they are
usually difficult to reproduce. In many cases, they present insufficient signal quality
due to engineering tradeoffs made in research. Last but not least, research products
usually lack the robustness necessary for human subject clinical trials.
Although commercial devices generally resolves the problems listed above, most of
them cannot satisfy all ideal requirements for wearable robotic applications including
dynamic exoskeletons, orthoses, or prostheses. Essential requirements of an sEMG
acquisition and processing platform includes the following:

Portability A human subjects should be able to mount the sEMG system on the
body with a reasonable comfort level. The system should not affect a subject's dy-
namic movement.

Versatile External Interfaces The system is required to have real-time, synchro-

nized, high-speed digital input/output(I/O) interfaces for system integration with
external robotic and computing devices through a variety of synchronized communi-
cation protocols.

Electrode Interfaces The system should be able to interface with different types
of electrodes including dry electrodes both physically and electrically. Electrode us-
age varies based on its application.

Based on the requirements listed above, commercially available sEMG platforms

from several major manufacturers on the market are compared in Table 1.1.

20
 Table 1.1: Comparison of commercial sEMG systems.

Manufacturer System Portability Electrode

Interface
I/OInterface #CH
Delsys Trigno Portable Integrated RCV USB 1 ~4
Delsys Bagnoli Benchtop Proprietary USB 8~16
Motion Lab MA-300/400 Benchtop Proprietary AN 2 /USB 16~32
Systems
TMSi Refa-64/136 Benchtop DIN USB 64~136

Biometrics SX230(&FW) Benchtop Proprietary USB 16~24

Snap
Biometrics Datalite EMG Portable Integrated RCV USB 1 1
Biopac BioNomadix Portable Proprietary RCV USB 1 2
Biopac Mobita Portable Proprietary Wifi ~32
Noraxon UltimEMG Portable Integrated RCV USB 1 1
1. RCV USB: PC-USB interface through proprietary wireless recevier.
2. AN: Analog Output.

In Table 1.1, the trends of the market and the limitations of the commercial plat-
forms are clearly visible. Most of the portable sEMG platforms on the market interface
with either integrated types of electrodes or their own proprietary electrodes. This is
not ideal for many wearable robotics applications. For instance, these devices cannot
be utilized in dynamic lower limb prosthetic research requiring extreme dynamic sur-
face loading inside a weight bearing socket. In this type of research, a special electrode
with an extremely low physical profile is required, but these measurement platforms
cannot interface with other types of electrodes. On top of that, most of the platforms
only interface with a personal computer with USB from the wireless receiver. These
limited I/O interfaces limit the robotic integration and closed-loop control capability.
For high-bandwidth robotic control applications, synchronized high-bandwidth I0/
is essential, and this equipment does not provide this options. Still further, some of
these commercial platforms provide post-processed and down-sampled outputs with
their proprietary processing pipelines. While the post-processed data provides con-
venience, it also limits research capabilities since this post-processing pipeline is not

21
opened in many cases.

Some of the limitations listed can be resolved with the implementation of the
custom application-specific sEMG system. Therefore, there is a necessity to develop
a portable sEMG platform that can overcome the limitations of commercial sEMG
systems while ensuring robustness and acquisition signal quality with an emphasis on
the efficacy and the practicality for wearable robotics applications.

1.3 Purpose and Goal

This thesis aims to develop an sEMG processing embedded system that can enable
and enlarge sEMG usage in the field of wearable robotics. Specifically, the purpose
of this thesis is not to develop a state-of-the-art sEMG platform demonstrating the
lowest noise, lowest-power, highest sampling rate, or other figures of merits being the
highest. Rather, here the developed sEMG system is designed in order to demon-
strate similar functionality as commercial sEMG measurment platforms in terms of
signal quality while overcoming current the limitations of the commercial platform in
terms of portability and system versatility. The detailed design goals of the system
developments are as follows:

• Portability
" High bandwidth, synchronized I/O interface for robotic applications
" Compatibility with varied types of electrode including passive dry electrodes
" Reconfigurable post-processing capabilities with transparent processing pipeline
* Ease of manufacturing

Satisfying these many requirements in addition to the basic functionality of com-

mercial platforms has the potential to expand research capability in the field of wear-
able robotics. A critical goal of thesis is that the resulting hardware and software will
allow the whole filed to experience an improved access to custom sEMG system.

22
1.4 Outline

In Chapter 2, the detailed design decisions and processes of the embedded system
hardware are discussed in detail. In Chapter 3, the development processes of re-
quired software stacks (signal processing pipeline, real-time operating firmware for
the electronics, graphic-user-interface, and communication interface) for the system
are explained and demonstrated. The designed and fabricated system is then evalu-
ated as a unit and in part of real-world applications in Chapter 4. Finally, Chapter
5 discusses the contributions of this work, as well as the required future work that
needs to be conducted in order for the proposed designs to have a greater impact on
the research community.

23
24
 -- 'I

Chapter 2

Design of Electronics Hardware

In this chapter, the decision and design processes of the electronics hardware for
sEMG measurement is explained in detail. Specifically, the design of the hardware in
this thesis refers to the following processes:

" Analysis of required electrical and computational specifications

* Choice of electronic components among commercially available components

" Design of electrical schematic and integration on printed-circuit-board (PCB)

Figure 2-1 shows the fabricated electronics as the result of the design in this
chapter.

(a) (b)

Figure 2-1: Layout of the developed sEMG system. (a) Top View. (b) Bottom View.

As mentioned in Chapter 1, one of the purposes of the thesis is to make the system
easily accessible to other researchers in the research field of wearable robotics. Thus,
application-specific-IC(ASIC) is not considered as a component of the system since
they are generally hard to access from the research field.

25
 The designed sEMG electronics consists of three major functional blocks: Analog-
Front-End(AFE), Digital Processing Backend, and Power Conditioning
Block. Figure 2-2 shows the three blocks with detailed subcomponents.

8-CH Analog Digital Block

Front End (AFE) High-speed 1/0

High Z - USB
Microcontroller
Intrumentation (MCU) - RS-485
Amplifer (IA) - 12C
- SPI
- USART
24-bit, 8-CH
Analog-to-Digital
Converter (ADC) Power Conditioning and Safety

Active Shielding USB Power MUX

Driver Input Range

Power/Comm Analog I Digital

Isolator LDOs

Figure 2-2: Functional block diagram of the electronics hardware design.

Detailed design reasoning and implementation of each functional block is discussed

in the following subsections.

26
2.1 Design of Analog Front End (AFE)

The Analog-Front-End (AFE) serves critical roles in the sEMG platform. The AFE
reads the raw analog signal from an electrode, pre-processes the analog signal, converts
raw analog signal to a digital signal, and conveys the signal to a digital computation
layer. In order to maximize the performance of the AFE in these roles, the purposes
of the AFE design are summarized as follows:

• AFE delivering maximal information from the muscle with minimal noise and
distortion
e AFE compatible with wide variety of electrodes
* AFE easily reproducible and providing robust signal quality (against manufac-
turing variances)

In order to achieve these design purposes, several improvements to the AFE are
made based on analyses of a body-electrode-AFE electrical model. Using this model,
key components of the AFE were then chosen.

2.1.1 Electrical Model of a Body-Electrode-AFE Interface

To design the AFE optimally, an electrical model of a body-electrode-AFE interface

was analyzed. Figure 2-3 shows modified electrical model of a body-electrode interface
from[11]1. Table 2.1 explains the physical implications of the symbols in Figure 2-3
and summarizes physical ranges for them.

To illustrate briefly, the target sEMG signal to acquire is illustrated as Vdin Figure
2-3. Thus, the purpose of the AFE design can be summarized as how to extract Vd
effectively and robustly from the AFE readingVAFE. The design decision of the AFE
sub-block architectures were made based on the model described in Figure 2-3 and
Table 2.1.

In this thesis, the AFE design paradigm is established mostly on a bipolar sEMG acquisition
setup

27
 Body-Electrode Analog-Front-End (AFE)

GND

.
Figure 2-3: Electrical model of abody-electrode-AFE interface. The AFE reads VAFE
and conveys the reading to adigital computational layer.

Table 2.1: Symbol implications of the body-electrode-AFE model.

Symbol Implication Physical Range

VCM Common mode voltage swing ~ 1 V
Vos Differential voltage offset ~ 500 mV (f < 20Hz) 1
Vd sEMG signal ~ 10 mV
VAFE AFE voltage reading
Zbe Body-electrode electrical impedance ~ 1GQ
ZAFE AFE electrical impedance
1. Frequency band is usually lies less than the frequency of 20Hz.

2.1.2 Input Impedance of the AFE

Analysis of the effect by an input impedance

Figure 2-4 visualizes the further simplified model from the body-electrode-AFE model
in Figure 2-3 emphasizing differential signal acquisition aspect.

28
 Body-Electrode Analog-Front-End (AFE)
+V* Vm

___
Dighta
ADC Core Signal

)
Output/

Vos

Figure 2-4: Simplified electrical model of a body-electrode-AFE interface emphasizing

differential signal acquisition.

From Figure 2-4, the relationship between Vd and VAFEcan be derived as Equation
2.1.

VAFE = Vbe X ZAFE , Vbe = VOS + Vd (2.1)

Zbe + ZAFE

Although Equation 2.1 is a straightforward equation, it contains a critical essence

and implication of an sEMG signal acquisition. It addresses the importance of under-
standing the effect of I/O impedance ratio between the body-electrode and the AFE.
Based on the purpose of the AFE, the AFE should be designed in order to preserve
the information from Vd inVAFE (the actual voltage reading of the measurement
equipment). Equation 2.2 shows the criteria to preserve the information from V in
VAFEmaximally based on Equation 2.1.

ZAFE >> Zbe (2.2)

Thus, in general, a larger input impedance of the AFE is considered better.

Nonetheless, the design decision should be made with considerations of other en-
gineering tradeoffs such as size, power consumption, cost, and others. Also, different
types of electrodes have impedance Zbe difference in the order of magnitude. It is
important to analyze an approximate value range of the impedance Zbe of each elec-

29
trode type. The table 2.2 shows a few approximate impedances Ze of several types
electrodes[111.

Table 2.2: Comparison of measured impedances of varied electrodes. Reprinted with

permission from 111]. © IEEE 2019.

Electrode Type Impedance Ze Zbe @ f= 100Hz

Wet Ag/AgCl 350 kQ 25 nF 53 kQ
Metal Plate 1.3 MQ 12 nF 120 kQ
Thin Film 550 MQ 220 pF 7.14 MQ
Cotton 305 MQ 34 pF 41.3 MQ
MEMS 650 kQ || -

-
Table 2.2 also shows the evaluated impedances of the listed electrode at the fre-
quency of 100Hz, which can be considered as a dominant frequency of a sEMG power
spectrum. The impedance at the frequency of 100 Hz was used as a decision metric
to estimate the electrode compatibility of the designed device.
For wearable robotics applications, the benefits of being compatible with Ag/AgCl
electrodes as well as dry metal or fabric types of electrodes are substantial. Thus,
the AFE is designed in order to have compatibility with these electrodes. To evalu-
ate "electrode compatibility," the author postulated that the impedance of the AFE
should be at least ten times higher than the electrode impedance to ensure robust
electrode compatibility. With this postulation, the required impedance condition was
derived in Equation 2.3 based on Table 2.2 and Equation 2.2.

ZAFE > max{Zbe}X 10 ~ 400MQ (2.3)

Thus, an input impedance of 400 MQ at the frequency of 100 Hz was decided as

a decision boundary of the minimal AFE input impedance.

Choice of the electrode interface IC

On the custom-off-the-shelf(COTS) components market, several types of ICs, includ-

ing an analog-to-digital converter(ADC), instrumentation amplifier(IA), and analog
buffer can be a candidate of the electrode interface IC. Table 2.3 shows the impedance

30
of representative state-of-the-art ICs for bio-potential acquisition at the frequency of

100 Hz.

Table 2.3: Comparison of bio-potential acquisition frontend ICs.

Component Type Impedance ZAFE ZAFE Manufacturer

Af= 100Hz

ADS1299 ADC 1GQ || 20pF 73.7 MQ Texas Instrument

1.3GO f= 10Hz
RHD2216 ADC 13MGQ f = 1kHz 127 MQ Intan Technologies

INA128 IA 10GQ 2pF A D.M.' 795.7 MQ Texas Instrument

100GQ |pF AD.M.12

INA828 IA 100GQ I2pF C.M. ~ 1.56 GQ Texas Instrument

AD8244 Buffer 10T | 4pF ~ 397.8 MQ Analog Devices

AD8422 IA 200GQ |2pF ~ 792.6 MQ Analog Devices
1. D.M.: Differential Mode Acquisition
2. C.M.: Common Mode Acquisition.

Only a few ICs with the type of IA meets the chosen decision metric, nominal

input impedance larger than 400 MQ at the frequency of 100 Hz. To prevent mis-

leading the context, there exists clear benefits and disadvantages for different types

of ICs such as ADC, IA, and analog buffer. To illustrate, ADCs listed in the table 2.3

have multi-channel input capabilities (ADS1299 with eight-channel inputs, RHD2216

with 16 channel inputs). Utilizing an ADC as an electrode interface IC can be sig-

nificantly beneficial in terms of minimizing the number of components used and an

overall footprint of the system. [10] compares capabilities of two ADC as a direct elec-

trode interface IC, and prior research exists that utilizes ADC as a direct electrode

frontend[9][12][13]. Nevertheless, in this thesis, the designed system utilized IA as a

first-stage AFE IC for each channel, as the author evaluated that the disadvantage

of having an additional footprint (3x5 mm2 per channel) is minimal compared to

the benefit of increased input impedance. Within the list of IAs, AD8422 (Analog

Devices) was utilized for the manufacturing of the system.

31
2.1.3 Analog Filtering and Pre-processing
In this subsection, the design of an analog filtering and pre-processing sub-block
is discussed. This block generally refers to a set of hardware components between
electrode connectors and analog-to-digital-converter(ADC). Designing analog filters
for an sEMG acquisition has been thoroughly researched in the field. To illustrate
a few, [7] presented a novel ac-coupled front-end for bio-potential measurement, and

[8] analyzed double differential acquisition method for active electrode development.
Several research works designed operational amplifiers(OPAMPs) based multi-stage
analog filters for band-pass filtering of sEMG signal with an emphasis of low-cost
design[5][6] . On top of that, in many areas of biomechanics researches, analog filters
have been used in sEMG acquisition. Table 2.4 shows several different design criterion
of analog filters in different biomechanics researches.

Table 2.4: Analog sampling and filtering frequencies for sEMG signal processing from
selected research works. Adapted with permission from1141.

Musce~rops 1
Muscle Groups' F Passband
)Fa (Hz) Fsample (Hz) Sources

BB 5 1000 2000 115]

VL, VM, ST, BF, RF, MG 5.5 600 1000 [16]
MG, TA 16 600 1000 [17]
ST, SM, BF 5 1000 2500 1181
1. BB: Biceps Brachii, BF:Biceps Femoris, MG:Medial Gastrocnemius, RF:Rectus Femoris,
SM:Semimembranosus, ST:Semitendinosus,TA:Tibialis Anterior, VL:Vastus Lateralis,
VM:Vastus Medialis.

Although there exist several conventions on how researchers have been designing
the analog filters and pre-processing sub-block, in this thesis, the design of the sub-
block was evaluated mainly based on the body-electrode-AFE model shown in Figure
2-3.

Analog Filtering and Common Mode Rejection Ratio(CMRR)

As mentioned above, several analog circuits were developed for pre-processing the
sEMGs signal in an hardware domain. Most of them were purposed to extract and

32
amplify Vd from VAFE in Figure 2-4 especially to apply bandpass filtering[7][8][19][201.
These processes include 1) differential AC-coupling with extremely large input capaci-

tors, 2) active bandpass filtering to eliminate low-frequency offset and high-frequency

white noise, and 3) notch filtering around power-line frequency. These approaches

were more effective in the past that the present when resolutions of the state-of-the-

art ADCs were limited above couple mV due to the limitation of the IC technology.

The analog pre-filtering approach was standardized for sEMG measurement since

then. However, this approach also accompanies several drawbacks such as the follow-

ing:

" Mismatch of components in differential filtering block can severely decrease

common-mode-rejection-ratio (CMRR). The tolerances of the filtering compo-

nents are required extremely high leading total cost increase.

" Core components for analog filtering (such as input capacitors) takes a large

circuit fooprint increasing the size of the system

" Amplifier ICs for analog filtering can consume large additional power

" Different analog filters distort the signal band. These non-linear distortion from

the filters leads quantitative analysis more difficult.

" Analog hardware filters are generally less-flexible than digital filters. These less

flexible filtering scheme limits the reconfigurability of the system.

Among the listed drawbacks, the CMRR requirement is justifiable with the body-

electrode-AFE model in Figure 2-3. In the model, VcM refers to an undesired

common-mode signal. The size of VCM in the model is an order of magnitude larger

compared to the sEMG signal Vd as described in Table 2.1. Thus, the low CMRR

caused by impedance mismatch of components in a differential analog filter could

lead to amplification of VcM in VAFE in the model. Thus, CMRR of the differential

measurement frontend should be high enough to cancel common mode signal VcM.

This CMRR criterion is recommended to be larger than 90 dB[21]. Moreover, the

CMRR criterion also justifies the usage of IA. Modern COTS IA provides CMRR of

higher than 110dB. The chosen IA for the electronics AD8244 provides the CMRR of

33
larger than 120 dB.
As the IC technology has been being improved, the general design paradigm of
the sEMG system also should be reevaluated. This analog filtering paradigm is orig-
inated when 1) the single chip ADC's resolution is larger than 1mV and 2) IC's
computational capability is relatively limited. In recent, multi-channel ADCs with
the resolution smaller than luV are widely available and computational capability
of digital processors are exponentially increased. By not using analog filtering com-
ponents, the drawbacks of hardware analog filters can be minimized. Thus, in this
thesis, the proposed sEMG measurement system was designed and fabricated without
an analog filter. The sEMG electronics hardware has an electrode connector directly
connected to IA, and the output of the IA propagates to the ADC directly. Also,
as the result of not using analog filtering, all post-processing is executed in a digi-
tal block. This also allows the designed system to have flexible filtering capability
to adjust and optimize the post-processing of the sEMG signal for different types
of applications. Table 2.4 also demonstrates the potential benefits of having flexible
data post-processing pipeline since different applications in the table utilized different
filtering standards and requirements.

Analog Signal Gain

Modern ADCs and lAs often have a capability to provide analog signal gain greater
than 10000. The analog signal gain of an IA and an ADC should be chosen carefully
with the consideration of the electrical model in Figure 2-4. As shown in Table 2.1,
the physical range of the differential voltage offset Vos is significantly larger compared
to the target signal Vd. Thus, amplifying the raw analog signal without canceling out
of the Vos will likely to cause signal railing of the ADC voltage reading, eliminating
the information from Vd. This is due to the fact that dynamic range of the ADC is
limited. Thus, the analog signal gain of the IA and the ADC before digitizing should
be low with the combination of minimal analog filtering scheme.
Also, since the analog signal gain is required to be small, the AFE requires high-
resolution ADC with the combination of pre-amplifier. A modern ADC with the

34
bit-resolution higher than 24-bit is generally recommended. Intuitively, the practical
role of pre-amplifier is to serve input impedance buffering with high CMRR interface,
while the ADC reads the signal with minute noise.

2.1.4 Input Signal Protection

Due to a small amplitude of an sEMG signal, it is important to physically protect the

hardware cable carrying an analog signal from an electrode to the AFE connector. As
one approach, the twisted pair differential signaling has been used to cancel common
mode noise effectively. Every corresponding bipolar electrode sets are recommended
to conform twisted bipolar hardware connection to AFE of the system. Additionally,
one of the major approaches for protecting small analog signal is to shield the electrical
cable physically. By wrapping the cable with a metal sheet and applying voltage on
it, the signal can be effectively protected from external electromagnetic noise. There
exists several shielding schemes for signal protection as shown in Figure 2-5[22].

+H2

CH1

A. No-Shield (Method 1) B. GND-Shield (Method 2)

+ CH4
+ CH 3

C. Bias-Shield (Method 3) D. Active-Shield (Method 4)

Figure 2-5: Analog signal shielding methods comparison. Reprinted with permission
from [22].

To illustrate Figure 2-5, there exists three primary ways to shield differential
signal cables: GND-shield, bias-shield, and active-shield. In GND-shield case, the

35
two bipolar signal lines are shielded with the output of an OPAMP driving virtual
ground voltage. This implies that the positive input of the OPAMP is connected
to ground while the output is connected to the negative input. The OPAMP is
driving ground voltage through its output node suppressing external noise to the
ground voltage level. In theory, it is possible to drive shieldings of multiple input
channels with only one OPAMP since they all share the ground node. Bias-shield
and active-shield methods also share the core mechanism. In bias-shield method,
the only difference with GND-shield method is that the OPAMP is driven by bias
generated by the voltage (usually an average of the positive and negative signals of
the diferential pair input). Thus, this bias-shield method requires one OPAMP per
one sEMG input channel. In active-shield method, OPAMP drives each signal line
applying negative feedback canceling out external noises. Figure 2-6 shows a result
of sEMG signal acquisitions with different types of shieldmethods[221.

36
 No-Shield
>0.5 50No-Shield

0 0

-0.5
0 0.5 1 1.5 2 2.5 3 0 50 100 150 20(
50Hz-Notch 50Hz-Notch
0.5 o5
0s 0
00

T -50
-0.5 E
0 0.5 1 1.5 2 2.5 3 < 0 50 100 150 20(
GND-Shield GND-Shield
f=50Hz, 4.9dB
0

>0.5 -50
0 50 100 150 20(0
Bias-Shield
0
50f=50Hz, y=2A4dB

S 0

E-0.5 -50
0 0.5 1 1.5 2 2.5 3 0 50 100 150 20X
Active-Shield Acive-Sheld
0.5
E-0.5 f=5OHz, y=-25.6dB
V 0 0

< 00 50 100 150 204

0 0.5 1 1.5 2 2.5 3
Time (s) Frequency (Hz)
(a) (b)

Figure 2-6: Result of sEMG measurements with varied of shielding schemes.

Reprinted with permission from [22].

In Figure 2-6, the active-shield method provides the best performance while bias-
shield method and GND-shield method also provide comparable performances. The
efficacies of different shielding methods can be compared objectively in power spec-
trum analysis. In the power spectrum analysis of the active-shield method, power
line noise around the frequency of 50 to 60 Hz was not visible. On the contrary,
attenuated power line noise is visible on the power spectrum analyses of GND-shield
method and bias-shield method.
Although the active-shield method provides the best shielding capability, there
exist different criteria to consider. First, the data presented in Figure 2-6 was collected
without twisted-pair signaling from the bipolar electrode. A significant portion of the
noise can be canceled out with the twisted-pair cabling scheme. With the twisted-
pair signaling, the effect of using different shield methods might not be as drastic as

37
presented in Figure 2-6.
Also, the required resources for each shielding method are largely varied. As
discussed above, the active-shield method utilizes two amplifiers per channel, while
bias-shield method and GND-shield use one amplifier per channel. In comparison
between bias-Shield and GND-shield, the required amount of amplifiers can signifi-
cantly different as the number of input channel scales up. Bias-shield method requires
reference bias voltage per channel requiring one amplifier per channel. GND-shield
method can share one OPAMP on several channel inputs (as many as OPAMP can
drive against the noise). Table 2.5 shows the required number of amplifiers for each
shielding methods assuming the case of eight-channel sEMG acquisition system.

Table 2.5: Required amplifier resources for different shielding methods.

Shielding scheme Required Number of Amplifiers

GND-shield 1
Bias-shield 8
Active-shield 16

Due to a significant difference in the required number of amplifier resources, the

designed system implements GND-shield method on the system using the OPAMP
IC , OPA2378 (Texas Instruments).

2.1.5 AFE Design Summary

Based on the discussion made, the AFE was designed based on the following design
decisions:

* Use of a miniaturized instrumentation amplifier IC with extremely high input

impedance (Za 2 400M © f=100Hz)
• Use of a multi-channel miniaturized ADC with high resolution
(ResolutionADC 2 24bit)
" Use of low analog gain (< 10)
* Minimal analog pre-processing

38
 e Differential twisted signaling with GND-shield

The statements above are the summarized design decisions of the AFE. Based on
the decisions, the overall design of the AFE is depicted in Figure 2-7. Table 2.6 shows
the chosen core components chosen for the AFE.
----------
Body ,,------------, Analog-Front-End (AFE)
S urface S-CH
notrumnenta on:
Differential Signaling A r
(1WIsted Pair)
+ uV Level
Signal
Buffered Low-N oise
Electro W PWR I nput

HCH
SHDI
-C>H2
Electrode
CH2

CH2
SHD

Digital
l High-t solution ADC Signal
Output
Activeiel""din High Input Z
uV Level Signal Input Low Gain

CHO
I
G:510
~~~~ byeartOPM

Active Shielding 1A output shielding

-CHO •IA Output
SHD) ,can be driven
.......... by separate OPAMP
Electrode Atv~rulN F
Active Shiling
Input Signal
OPAMP
Active Virtual GND
Electrode AFE
GND AGND)
---------- GND

Figure 2-7: AFE design summary.

39
 Table 2.6: Specifications of the selected AFE components.

Component Part Number Manufacturer Note

IA AD8422 Analog Devices Zip = 200GQ || 2pF
ADC ADS1299 Texas Instruments 24-bit, Input referred noise < 1pV
OPAMP OPA2378 Texas Instruments AMPspec

2.2 Design of Power Conditioning Architecture

In embedded system design, proper power conditioning is always a necessary condition

to ensure the robustness and the stability of the system. Specifically, in the sEMG
application, the role of power conditioning block is significant. Among many roles,
some of the critical roles of the power conditioning block are shown in the following:

" Safety of a subject

" Power input flexibility
* System robustness
" Efficient power management

The power conditioning block of the constructed sEMG system was designd in
order to achieve the roles stated above with minimal footprint. Figure 2-8 shows the
abstracted components layout of the power conditioning block of the system, and
Figure 2-8 shows the conceptual power flow among these ICs and the functions of
them.

40
 Isolated Block
LMWR16006Y BATT pwR
TP73525 WMe Range SMWPS 9V~
+2V6 LDO +V

+42V,AFE Analog PWR r~~I +5V

TPS2111 a
ISOW7842 '5V PWR MUX
8-CH A nalog
Front E id (AFE) PWR/COMM
Isolator
46v +sy~
AFE +3V3 3V3c 5V TIPS 73533
Digital 3V3 LDO
Block TXBO104
+
IC filter +5V
DigitalR
Digital COMM Digital PWR
signal Signal LVSHIFT
I-WV, AFE Analog PWR 5V -> 3V3
TPS72325 MA889
-2V5 LDOI- -3V3 Inverter) Digital
Signal

4 Data Flow 4 - PowerFlow

Figure 2-8: Power conditioning block diagram of the hardware. Red blocks represent
selected PMICs.

Input (V) e ~54 5 5 5 3.3 a.S -. 3 3.3

a 5 3.3 3.3 3.3 .. 3 -2.5 2.5

output (V)
StopDown Power Mux LowDropout PWRguCOU
LowDropout PWR& COi LC Filter Vot
Inverter RWgw taoltIlon
Function SMPO Regulao Isolation

User LOW High LOW LOW

Purose High System LOW
Efficiency Safety Noise Safety Noise Efficiency Nols Noise

5-4V LMR -----1 V A.V LC TPSv

BATPWR 16006Y TPS ISOW filter
5V 2111 TPS 7842 MAX TPS
USB PW 73533 889 7232
USB PWR 3.3V

3.3V 3.3V -. V 2.5V

Appllailon SytemDigital Blok Isolated AFE Digital Block AFE An lok

Block (U+Vm) BAA AM +ADC

Power High Efficiency Safety Low Noise

Flow Purpose Purpose Purpose

Figure 2-9: Power flow diagram among selected PMICs. The purposes of PMICs are
categorized into three groups: high efficiency, safety, and low-noise.

41

I
 Generally, each power conditioning IC was chosen with the emphasis of either high
efficiency, safety augmentation, or low-noise regulation. As power input flows from an
input voltage source to the functional block (the digital block or the AFE), the supply
power to the functional block is converted and regulated efficiently and robustly while
ensuring tolerable noise level to each block. Also, the power conditioning block isolates
the AFE from the primary power input source and limits maximum power delivery
rates to ensure the safety of a subject. The detailed explanation of Figure 2-8 is
discussed in the following subsections.

2.2.1 Safety for Human Subject Trials

The safety of a subject should always be a top priority in biomedical signal acquisition
platforms. In general, there exists regulation and guideline for commercial medical
devices, IEC-60601[23]. Specifically, electrical isolation and insulation between the
main power source and the AFE are the core requirements of the regulation. Although
the device was not designed to be commercialized currently, the proposed sEMG
system was designed to satisfy the safety regulation requirement.
The physical isolation on the system was established as shown in Figure 2-10. The
power and data transmission between the isolated and non-isolated blocks was enabled
with an isolation PMIC, ISOW7842 (Texas Instruments). With the isolator PMIC
satisfying the regulation requirement, the safety requirement for patient-acquisition
module was satisfied in the design phase.

42
 Eu-

U.U

C
-

Power Transfer
Analog Front End Block Limit upto 650 mW

SPI Communication

Electrically Isolated 16Mzlo

(a) (b)

Figure 2-10: Isolation scheme of the AFE for a subject safety. (a) 2-Dimensional
multi-plane layout of the electronics hardware emphasizing a physical isolation. (b)
3-Dimensional model of the electronics hardware visualizing the roles of the isolator
PMIC.

2.2.2 Power Input Flexibility

In wearable robotics applications, flexible power input options can be beneficial in

terms of user convenience. Strict power input condition on the electronics requires an
additional embedded system for power regulation that has to be carried by a subject.
As portability is always a requirement in wearable robotics applications, the system
requiring an additional component is not desirable. Thus, the proposed sEMG system
was designed to handle a wide range of power supply conditions. To describe, Figure
2-8 and Figure 2-9 show the power input capability of the sEMG system hardware.
Main power input interfaces with wide range input voltage step down switched-mode-

43
power-supply (SMPS), LMR16006Y (Texas Instruments). This first stage SMPS
enables efficient power supply from the power source of voltage range between 9V

to 54V and steps down to 5V voltage output. Also, the system was designed to

be capable of being powered up by a 5V USB input. This allows the system to be

powered directly from a portable single board computer (SBC). Power multiplexer

IC, TPS2111 (Texas Instruments), safely multiplexes the two power sources (main

power source and USB) in order to make sure the system can interface both power

sources at the same time. This feature is useful when the system is powered up by a

high power battery while the USB communication is required for high-level controller.

2.2.3 System Robustness

As depicted in Figure 2-9, the functional blocks (the digital block or the AFE) receive

the power supply from low-noise drop-out regulators. The supply power flows to

the functional blocks via cascaded PMICs from high-efficiency PMICs to low-noise

regulators. This cascade PMIC approach is effective in designing power flow for

insuring robustness of the system while demonstrating reasonable efficiency in power

conditioning.

2.3 Design of Digital Processing Backend

2.3.1 Digital Block Requirement

Computational Capability

A main computational processor processes the real-time sEMG post-processing. The

main processor is required to have the hard real-time capability with high data

throughput from the AFE to I/O interface for real-time digital signal processing

(DSP). The detailed DSP scheme is discussed in Chapter 3, but bandpass filtering

capability with the frequency of 1kHz is a minimum requirement to process the sEMG

signal in order to avoid data aliasing. Also, for hard real-time capability, the digital

block requires a hardware clock and a watchdog capability.

44
Input/Output Interface

The processor is required to have different types of real-time I/0 capabilities for

compatibility with different wearable robotics applications. Also, the importance of

high communication bandwidth of the I/O interfaces is explicitly emphasized in high-

bandwidth closed loop system integration. Although there exist numerous physical

communication interfaces for robotics applications, the system aims to provide some

of the major interfaces widely used in wearable robotics and mechatronics fields. The

selected physical I/0 interfaces of the electronics are shown in the following:

* RS-485
" Inter-Integrated Circuit (12 C)

* Serial Periphal Interface (SPI)

" Universal Asynchronous Reciever/Transmitter (UART)

" Universal Serial Bus (USB)

Thus, the digital processor of the system was required to have connectivities for

the above communication protocols.

Power Consumption and Footprint

Power consumption and footprint size of a computational processor are general trade-

offs against computational capability and I/0 versatility. Several computing cores

were considered as a main processor such as field-programmable-gate-array (FPGA),

microcontroller unit(MCU), and microprocessor. On top of power consumption, real-

time capabilities, and computation bandwidth, user interface and ease of reconfiguring

and programming are also significantly important for real-world research applications.

With qualitative comparison, MCU was chosen as the main processing core. Table

2.7 shows the general and qualitative comparison metrics.

45
 Table 2.7: Comparison of processor tradeoff.

Type Power Real-time Computing Reconfigurability

Consumption Capability Power
FPGA +++ +++ ++

+
MCU ++ +++ ++ +++
Microprocessor ++ + +++ +++
Number of '+' symbols refers to qualitative relative advantages.

2.3.2 Processor Selection

Based on the discussion above, versatile cortex-M4 architecture MCU was selected

as a main processor. The chosen MCU part is STM32F405 (ST Microelectronics).

Table 2.8 shows brief specifications of the MCU.

Table 2.8: Specifications of the selected MCU.

Specification Value
Part Number STM32F405
Supply Voltage 1.65 ~ 3.6 V (3.3 V is used)
Max Clock Speed 168 MHz
Max Current Consumption 240 mA
Architecture Cortex-M4
I/O Peripherals GPIO, SPI, I2C, UART, USB, CAN
Flash Memory 1 Mb
Memory Controller Direct Memory Access Enabled
Manufacturer ST Microelectronics

46
2.4 System Integration

With the considerations and decisions made in this chapter, the embedded system
for sEMG acquisition and processing was designed and manufactured. Figure 2-11
shows the rendered design of the hardware.

(a) (b)
Figure 2-11: Rendering of the electronics hardware. (a) Top view. (b) Bottom view.

The nominal overall specification of the designed sEMG system is shown in Table
2.9.

Table 2.9: Nominal specifications of the designed sEMG system.

Specification Value
Size 33 x 60 mm 2
Maximum sEMG Sampling Frequency 2 kHZ
Digital Interface SPI / 12C /UART / RS-485 / USB
PowerInput USB & 9 54 V voltage source
Number of sEMG Channel 8
Compatibile Electrodes Ag/AgCl, Dry Metal, Fabric
Dynamic Range 460 mV (±230 mV)
Estimated Noise Level < luVrms
User Interface PWR LED, RGB LED

Figure 2-12 shows the manufactured hardware and the explanation of overall major
blocks.

47
 lolated Power Digital UO Connector
Regulation UART I SPi ItC I RS-486

Instrumentation
Amplifier
USB Connector

EMG Electrode
Connector Main Power
Regulation

Main Power input

9 - 54 V

Active Shielding
Driver

Microcontroller
Programmer

ADC
Microcontroller
&Digital1O

Figure 2-12: Hardware sub-block function summary of the manufactured electronics

hardware.

Table 2.10 shows the core component selections. All the components were selected
from COTS electronics components markets.

48
 Table 2.10: Selected core components of the designed sEMG system.

Block Component Part Number Manufacturer

IA1 AD8422 Analog Devices

AFE ADC 2 ADS1299 Texas Instrument
OPAMP 3 OPA2376 Texas Instrument

Digital Processor Microcontroller STM32F405 ST Microelectronics

Isolator ISOW7842 Texas Instrument

4 LM16006Y Texas Instrument
e .ation SMPS
USB Power MUX TPS2001 Texas Instrument
1. IA: Instrumentatioi Amplifier.
2. ADC: Analog-to-Digital Converter.
3. OPAMP: Operation Amplifier.
4. SMPS: Switched Mode Power Supply.

Detailed design files including schematics and bill of materials are attached in
Appendix A and B. As the first prototype, the manufactured system met the required
functionality. The detailed evaluation result are discussed in Chapter 4. Also, there
exists some design aspects that need to be improved. The required improvements for
the next revision of hardware are discussed in Chapter 5.

49
50
Chapter 3

Design of Supporting Softwares

In general, harmonization between hardware and software is necessary to ensure good

performance of an embedded system. From the hardware design phase, the designer

should consider an overall firmware architecture and evaluate the overall system fea-

sibility over time. A firmware and a hardware of the system should be designed

complementary to each other. On top of firmware development, interface softwares

such as graphic user interface (GUI) or communication interface driver running on

a mainframe computer are also required to utilize the electronics hardware properly.

These interfaces are critical for users to debug and reconfigure the system in different

types of applications. In other words, for successful deployment of the embedded

system in real world, the designer of the system should provide a pipeline that users

can access the data inside an embedded system through physical byte stream to

user-friendly environments such as PC or other measurement equipment.

In this chapter, the design processes of required software stacks for sEMG system

are explained in detail. Specifically, the design of software stacks in this thesis refers

to the following processes:

" Analysis of requirements for sEMG filtering and post-processing specifically in

wearable robotics applications

" Design and implementation of real-time DSP and post-processing algorithms

" Design of the real-time operating system (RTOS) firmware for MCU

51
 * Design of the graphic user interface (GUI) and the communication interface
driver for a mainframe computer

3.1 Real-Time DSP of sEMG Signal

3.1.1 Characteristics of sEMG Signal

Frequency and amplitude characteristics of sEMG signals were well understood in
the field. 124] notes that bandwidth of sEMG signal generally lies in 20 - 1000 Hz,
while 125] shows that major portion of power spectrum of sEMG signalS lies in the
frequency band under 500 Hz. Figure 3-1 shows a good outline for understanding the
signal characteristics of sEMG signals.

o'10 ECG 10
Uso
102 EMG °
10°
0C4
00
offset 20-
10^'
0.1 10 100 1000 0 100 200 300 400 So0
Frequency (Hz)
Frequency (Hz)

(a) (b)

Figure 3-1: General signal characteristics of sEMG signals. (a) Amplitude-Bandwidth

overview of bio-potential signals reprinted with permission from [24]. © Springer
Nature. (b) Example sEMG power spectrum analysis reprinted with permission from
[25]. © 2019 Delsys Inc.

Also, international standards of sEMG processing for medical purpose recording

are shown in Table 3.1.

52
 Table 3.1: International standard of sEMG filtering.

Standard High-Pass Frequency (Hz) Low-Pass Frequency(Hz)

SENIAM 1 [26] 10 ~ 20 500
ISEK2 [27] 5 500
1. SENIAM: Surface EMG for non-invasive assessment of muscles[26j. The project of the European
Union
2. ISEK: The project of International Society of Electrophysiology and Kinesiology.

To summarize, a significant portion of the sEMG signal power is focused on a spe-

cific frequency band. This is the reason why bandpass filtering is generally considered

as the first step of sEMG signal processing.

3.1.2 Digital sEMG Processing for Wearable Robotics

Based on the sEMG signal characteristics discussed above, designs of digital post-

processing pipelines are discussed in this subsection. In the wearable and prosthetic

robotics applications, an acquired sEMG signal is mainly utilized as a real time con-

trol input for wearable robotic devices. Specifically, sEMG signals are widely utilized

to analyze users' intention quantitatively, to interpret the intention toward physical

quantities (such as force, torque, or position), and ultimately to transfer this infor-

mation to physical domain and to actuate mechatronics system[3].

Figure 3-2 shows the general sEMG processing pipeline for the wearable and pros-

thetic robotics applications.

53
 Reconfigurable
Band Pass Filter Feature Extractor Additional Processing
Envelope Detector
Sample Variable - RMS I MAV I LPF Dynamic
Raw & Reconfigurable Joint Model
Domain Transfer
Signal Band - FFT
- Wavelet Transform Pattern Recognition
from 20M0Hz - SVM
ADC (+ 60Hz Notch) TD Features - LDA
-Zero Crossing - etc
80-400Hz - Slope Sign Changes
- Variance
Custom Band - etc Other Models

Figure 3-2: General post-processing pipeline of sEMG signals for wearable robotics
applications

As depicted in Figure 3-2, several layers of post-processing are generally required

before the acquired sEMG signal can be used as a control input of an external device.

As noted above, the first step of the post-processing is bandpass filtering to reject noise

and to extract the signal of interest. This filtered signal is then further processed with

varied feature extraction algorithms. Some of the representative feature extraction

methods are shown in Figure 3-2.

The extracted features are used as 1) inputs of the iterative virtual joint model to

acquire joint torque/position or 2) inputs of pattern recognition framework to classify

general intention or to regress torque/position.

3.1.3 Design Consideration of Bandpass Filter

Since bandpass filtering is the first step of the post-processing, the bandpass filter

should be carefully designed for successful further processing. This subsection dis-

cusses tradeoffs, requirements, and design approaches of the bandpass filters.

General filter tradeoff In the past, most of sEMG acquisition and processing plat-
forms used hardware-based analog filtering before digitization. However, the thesis

already discussed the drawbacks of the hardware filtering approaches.

Utilizing a digital bandpass filter can avoid the drawback originate from the hard-

54
ware filtering. Thus, the design paradigm of the first stage digital bandpass filter for

acquiredf sEMG signal is discussed in this subsection. One might think that the de-

sign of bandpass filter is an obvious process as passband specification is determined,

but there exist other specifications that need to be considered carefully. The following

list shows general filter design specifications:

" Pass band and stop band frequencies

" Magnitude response : Stop-band attenuation should be decided based on the

signal power comparison between noise and desired sEMG signal.

• Phase response : How much distortion is allowed.

" Group delay response: Time delay from input signal component to output signal

component of each frequency.

* Stability : Whether filter output is stable or not.

" Cost of computation : How much computation is required to get one sample of

output

All of these specifications can be varied based on different design methods, and

they are engineering tradeoffs to each other. Thus, the bandpass filter should be

designed in a way that these specifications harmonize each other and provide the

best output responses for sEMG processing applications.

Design of pass/stop and magnitude response The decision of pass band and

stop band of the bandpass filter should be made with the following considerations:

" Strength of the power-line noise

" Allowable information loss of sEMG signal

* Allowable computational complexity

Although general trends and conventions exist, still the pass band of the filter is

required to be optimized based on its application. Specifically, pass band decision

directly relates to movement artifact cancellation and power-line noise cancellation.

55
 80

70

-
60
Movement Artifact

50

~40
30

20

10
sEMG

o o 0 0 0 00

Filter Increment (Hz)

Figure 3-3: Movement artifact power attenation with passband variation. Reprinted
with permission from [28]. © 2019 Elsevier.

Figure 3-3[28] shows movement artifact noise power attenuation based on different

pass band specifications.

Figure 3-3 implies that the benefits of using the bandpass filter with high pass
frequency higher than 20 Hz can be apparent for the applications entailing dynamic

movement while the loss of information is negligible. Also, in most developed coun-

tries, power delivery lines from the grid usually occupy the frequency band of either

50 Hz or 60 Hz. Although we protect the sEMG signal cables physically with GND-
shield scheme, still power line noise can be one of the most dominant noise sources

especially when the wearable system is functioning inside the building. Based on dif-

ferent applications, the user should evaluate the necessity of filtering power delivery

line. If preserving signal power of sEMG is important, then the user should use the

high-pass filter of around 20 Hz and insure to protect sEMG analog cable from the

56
power line noise.

If preservation of total sEMG signal power is not critical in some applications,

high pass filtering with the frequency of above 80 Hz might provide effective and

efficient noise cancellation methodology, and thus improve robustness of the overall

system. Table 3.2 shows the summarized design recommendation of the filter pass

band.

Table 3.2: Digital filter pass band recommendations for sEMG processing.

Application Passband Note

Frequency(Hz)
Indoor 80 - 400 Hz Augmented power-line noise cancelling
Outdoor 20 ~ 400 Hz Assuming low Power-line Noise existence

For the design of magnitude response of the sEMG bandpass filter, SENIAM[26]

and ISEK[27] recommend to attenuate stopband signal with an intensity of around

80 dB.

Analysis in phase response and group delay Design of phase response and

group delay generally gains less attention compared to the design of magnitude re-

sponse. Nonetheless, phase response and group delay of the filter also require careful

consideration to ensure proper performance in wearable robotics applications.

Among the digital filters having equivalent magnitude responses, phase response

of these filters can be largely varied. To explain the importance of phase response

and group delay design, phase, magnitude, and group delay responses of filters with

different design methods are analyzed in Figures 3-4, 3-5, 3-6, 3-7, 3-8, and 3-9. In

these analyses, bandpass filters with different design methods including three finite-

impulse-response (FIR) filters (generalized equiripple, minimum-phase equiripple, and

Kaiser) and two inifinite-impulse-response(IIR) filters(Butterworth and Elliptic) are

analyzed. These filters were designed on MATLAB2017B (Mathworks).

Figure 3-4 shows the magnitude and phase responses of the filters with the a band

of the frequency from 80 Hz to 400Hz with a sampling rate of 1kHz and a stop-

band attenuation of 80dB designed by different design methodologies. As shown in

57
Figure 3-4, although magnitude responses of four filters show similar responses, they
present significantly distinct responses in their phase plots. Figure 3-5 shows the
corresponding group delay of these filters based on the phase responses. Confining
the signal of interest in the bandwidth of 80 Hz ~, 400 Hz, the group delay can be
varying between 20 ms to 600 ms. In detail, minimum-phase equiripple FIR filter
provides the smallest group delay overall around pass band. Linear-phase equiripple
FIR filter provides a constant group delay ensuring no distortion of the filtered signal.
Figures 3-6, 3-7 also show similar intuition visualizing large difference in group
delay from filters with pass band of 30 Hz to 400 Hz and similar magnitude response.
Figures 3-8, 3-9 show the same type filter response plot of a notch filter the notch
frequency of 60 Hz for power-line noise cancellation.

I 0
I
0
so 30 4W N

I= M- 1

0.5

of -1
bnad ial .f Wip

Figure 3-4: Phase and magnitude responses of bandpass digital filters with passband
frequency of 80 ~ 400 Hz.

58
 60

0-

MI
0-

2C

0
Ion M 300 W amo SO ran s
9e 10
0-Hz)
-

FriLuenc kt) FieluWWy

Figure 3-5: Group delay responses of digital filters with passband frequency of 80
400 Hz.

I-
I

0 0N - NO a 0 00 100 00 0
FM*WMVnOcy FouMUy ft)

00 - - - - - --

I
1600
I
igg0

0 700 O N 400 No NO 700 NO No

0 too 2W 40 O M 7W M O low
1O
lo
Fmaq (Mt) Foqueny (H)

Figure 3-6: Phase and magnitude responses of bandpass digital filters with passband
frequency of 30 ~ 400 Hz.

59
 - ~
Our-it--I-

Au.

I 7W
A
II

y
0 so "0 WD Mno
FMWAMW M
300 30D AW 4W no a IN 2W 300 4W no
Fmquewy M
6W 7W am ON IQW

Figure 3-7: Group delay responses of bandpass digital filters with passband frequency
of 30 ~ 400 Hz.

DUOnw

100 1 20 40~
-b-P U
IN
*

J40D
.11W
.100

-14a 4W
M

a ---u-mo--
inu.vouu
10f-F s. - o-rn

FI:e

D0-

I0 I ; 0 W O o 10

0 "0 2W0 3W AU0 OW AU 100 AU AUo

"

FUQAOncy0t0) ,.M Lls(")

Figure 3-8: Phase and magnitude responses of bandstop digital notch filters with
notch frequency of 60 Hz.

60
 3W

-- pa

230

100

2Wm

Im

'I
It
o a IGO ISD no 250 - 4W3 450 gaW 0 1W 2W =a 4W m a O a M S I=a
F uaaa(Ha)

Figure 3-9: Group delay responses of bandstop digital notch filters with notch fre-
quency of 60 Hz.

61
 With reconfigurability of digital filtering, users should be able to design and opti-
mize bandpass filters based on their applications. Table 3.3 shows some of the filter
design recommendations based with different types of applications.

Table 3.3: Digital filter design method recommendations for sEMG processing.

Condition Filter Design Recommendation

Data Recording and Analysis Linear-Phase Equiripple FIR1
Closed-loop Control Minimum-Phase Equiripple FIR 1 / Elliptic IIR2
1. FIR: Finite impulse Response filter.
2. IIR: Infinite Impulse Response filter.

Additionally, the importance of group delay and full processing pipeline delay
design is justifiable. [29] noted that general electromechanical delay(EMD) of human's
Tibialis Anterior muscle is varied between 112 ms to 361 ms in ankle dorsiflexion. This
result possibly implies that controlling delay from sEMG measurement to control
output contributes or affect full system characteristics and capability since the EMD
of a human body is varying in a controlled way. Also, in 1301, introducing EMD
around 40 ms to 100ms range between sEMG measurement and force output leads
joint model having better performance compared to the model without the EMD.
These suggest that designing EMD can be a critical factor for the closed-loop control
system of wearable robotics, so the group delay of the bandpass filter for sEMG
post-processing should carefully be designed.

3.1.4 Feature Extraction and Further Processing for Robotic

Applications

Several robotic applications require further post-processing after the bandpass filter-
ing of sEMG signals. The purpose of designing this sEMG platform is to provide
robust sEMG post-processing pipeline that users can implement,optimize, and re-
configure based on their applications. Nonetheless, a few najor feature extraction
methods are pre-implemented for the convenience of future users.
One of the most generic ways to extract information to control an external hard-

62
ware is to extract the size of an envelope of a bandpassed sEMG signal. With a
given time window between 100 ms to 250 ms, root-mean-square (RMS), mean of
absolute value (MAV), and low-pass filtering of an absolute value are the three most
generic methods to extract the envelope features. Based on the envelope features, es-
timation of the percentage of maximal voluntary contraction (%MVC) can easily be
implemented. Calibrating maximum sEMG envelope data while a subject maximally
contracts a muscle as a reference point and calculating the ratio between real-time
measurement and the reference provide the estimate of %MVC of the muscle in real-
time[31]. Although the envelope has a crude correlation between the actual %MVC,
this estimation can be effectively utilized in several applications.

Besides these simple pre-implemented feature extraction methods, there exists di-
verse sEMG feature extraction methods[32]. The extracted features through these
processes are commonly used for pattern recognition to estimate the high-level inten-
tion of the subject or information of the desired joint state such as torque or position
in order to control wearable robotics[33].
To support a wide variety of different sEMG processing schemes in varied applica-
tions, the designed sEMG system provides a highly reconfigurable processing frame-
work while ensuring real-time operation robustly. Users will be able to construct
their own processing pipeline on the developed sEMG system. Infeasible processing
routine due to the heavy computational load will be reported back to users since the
system monitors its state continuously.

3.2 Design of RTOS for Embedded System

3.2.1 Necessity and Requirement

This section discusses the design and implementation of RTOS firmware architec-
ture for MCU. The purpose of the RTOS is to provide robust processing framework
for implementation of ideal DSP algorithms. Also, the RTOS is required to allow
the flexibility and reconfigurability of the post-processing data pipeline to optimize

63
the system on its application. To illustrate, Figure 3-10 shows an example system

integration scenario of the developed sEMG system in a complex wearable robotics

application.

f =2kHz f£=1kHz 1 = kHz

N
K Reconfigurable
Band Pass Filter Feature Extractor Additional Processing
(FIR / IIR) Envelope DetectorDyaiJon
- RMS MAV / LPF Dynamicioint
Sample Variable ~-N Model
Raw Reconfigurable 2 Domain Transfer N > 1
Signal Band - eFFT Pattern Recognition
Wavelet Transform - SVM
ADC (+ N60HzNotch) TD Features - eDA
- Zero Crossing
80~400Hz - Slope Sign Changes
- Variance Other Models
Custom Band - etc

Readftedata on the memory

(eg.extenalsensor valuetfor
closed-loop control)

Running Buffer Memory - Asynchronously log and hold every results of data processing
(e.g. Raw / Band-passed /nvelope / Some extracted features 4oint model output / etc...)

High Bandwidth Bus (USB / RS-485 /12C / SPI / UAR Digital High-Low) f..= IkHz
Each de ecan access all of the results from Iculation

(egBluetotI Data logge) (areading

20awZban-setohdsEatal ofsg jointmodelo
.kH utpu e.g exaa 50DW reading of multoleBG lure,
-rteoo

"eg.)"represents attrary usage scenario

Figure 3-10: Example utilization scenario of the developed sEMG system in wearable
robotics applications. The device isutilized to control a robotic ankle prosthesisvia
I2C protocoland t contribute highlevelcomputingontheSBCviaUSBwhileuser
is logging data on PCthrough Bluetooth.

In thisexample scenario, the sEMG signal is sampled with thefrequency of 2

kHz. The sampled sEMG signal is bandpassed and down sampled with the frequency

of 1 kHz. The down sampled signal is then utilized to extract specific features to

control a robotic ankle. These features can directly be used for control of hardware

or be further processed for complex pattern recognition on an advanced computing

platform. In Figure 3-10, the system is interfacing with three different hardwares for

different purposes: a Bluetooth device for data logging, a robotic ankle prosthesis

64
for walking, and an advanced computing platform for a high-level computation and

an off-line optimization. Each of these devices uses different type of communication

protocols and requires different types of data packets with different bandwidth. The

practical goal of designing the RTOS is to provide robust computation framework

that can handle the complex robotics application scenario such as shown one shown

in Figure 3-10.
With the limited computational capability of MCU, the RTOS firmware should

strictly control the timing of the computational processes, maximize the capabilities

of the MCU hardware peripherals, and monitor overall system operations for safety.

With this requirement, the RTOS firmware is designed to provide the following ca-

pabilities:

" Real-time processing pipelining with asynchronous downsampling capability

• Hardware timing control

" Flexible data buffering and I/0 managing

• Watchdog monitoring and error setting

The RTOS was implemented as multiple files of C-language based on the STM

hardware abstraction language (HAL) library.

3.2.2 Process Scheduling and Context Management

In order to provide a robust asynchronous processing framework, preemptive schedul-

ing of different computing threads is essential. Each of the computing thread should

have its own priority, and the RTOS should provide a simple and effective framework

to schedule this. Figure 3-11 shows a simplified scheduling implementation of the

designed RTOS.
The designed RTOS firmware provides a framework that can achieve the schedul-

ing scheme demonstrated in Figure 3-11. The RTOS allows users to set priority

for each of computing threads and schedule them to run in real-time with differ-

ent execution bandwidths. Within the provided framework, the users can customize

their cascaded processing pipeline with different required execution bandwidths. The

65
 0 ms 0.5 ms 1 ms 1.5 ms 2 ms 2.5 ms 3 ms

Computation Execution Execution

Block Priorit
Freq (Hz) Time (us) r Trigger

1 ADC Sample Post Processing 2k 51 -VPreemptive Processor Acquire

2 FIR band pass filtering (80~420Hz) 1k 224 Release Processor

S 3 Arbitrary Feature Extraction Process 500 1120 End of computation routine

This is one simplified &conceptual example usage case to show

how OS process multiple routine asynchronously

Figure 3-11: Example process scheduling and management scheme of the developed
RTOS. ADC sampling is running in the frequency of 2 kHz, bandpass filtering is
running in the frequnecy of 1kHz, and the feature extraction processing is running in
the frequency of 500 Hz.

RTOS allows easy down sampling of different types of post-processing to allow the
users executing complex computations while optimizing the hardware capabilities.
All of the scheduling is running based on hardware timer ensuring hard real-time
operation.
Also, in order to ensure robustness and safety while providing flexible reconfig-
urability of the system, the RTOS utilizes a hardware watchdog timer to monitor the
overall system bandwidth. If each of a processing thread is not running with required

bandwidth due to an overloaded computation, the system shuts down and lets the
users know about the situation through LED.

3.2.3 Memory Management

Effective memory management is also crucial in building the processing pipeline and
supporting versatile I/O. In general, several different types of sEMG post-processing

66
routines (bandpass filtering, fast Fourier transform, envelope detector, and others)
require an array of data with the given time window. Thus, constructing a data

processing pipeline with cascaded computing threads requires effective data manage-
ment scheme of each computational layer. Also, the importance of data management
is emphasized in MCU based embedded system where memory space and computing
power are both significantly limited. With these limitations, it is essential to opti-
mize between the usage of memory space and the computing power used in memory
management. The designed RTOS firmware provides an effective method to manage
a memory space for multiple and real-time sEMG post-processing algorithms. Figure
3-12 shows a memory management framework of the developed RTOS firmware.

Original Buffer (with size =6) Clone Buffer

Memory Space M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12

r _tq9 r-t10 I r_19 r-t 010

Buffer 1 r _t7 rt rt r 15 I r e I6 r - 7 r tJ rtBrt rjt5 r_
Raw EMG Signal - r_t9 rjl1 - - r_t9 r_t 0
r_13 - rt8, but index:3 I_ _
aw EMG n99-
r_t4 ~r_9, buiLndex:4 e0nsTpl=N

FlRR b_9 bit10 b1t9 bj1

e .,b_3~
-asda ~4
I b_B8, bu index:3
~9
EN
bubide: a baonW M t amp WW
g
or...anv
Ef naw anbuMWnd4x- b_6 b_1huJd'
Buffer 2
Band-Passed Signal fbj7 Ib8 bfb. bt5 bft6 b 7 5 fbt6
og~~ Feat EIdrU
°''"1~9 f_10 f~ t 19 f0 0-t5 i

ofbK~99 W tt LI f_110 L9 U1O et=

Buffer 3
Extracted Features

Buffer used to compute data data loaded

More Buffers
0 for next computation layer @ to19 IonNewthe buffer 0tt9
&Computing Layers 0 New data loaded
0 Buffer used to compute data
for next computation layer@ t=t10 on the buffer 0@tU10

Figure 3-12: Example memory management and buffering scheme of the developed
RTOS in real-time. The IIR bandpass filter uses the past six data points of raw and
bandpassed singals. The feature extraction process uses past four data points of the
bandpassed signal.

To describe Figure 3-12, each computation layer has its own memory space with a
size of at least twice larger than the required time windows for the next computation

67
pipeline. This memory space consists of an original buffer and a clone buffer located

next to the original buffer, and the clone buffer contains the same data in the original

buffer. After every computation, the result of the computation is newly stored on the

original buffer and the clone buffer updating the oldest data point. For each processing

cycle, each computational layer has its time index indicating the data point updated

lastly. Thus, by shifting memory space based on the time index, each computational

layer can access recent time-windowed data array without extra computing. The

computed output is stored in the memory space containing the oldest data. As the

data reached the end of the memory space, the following output is stored in the first

memory space since the first memory space containing the oldest data point. With

this cyclic buffering memory management scheme, the processor can avoid massive

copy and paste of data for shifting the array in real-time operation. Also, since the

RTOS of the sEMG system stores every computation result of each data processing

pipeline, users can access every layer of data which they require.

3.2.4 Hardware Peripheral Control

In designing RTOS for the embedded electronics hardware, the importance of interfac-

ing and utilizing hardware peripherals available on the processor is largely emphasized

in general. For high-bandwidth and real-time applications based on MCU, it is crucial

to off-load the required amount of computing from the MCU to available hardware

peripherals. Also, due to this nature of the system, the embedded RTOS should be

customized and optimized for the MCU and the electronics system. The developed

RTOS firmware was also developed with little compatibility with other embedded

systems in order to optimize available resources for the given electronics hardware.

The RTOS provides low-level interface drivers for control of hardware peripheral

ICs on the electronics. Also, the RTOS provides hardware communication protocol

interface drivers for available external I/O interfaces such as SPI/2C/UART/RS-

485/USB with direct memory access(DMA). This allows inter-device communication

possible with minimum processing power by letting hardware peripherals directly

accessing to the hardware memory space. The RTOS also activates MCU on-board

68
flash memory enabling users to have non-volatile memory for configuring and saving
the device setting. Moreover, the RTOS provides hardware timer controls for process
scheduling, system monitoring, and external triggering. The RTOS also provides LED
control functionality with hardware PWM peripherals for user interface.

3.3 User Interface Software

3.3.1 Graphical User Interface

Graphic user interface (GUI) software was developed to provide user convenience for
system integration and debugging. In detail, GUI provides visualization and recording
of the real-time sEMG data. Figure 3-13 shows the implemented GUI.
an-, ass-s
- Is..

'OtjDOA Typ* Ins K

* S
14-WH .1
O.5u5Th --
IDUI.SZ. k -5

2COSwA

Rud LowCwqm
mbdfu wIiT2 * S

CNWI
L4g0
W
sop.-
0-IS
I

Figure 3-13: Developed GUI for internal signal mo nitoring and debugging.

The GUI was developed based on LabVIEW language (LabVIEW2018b, National

Instruments). The GUI supports serial communication protocol on a computer, and it
can interface with either wireless Bluetooth bridge or on-board USB on the developed
sEMG system. Through this serial port, The GUI can visualize eight-channel sEMG

69
measurement in 1kHz bandwidth real-time depends on the bandwidth of hardware
communication protocol. The GUI can configure a generic setup of the developed
sEMG system and capable of recording the data in real-time up to the frequency of
1kHz.

3.3.2 Real-Time Network I/O

For the convenience of users and flexible integration with a high-level computational
controller, several stacks of real-time network I/O bridge was developed. These soft-
ware stacks allow users to connect real-time sEMG output signals to other pieces of
software algorithm including dynamic joint models or complex neural net model on
a computer or cloud-based environment.
For real-time SBC integration, SPI to TCP/IP bridge software was developed
based on C/C++ language. This bridge enables users to stream measured sEMG
data with full bandwidth (1kHz) to TCP/IP network socket layer. Also, USB to
TCP/IP bridge was developed based on python language for a network interface.
These interfaces are also capable of recording measured data in full bandwidth.

70
Chapter 4

System Evaluation

In this chapter, an evaluation of the manufactured sEMG system is presented. The

evaluation includes basic electrical specifications measurements, comparison with a
commercial sEMG workbench and in real-world applications. This chapter argues the
efficacy of the developed sEMG system.

4.1 Electrical Characterization

4.1.1 Differential Input Dynamic Range

The differential input dynamic range of the manufactured sEMG system was mea-
sured. A sinusoidal wave with a frequency of 100Hz and an amplitude of 800 mV,
was supplied to the manufactured sEMG system as a reference signal input. The mea-
sured signal was then recorded via a SBC-USB interface with a frequency of 1kHz.
Figure 4-1 shows the measured dynamic range.

Figure 4-1 demonsrates clear positive and negative railings from the input signal.
The RMS value of each rail is analyzed and compared with the design specifications.
Table 4.1 shows the comparison of designed and measured dynamic ranges.

The measured dynamic range shows a 5.23% increase over the designed value.
The dynamic range characteristics met the intended design requirements.

71
 Dynamic Range a 484.05mV
300

200

100

E
0

-100

-200

-300l
0 100 200 300 400 500
Time (ms)

Figure 4-1: Visualization of the dynamic range measurement setup. Sinusoidal signal
with the frequency of 100Hz the amplitude of ± 400mV clipped at its maximum rail.

Table 4.1: Measurement result of the dynamic input range of the developed sEMG
system.

Top Rail (mV) Bottom Rail (mV) Dynamic Range (mV)

Design 230.00 -230.00 460.00
Measured 243.20 -240.85 484.05

4.1.2 System Bandwidth

The bandwidth of the manufactured sEMG system was evaluated. To be specific,

the sampling and DSP frequencies were evaluated. A square wave with a frequency
of 100 Hz, an amplitude of 400 mV,,, and a duty of 50%, was supplied to the man-
ufactured sEMG system to evaluate the average system bandwidth. For bandwidth
measurement, the system is configured to sample an input signal with a frequency of
2kHz. The signal was measured for more than 30 minutes. The number of cycles of
the square wave was then analyzed along with the number of sampled points. Table
4.2 shows the measured system bandwidth.
Based on the measured result, it is clear that the hardware clock of the developed
system was properly driving the RTOS of the system. The error between measured

72
Table 4.2: Measurement result of the system bandwidth of the developed sEMG
system.

Specifications Value
Duration ~ 30 min
Reference Signal 100 Hz square wave
Number of the sampled points 3718000
Reference wave measured cycle 186118
Measured Sampling Frequency 1997.7 Hz
Intended Sampling Frequency 2000 Hz
Error in Sampling Frequency 0.115

%
and intended frequency is expected to be originated from the hardware clock jitters
from the function generator and the manufactured sEMG system.

4.2 Qualitative Comparison with a Commercial sEMG

System

In this section, a practical sEMG acquisition capability of the developed system was
evaluated. Specifically, the manufactured sEMG system was evaluated with the inter-
face of both standard Ag/AgCl and custom dry metal electrodes. In order to compare
the capability of the system, a state-of-the-art commercial sEMG acquisition work-
station was utilized as a reference equipment.

4.2.1 Comparison Measurement Setup

Reference Measurement System

The Refa-136 bio-potential measurement system (TMSi) was used as the reference
workstation for comparison. The electrical specifications of the Refa-136 are shown
in Table 4.3.

73
 Table 4.3: Specifications of the Refa-136 sEMG workstation.

Specification Value
System Refa-136 (TMSi) Benchtop system
RMS Noise < 1 uV
Dynamic Range ±150 mV
Max Sampling Frequency 2.048 kHZ
Input Impedance > 100 MQ
CMRR > 90dB
Electrode Wet Ag/AgCl
Cable Active shielded cable (DIN Connector)

Standard type snap Ag/AgC1 electrodes (HC124SG, Covidien) were used for 1)
the Refa-136 measurement and 2) the manufactured sEMG system with the Ag/AgCl
electrode setup.

Ag/AgC1 electrode interface

In order to compare the manufactured sEMG system with the Refa-136 system, stan-
dard Ag/AgCl electrodes (HC124SG, Covidien) and shielded snap electrode cable
were used with the developed system. This setup provided a comparable acquisition
setup with the Refa-136 system. In order to interface the electrode and the manu-
factured sEMG system, a robust physical interface pipeline was fabricated. The fab-
ricated pipeline includes custom-built miniaturized multi channel shielded cable and
3.5 mm jack shielded connector adapter. Figure 4-2 shows the fabricated Ag/AgCl
electrode pipeline including the electrode and the cable.
The fabricated pipeline provides a robust physical interface against mechanical
perturbation. Also, the pipeline provides electrical shielding up to the end of the
electrode driven by the developed system.

Dry electrode interface

A custom dry electrode was also used to evaluate the functionality of the manufac-
tured sEMG system. The manufactured sEMG system was designed with compati-
bility with dry electrodes such as metal or fabric types as discussed in Chapter 2. In

74
 Custom Built
8-Ch GND-shlelded Cable
a
EW

, 0O

)
Developed 3.5mm Connector
sEMG System Adapter

(a) (b) (c)

Figure 4-2: Evaluation setup for the developed sEMG system with Ag/AgCl elec-
trode. (a) Standard Ag/AgCl electrode used in the measurement. (b) Snap electrode
connector with 3.5 mm jack output connector. (c) The developed sEMG system con-
nected to the 3.5 mm jack connector adapter board via the custom shielded connector.

order to evaluate this compatibility, a custom metal dry electrode and a physical in-
terface pipeline were fabricated. Figure 4-3 shows the fabricated dry metal electrode
and the physical interface.

Custom Built Flexible

8-Ch GND-Ghlelded Cable Dry Electrode

GND Electrode

00 Developed
sEMG System
Flexible Dry Electrode
Adapter

(a) (b) (c)

Figure 4-3: Evaluation setup for the developed sEMG system with custom dry metal
electrode. (a) Custom flexible bipolar dry metal electrode surfaces. (b) Visualization
of the thickness of the custom electrode. (c) The developed sEMG system connected
to the flexible cable adapter board via the custom shielded connector.

The dry electrode in Figure 4-3 was designed and fabricated with consideration
of a specific application. Physical characteristics of the fabricated dry electrode are
shown in Table 4.4. The electrode was designed having a minimal thickness (80
pim) intended for use in lower limb active prosthesis research in the future. The

75
electrode enables sEMG acquisition in real-time while wearing a load-bearing standard
prosthesis socket. With further testing and development, the fabricated custom dry
electrode will be used in lower-limb active prostheses applications such as dynamic
walking and running.

Table 4.4: Specifications of the custom dry metal electrode.

Specification Value
Electrode Type Bipolar
Electrode Diameter 10 mm
Electrode Surface Gold Coating
Electrical Connection Copper Layer
Base Material Polyimide (Flexible)
Thickness 80 pm

With the fabricated custom shielded cable and the flexible cable adapter, a ro-
bust physical connection between the flexible dry metal electrode and the designed
electronics was established. The flexible electrode was designed for extremely low-
profile, and thus, it lacks electrical shielding capability as an engineering tradeoff of
low-profile characteristics. The electrode with dry metal contact and lack of shield-
ing capability provided difficult conditions for the developed electronics. Thus, this
setup provided a perspective on the general electrode compatibility of the developed
system.

Comparison Condition Formulation

Comparing more than two bio-signal acquisition devices is not a trivial process. Al-
though a comparison of nominal electrical specifications would provide a raw per-
spective, the isolated equipment evaluation paradigm does not provide a thorough
picture. Bio-signal acquisition is a complicated process involving a human body,
complex physical interfaces, an acquisition hardware, and a data-logging and pro-
cessing framework. For a thorough evaluation of the whole framework, it is crucial to
evaluate based on acquired data from a human subject rather than only comparing
nominal specs.

76
 Unfortunately, acquiring equivalent bio-signal is not a straight forward process.
This is because different equipment cannot share the same electrode output due to
the change of impedance of an electrode as a device added. As devices are added on
the same electrode, the overall acquisition capabilities of both systems are expected to
be degraded, and thus, it is impossible to evaluate the performance them. However,
accessing a different electrode on an equivalent muscle also gives a different result.
The voltage output of the electrode can widely be varying based on an attached
position. Due to these reasons, comparing the sEMG equipment based on biosignal
acquisition should be done in the context of qualitative analysis.
For qualitative analysis, bipolar electrodes for both system (Refa-136 and the
developed sEMG system) were attached on a Tibialis Anterior muscle of a subject.
The data was recorded for two sessions, one session for the Ag/AgCl electrode with the
manufactured sEMG system and the other session for the custom dry metal electrode
with the manufactured sEMG system. Figure 4-4 shows the electrode placement for
both sessions.

Portable System Portable System

GND GND

TMSI Refa-136 TMSI Refa-136

GND GND

Portable System
Input "UCustom Dry ....
Electrode

TMSI Refa-136 ..
Input TMSI Refa-136
Input

(a) (b)

Figure 4-4: Simultaneous sEMG measurement setup of the developed sEMG system
and the Refa-136 system on a same muscle (Tibialis Anterior) with a different elec-
trode position for each system. (a) The setup with the Ag/AgC electrode connected
to the developed sEMG system. (a) The setup with the custom dry metal electrode
connected to the developed sEMG system.

For each measurement setup shown in Figure 4-4, the sEMG signal was recorded

77
simultaneously with the Refa-136 equipment and the manufactured sEMG system.
Table 4.5 shows the simultaneous data recording setup for both equipment.
Table 4.5: sEMG measurement setup for comparison.

Conditions Refa-136 Developed sEMG system

Sampling Frequency 2048 Hz 2000 Hz
Recorded Signals Raw Raw, Bandpassed, Envelope
DSP Execution Offline analysis Onboard DSP

Shielding Setup Active-shield GND-shield (Ag/AgCl Electrode)

None (Dry Electrode)

For the post-processing pipeline of an sEMG signal, bandpass filtering of the raw

signal followed by envelope extraction via time-windowed RMS was chosen. Since

the sampling frequency of the two devices is slightly varied, the filter for each sys-

tem is designed separately with the same design specifications. Table 4.6 shows the

specifications of the designed bandpass filters for the two equipment.

Table 4.6: Bandpass filters for the comparison of the Refa-136 system and the devel-
oped sEMG system.

Specifications Value
Stop Frequency 1 (Hz) 50
Pass Frequency 1 (Hz) 80
Pass Frequency 2 (Hz) 450
Stop Frequency 2 (Hz) 480
Stopband Attenuation (dB) 80
Design Method Generalized Equiripple
Filter Order 1 for the Reference System (w/ F, = 2048 Hz) 154
Filter Order' for the Developed System (w/ F, = 2000 Hz) 152
1. Filter order: The number of coefficients in the filter. Roughly it implies required number of
multiplications and additions for generating one output.

The filter specifications were chosen with consideration of practical usage in the
future. The digital filters were designed on MATLAB R2017b (Mathworks). Figure 4-
5 shows the designed filter for the two equipment with different sampling frequencies.
For envelope detection using the time-windowed RMS feature extraction, the input
signals were down sampled with a prescaler of two resulting in the bandpassed signal

78
 Filter Magnitude psonse
100
-- -Fs=2048

0 -s20

-200-

-300

-400 I
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Filter Phase Response
F1=200

1500

-00

0 100 200 300 400 500 600 700 8 900 1000

Frequency (Hz)

100 Filter Group Delay Response

FS=2048
80 - FS=2000

*60

s40

020

0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

Figure 4-5: Magnitude, phase, and group delay responses of the digital bandpass
filters for the two sEMG meausurement equipment. Due to the sampling frequency
differences among two devices, the two filter shows minutely different responses.

with a sampling frequency of either 1024 Hz (Refa-136) or 1000 Hz (manufactured

sEMG system). These input signals were fed into an RMS filter with 200 ms time
window.

All post-processing results of the manufactured sEMG system were executed on-
board. The processed signals (raw, bandpassed, and envelope) were recorded via
SBC-USB interface with the frequency of 1 kHz. In the Refa-136 system measure-
ment, post-processing of the signal was executed on offline (MATLAB2018b, Math-

79
works) after recording data. This is not because the system is inferior, but because
the purpose of the equipment being investigational research equipment to allow re-
searchers accessing multi-channel true raw data for varied off-line post-processing.
For the synchronized measurement of the two systems, a digital trigger signal was
utilized.

4.2.2 Time Domain Signal Evaluation

In this subsection, recorded sEMG datasets from the Refa-136 equipment and the
developed system were analyzed. Recorded time domain datasets were analyzed qual-
itatively to evaluate the overall behavior of the manufactured sEMG system. For the
Refa-136 system, the post-processed resultant signal was processed offline. For the
manufactured sEMG system, all the post-processed signal was generated on the sys-
ten in real-time. Since the sEMG signal for each device was measured from different
electrodes, direct comparison of the quantitative value is not an effective measure to
compare two systems quantitatively. Only RMS peak-to-peak noise was evaluated
quantitatively. As stated above, the measurements were separated in two recording
sessions with the different electrode (the Ag/AgCl electrode and the custom dry metal
electrode) interface setup for the manufactured sEMG system. For each recording,
the datasets were consists of 30 seconds of data, and a subject was resting for at
least first and last 5 seconds. The RMS peak-to-peak noise of the bandpassed signal
was evaluated within the first and last 5 seconds of the time domain datasets. Each
measurement dataset from each recording session was analyzed separately.

Evaluation of the manufactured sEMG system with wet electrode interface

The recorded time domain signal from the Refa-136 sEMG workstation and the man-
ufactured sEMG system with standard Ag/AgCl electrode is shown in Figure 4-6.

80
 sEMG Measurement Comparison
Ag/AgCI Electrode Setup
2000
-- Reference
> 0

-2000

-4000
0 5 10 15 20 25 30

2000

1000
(I,
0

-1000

-2000
0 5 10 15 20 25 30

600

400

X200

0
0 5 10 15 20 25 30

'0.5

0
- ~AM

0 5 10 15 20 25 30
time (s)

Figure 4-6: Measured raw and post-processed sEMG signals from the Refa-136 equip-
ment and the manufactured sEMG system with Ag/AgCl electrode.

The raw signal has a different differential DC offset since each equipment interfac-
ing with the different electrode on the surface of the same muscle (Tibialis Anterior)
of the subject. Thus, the tendency of the signal should be similar, but the value of
the signal cannot be identical. While having different DC offsets, two raw signals

81
show largely identical activation patterns. With post-processing of the signals in-

cluding bandpass filtering, time-windowed RMS extraction, and RMS normalization,

the equivalent patterns of the measured signals are increasingly emphasized. This

measurement confidently implies that the developed system is capable of measuring

and processing sEMG signal at least with standard Ag/AgC electrode.

Within the recorded signal, the RMS noise was evaluated as shown in Table 4.8.

Based on the noise level, the developed system was capable of capturing the raw

sEMG signal effectively up to the fidelity that the post-processing capability of the

system can cancel the noise effectively. However, this noise level does not provide

an absolute comparison metric, and it should only be interpreted as a qualitative

measure to evaluate the overall capability of the developed system. Although the

level of noise argues that the system is capable to the sEMG signal in real-time, the

value does not imply much due to the strong attenuation from the designed bandpass

filter.

Table 4.7: Measured baseline noise for the comparison of the Refa-136 system and
the developed sEMG system with the Ag/AgC electrode.

Reference Workstation Developed System

Physical Interface Active-Shielded Cable GND-Shielded Cable
Electrode Ag/AgCl Ag/AgCl
Measured RMS noise (pVp) 1.3379 0.5308

Evaluation of the manufactured sEMG system with dry electrode interface

The recorded time domain signal from the Refa-136 sEMG workstation and the de-

veloped system with the custom dry metal electrode is shown in Figure 4-7.

The DC offset of the raw signal measurement from the developed system drifted

largely compared to the raw signal from the measurement with Refa-136 equipment.

This likely due to the varying mechanical contact pressure of the skin and the electrode

surface during the measurement. Yet, this low-frequency drifting can be easily filtered

out with digital post-processing. The post-processed sEMG data shows an equivalent

activation pattern with the reference measurement signal with a minutely attenuated

82
 sEMG System Measurement Comparison
Dry Metal Electrode Setup
5000

(U
-5000 - Reference
Dev - Dry Metal

-10000 30
-- 5 10 15 20 25

2000

1000
CD
0 0

-1000
C

-2000 30
0 5 10 15 20 25

600

400
C,,
200

0
0 5 10 15 20 25 3C

Co

0.5-

I
z
-

0t 25 30
0 5 10 15 20
time (s)

Figure 4-7: Measured raw and post-processed sEMG signals from the Refa-136 equip-
ment and the manufactured sEMG system with custom dry metal electrode.

signal amplitude. This attenuation is expected to be originated from 1) impedance

ratio of skin/electrode and the AFE changes and 2) different electrode spot with
actual different voltage generation. Nonetheless, the overall activation pattern of
the post-processed signal shows a high correlation between the measured signal from

83
the Refa-136 system and the measured signal from the manufactured sEMG system.
This demonstrated the capability of the manufactured sEMG system to interface with
different types of dry electrodes.
Within the recorded signal, the RMS noise was evaluated as shown in Table 4.8.

Table 4.8: Measured baseline noise for the comparison of the Refa-136 system and
the developed sEMG system with the custom dry metal electrode.

Reference Workstation Developed System

Physical Interface Active-Shielded Cable None-Shielded Cable
Electrode Ag/AgCl Dry Metal
Measured RMS noise (pV,,) 1.3486 0.7625

The measured RMS noise implies that the system is also capable of interfacing
with several types of dry electrodes for sEMG measurement qualitatively.

4.2.3 Frequency Domain Signal Comparison

The recorded signals from both measurement sessions were also evaluated on the
frequency domain. The frequency domain analysis can provide clear insight into the
manufactured sEMG system's capability and the noise characteristics.

Evaluation of the developed system with Ag/AgCl electrode interface

Figure 4-10 shows the power spectrum analysis of the raw and bandpassed signals on
the first session.

84
 Overall Power Spectral Density, AgIAgCI Electrode Setup
1
121

10 Raw, Reference
1-Raw, Dev-Ag/AgCIE
- Bandpassed, Reference
8 - - - Bandpassed, Dev-Ag/AgCIE

> 6

4
0
2

100 20 300 400 500 600 700 800 900 1000

N
z0
C%1

-20
0
a
U)o-40
0M.

-60
100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

Figure 4-8: Power spectral density analysis of the dataset from simultaneous measure-
ment of the Refa-136 device and the manufactured sEMG system with the Ag/AgCl
electrodes.

Based on Figure 4-10, overall characteristics of the power spectral density of the
developed system showed largely equivalent characteristics of the power spectral den-
sity of the Refa-136 sEMG workstation. The difference in scale was originated from
the difference in scale on time-domain signals. For noise characterization of the setup,

low-frequency PSD of raw signals was analyzed in the figure 4-9.

85
 LowFmauencvNoisa.AaIAaCIElactrodsSotun

Raw, Reference
N15 Raw, Dev-Ag/AgCIE

>10

c05

2 4 6 8 10 12 14 16 18 20

N
20
10
0-

-10
-

CO
-20
2 4 6 8 10 12 14 16 18 20
Frequency (Hz)

Figure 4-9: Low-frequency power spectral density analysis of the dataset from simul-
taneous measurement of the Refa-136 device and the manufactured sEMG system
with the Ag/AgCl electrodes.

In Figure 4-9, the overall low-frequency noise pattern of the developed system with

Ag/AgCl electrode is minutely smaller than the reference system setup. This result

is expected due to the input reading scale difference caused possibly by differences in

electrode position or amplifier impedance, but the result does not necessarily indicate

that the developed system is superior to the reference system. Nevertheless, this

result implies that the developed system is designed with a comparable capability to

one of the state-of-the-art sEMG workstation qualitatively.

Evaluation of the system with dry electrode interface

The figure 4-10 shows the power spectrum analysis of the recorded signals on the

second session.

86
 Overall Power Spectral Density, Dry Metal Electrode Setup
12
Raw, Reference
10 Raw, Dev-MetalE
--- Bandpassed, Reference
8 - --- Bandpassed, Dev-MetalE
6

C 4
0-
2

0 || | 1
100 200 300 400 500 600 700 800 900 1000

I
20 I I

I F-i

Cf) -40

-60
100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

Figure 4-10: Power spectral density analysis of the dataset from simultaneous mea-
surement of the Refa-136 device and the manufactured sEMG system with the custom
dry metal electrode.

In Figure 4-10, the developed system with dry electrode shows a comparable
response to the reference system after bandpass filtering. For raw data, low-frequency
power rose around the frequency range of lower than 10 Hz. Figure 4-11 amplifies the
low-frequency component of the raw signal.

87
 Low Frequency Noise,.Dry Metllcpoeeu
20
Raw, Reference
15 Raw, Dev-Ag/AgCIE

10

05
0-
0
2 4 6 8 10 12 14 16 18 20

N
;E20
10
0

-10
-20
2 4 6 8 10 12 14 16 18 20
Frequency (Hz)

Figure 4-11: Low-frequency power spectral density analysis of the dataset from si-
multaneous measurement of the Refa-136 device and the manufactured sEMG system
with the custom dry metal electrode.

The higher power of the measurement from the developed system with dry metal

electrode interface is visible around the low-frequency region. This is suspected due
to the lack of shielding and DC-drifting caused by electrode contact perturbation.
With proper filtering, the developed system shows comparable signal quality after
bandpass filtering. This justifies that the manufactured sEMG system was properly

designed satisfying the compatibility with varied types of electrodes.

4.3 Utility Evaluation in Robotic Prosthesis Appli-

cations

In this section, three real-world applications are discussed to show the efficacy of

the designed sEMG processing platform. One case shows the sEMG recording in

dynamic walking while wearing a robotic prosthesis ankle. The second case shows

the climbing ankle prosthesis system controlled by manufactured sEMG system. The

88
third application demonstrates high-bandwidth data logging with motion labeling for
a future pattern recognition research.

4.3.1 Dynamic Measurement Interface for Prosthetic Socket

For applications using a lower-limb robotic prosthesis, it is crucial to access muscles

of residual limb inside a weight loaded socket. Due to a significant pressure level
inside a weight-bearing socket, it is always challenging to access to the residual limb
inside the socket. Any materials inside a lower-limb socket and a liner should be
extremely low-profile in order to preserve a level of comforts of a subject. Thus, in
order to measure sEMG signal inside a weight-loaded socket, a specialized liner with
embedded fabric electrodes and an external connector was utilized. The liner was
manufactured in Ottobock, Inc. Figure 4-12 shows the fabricated sEMG liner.

R k1

(a) (b) (c) (d)

Figure 4-12: Custom prosthetic liner (Ottobock, Inc) with integrated fabric electrode
for sEMG measurement. (a) Overview. (b) Electronics connector. (c) Electrodes
located around calf area. (d) Ground electrode located around kneecap area.

The electrode placement inside the liner was customized for each subject. The
electrodes were placed around arbitrary representative musculature areas on the resid-
ual limb. The liner contains eight bipolar electrodes and one ground electrode inside
the liner. It contains Picoclasp (Molex, Inc) miniaturized connector under the prox-
imal side of the liner. In order to access the connector, a specialized carbon fiber

89
 _4

socket was manufactured with a hole around the connector area. Figure 4-13 shows
the sEMG liner connected to the proposed sEMG platform while mounted on the
socket.

(a) (b)

Figure 4-13: The manufactured sEMG measurement system mounted on the socket
with the sEMG liner for dynamic sEMG acquisition in lower limb robotic prosthesis
research.

As shown in Figure 4-12, the connector on the liner is connected to the sEMG sys-
tem through the custom-built sEMG cable. Each bipolar channel consists of twisted-
pair connection. The cable is wrapped with metal outside and shielded with GND-
shield scheme. This shielding scheme protects the sEMG signal from noise while
minimizing the required volume.

Since the purpose of fabrication of the liner was to prove the efficacy of the man-
ufactured sEMG hardware, not all aspects of liner are designed ideally. Specifically,
the miniaturized connector is not robust against vibration and shock. Due to these

90
reasons, partial data in the result section shows unexpected noise when the connector
contains mechanical shocks resulting in an unstable electrical connection.

4.3.2 Analysis of sEMG Signal in Walking

The fabricated sEMG liner was used to record sEMG signal while a subject is walking
on a powered ankle prosthesis, EmPower (Ottobock, Inc). Figure 4-14 shows an
example usage case of the manufactured sEMG system while the subject is using the
EmPower system.

Figure 4-14: Usage case of the developed sEMG system with the EmPower powered
ankle prosthesis[34].

A computed envelope of the bandpassed sEMG signal has been recorded in 100
Hz while the subject was walking on a level ground. Table 4.9 shows the detailed
experimental setup for data recording.
Figure 4-15 shows the recorded envelope data of sEMG signals while the subject
was walking on a level ground with the powered prosthetic ankle.
The data shows about 40 seconds of recording, and it is visible that the subject
is walking between 3s to 11s and 25s to 40s. Figure 4-15 also visualizes magnified
signal view between the time of 27s to 33s. This magnification shows the repetitive
pattern of the sEMG signal which largely synchronizes with the subject's walking

91
 Table 4.9: sEMG measurement setup for the walking trial.

Condition Value
Electrode Dry fabric electrode on the sEMG Liner
Number of Channel 8
Raw Sampling Frequency 1 kHz
Bandpass Filter Design Method Minimum-phase Equiripple FIR
Passband Frequency 80 ~ 400 Hz
Stopband Attenuation 80dB
Envelope Detection RMS with time window of 200ms
Data Logging Interface PC GUI via UART Bluetooth
Data Logging Frequency 100 Hz

phase (stance and swing phase).

While the data was not recorded, the sEMG system was also utilized to control
and to modulate the behavior of the EmPower ankle. The system was interfacing with
the EmPower ankle through UART communication with baudrate of 115200 bps. The
intensity of the power plantarflexion on the late stance phase was modulated based
on the average activation of muscles around the calf area.

4.3.3 Control of Climbing Prosthesis System

The manufactured sEMG system was utilized in the research of a neurally-controlled

climbing ankle prosthetic system[35]. The goal of this system is to volitionally control
2-Degree-of-Freedom robotic ankle with high-precision joint position to augment a
subject's ability to climb. The system is comprised of many sub-systems shown in
Figure 4-16.

Figure 4-17 shows the deployment cases of the climbing prosthesis system in the
real world.

The climbing prosthetic system was implemented based on the assumption that a
subject of the system had an experimental amputation surgery, Agonist-Antagonist
Myoneural Interface(AMI)136][37]. Preliminary research regarding this surgery showed
that it significantly improves the preservation of a proprioceptive sensation of a phan-
tom limb after amputation compared to a traditional amputation surgery. Current

92
 8-Channel EMG Ignal
-- CH1
120 ~ CH2
Ca
cia
100
ca
-

- 07
2c3
so
-

20

0
-

0 5 10 15 20
time (s) I I

..- • - - Time domain expansion

--- CH1
120 CH2
CH3
CH4
CH5
100 -CHO
-CH7

404
so-

20

02-a-04
27, * 2q :
29 0 31: 32 33
time (s)

SW' ST 'STSW' ST 'SW ST SW ST SW ST SW ST

S-- STANCE PHASE 4 SWING PHASE

Figure 4-15: Measured sEMG signals from the walking trial.

research aims to evaluate the efficacy and effect of the surgery. The subject of the sys-
tem had two AMI pairs for each degree of freedom of ankle joint and subtalar joint:
Tibialis Anterior and Lateral Gastrocnemius for ankle joint and Peroneus Longus
and Tibialis Posterior for subtalar joint[36]. The sEMG signals of these muscles then
utilized to control the mechatronics system.

93
 Agonist-Antagonist Embedded EMG Dynamic Ankle Climbing Prosthetis
Myoneural interface (AMI) Acquisition Platform Joint Model Ankle Mechatronics
I Nil -W--r(F, -F,) -BO- K

Regeneration of proprioceptive sensation Embedded EMG Platform EMG as an iput signal High-load capability and stability
Eablin control of musclesignal EMGlProthetlcLner State DoFMotion

Figure 4-16: Conceptual block diagram of the robotic climbing ankle system.

(a) (b)
Figure 4-17: Usage cases of neurally-controlled robotic climbing ankle system in real-
world. (a) Captured from 1341. (b) Climbing data measurement trial.

A custom 2-DoF climbing ankle mechatronics system was designed with the em-
phasis on light-weight and low-power characteristics[351. With two custom non-
backdrivable actuators, the ankle can adjust to a neurally controlled position while in
an unloaded state. When the ankle is loaded by weight, the actuators lock the ankle
position and bears loaded weight with minimal power consumption.

In order to control the ankle mechatornics system, the sEMG liner and the man-
ufacutred sEMG system were used to acquire the sEMG signals from the four muscle
groups (Tibialis Anterior, Lasteral Gastrocnemius, Peroneus Longus, Tibialis Poste-
rior). A second-order dynamic joint model[36][38][39] was utilized to interpret esti-
mated position of phantom limb based on the sEMG singals. Two joint models were

94
utilized for the ankle and subtalar joints, and the models were tuned in heuristic
basis. The joint model runs on the frequency of 1kHz on the motor driver embedded
system on the ankle mechatronics. The sEMG system bandpassed the sEMG signal,
estimated %MVC using the ratio of the calculated envelope by applying mean abso-
2
lute value extraction, and streamed this signal via C communication protocol. The
detailed system configuration is shown in Table 4.10.

Table 4.10: sEMG measurement setup for the climbing trial.

Condition Value
Electrode Dry fabric electrode on the sEMG Liner
Number of Channel 4 (on muscles: LG 1 TA2 /PL 3 /TP 4

)
Raw Sampling Frequency 1 kHz
Band-Pass Filter Design Method Equiripple FIR'
Pass-band Frequency 80 ~ 320 Hz
Stop-band Attenuation 80dB
Envelope Detection MAV 6 with time wi ndow of 120ms
Mechatornics Interface I2C
Data Logging Frequency 500 Hz
1. LG: Lateral Gastronemius.
2. TA: Tibialis Anterior.
3. PL: Peroneus Longus.
4. TP: Tibialis Posterior.
5. FIR: Finaite Impulse Response filter.
6. MAV: Time-windowed mean of average value extraction filter.

With the system setup described above, an experiment was conducted to evaluate
the practical efficacy of using active climbing prosthesis compared to passive prosthesis

[35]. Figure 4-18 shows a subset of recorded sEMG dataset of four muscle groups while
the subject was climbing.
Moreover, Figure 4-19 shows the joint position outputs calculated based on dy-
namic joint models with %MVC inputs from measured sEMG signals.

4.3.4 Synchronized Motion Data Labeling

The system was also utilized to collect datasets for a preliminary study of free-space
joint control based on multi-channel sEMG signal. A subject with transtibial am-

95
 1 1000 i ii
500

-
0 2 4 6 8 10 12 14 16 18
200

100
0
0 2 4 6 8 10 12 14 16 18
'100
50
-J
0 0
0 2 4 6 8 10 12 14 16 18
'100 1

50
0
0 2 4 6 8 10 12 14 16 18
tme (s)

Figure 4-18: Measured sEMG signals from the climbing trial. Extracted envelop
feature of the meausred sEMG signals are presented.

putation wearing sEMG liner mapped the intention to generate 2-DoF directional
torque of ankle on a joystick. The system comprised of the developed sEMG system
and SBC. The sEMG system streamed bandpassed sEMG signal to SBC with the
frequency of 1kHZ. The SBC recorded the joystick output and the sEMG signals
simultaneously in 1kHz. Detailed system configuration is shown in Table 4.11.

Table 4.11: sEMG measurement setup for the motion labeling trial.

Condition Value
Electrode Dry fabric electrode on the sEMG Liner
Number of Channel 8
Raw Sampling Frequency 1 kHz
Band-Pass Filter Design Method Equiripple FIR
Pass-band Frequency 80 ~ 320 Hz
Stop-band Attenuation 80dB
Data Logging Interface SBC-SPI
Data Logging Frequency 1 kHz

Figure 4-20 shows the subsets of the recorded data during the trials.

96
 :i LG

PL
0.5

0
0 2 4 6 |8 ' 10 12 14 16 18
0 2 4 6 :8: :10::: 12 14 16
10

LL
0 -10 5 5 a ems

-20
8

4
0 2 4 6 a
8:a 5
10::
S 55
12 14 16 1
*

0a2 a6 8 |1 al| 121a1

* a me (s |a|
* a a a amI
I m (g) .I
* I S I SB

8
-a i i it la I

I I B I II

Free Space Weight Loaded

Adjustable Ankle Position Ankle Position Locked

Figure 4-19: Measured joint positions actuated based on the estimated %MVC signals.
The joint positions were changing when the prosthesis is in free-space state.

97
 1000
CH1
500
CH4
CM 0 CH7
> -500
CH8

-1000
0 5 10 15 20 25 30

F.
s0.5

0
FI
,
-0.5 X axis - subtalar
Y axis -anE
-1
0, 10 15 2253
0 5 10 15 20 25 30
ime (s)

(a)

1000

500

-500
0

"
III
CHI
CH2
CH3

- CH5
0 20 40 60 80 100 120 CH6
CHT
ICH8

0.
-0.5

0.5
z -a
nW~i YaxJ
-11
0 20 40 60 80 100 120
time (s)

(b)

Figure 4-20: Measured sEMG signals from the motion labeling trial. Bandpassed
sEMG signals were recorded with joystick input signals simultaneously.

98
 The RMS noise level evaluated on the dataset from a timestamp of 0 to 5 seconds
shown in Figure 4-20a was 1.5701 uV. Considering that the shown data is the data
from the full measurement system pipeline, the electronics functions as intended.
Although the recorded data does not provide accurate kinematics of the phantom
limb joint position nor dynamic torques of the phantom limb, the high bandwidth
datasets labeled with estimated intentions have values in off-line analyses for prelim-
inary research.

99
100
Chapter 5

Discussions

5.1 Thesis Contributions

This thesis presents the design of an embedded sEMG acquisition and processing
platform specialized for wearable robotics applications. The presented design in-
cludes the design of the electronics hardware, digital filters, real-time operating sys-
tem, and external interface softwares. This thesis analyzed the design requirements
of every component of the sEMG system and provided one functional design for
each component. All components were custom designed, developed, and manufac-
tured. The manufactured sEMG system was then evaluated against a commercial
sEMG system and with different real-world applications. Compared to a commercial
sEMG measurement equipment, the developed sEMG system demonstrated compa-
rable functionality. In the real world deployments, the system was successful and
played the intended roles in different types of applications such as walking and climb-
ing. High-level requirements of the sEMG processor design include the following:
1) robust signal acquisition with low-noise, 2) portable form factor, 3) flexible and
reconfigurable signal processing pipeline, 4) robust real-time operating system, and
5) flexible external interfaces. Through real-world tests and deployments, the system
demonstrated the capability satisfying the high-level requirements and showing the
efficacy of the design.

101
5.2 Future Work

Future work includes a hardware design revision of the electronics. Although the core
hardware architecture was qualitatively proven with real-world applications, some
of the interfaces show a few aspects that can be improved. Specifically, the analog
interface connector could be changed to improve robustness against physical pertur-
bations. On top of the connector change, increasing the number of channels of sEMG
input and introducing controller area network communication protocol (CAN) as an
external interface are currently being considered. Increasing computational capacity
by upgrading the main processor is also currently being considered.
With further design iteration of the hardware and the software interface devel-
opment, the designed system is expected to be easily utilizable in different types of
wearable robotics applications. All of the hardware and software designs will be open-
sourced after thorough design evaluation in near future. The author's hope is that
the system will contribute to the wearable robotics research field by enabling faster
integration of sEMG based control.

102
Appendix A

Hardware Schematics

103
104
 2 3 4

based preampifi

DNS

+2V51 B
C87A
R71A GNDI
VINNA 10n
U 4.99K 0 1OOnF
UIIA
Vin-

+
RGA)2RG > 7 R72A-
Vout I

INPA'
i eREF G
RG oni 4 RG ,4.99K
Vin+ >
8422BRMZ

VINPAC88R,7,4,A
4,99K
1(znF
-2V-51

DNS

Disable preamp by GAIN: G= 1+19.8k /Rg

.-deleting 4.99k on Vm-n, Ym;+, Vout REF
- adding 4.99kInputmpednce:ZOG1b1/2p
on two DNS node use Rg=2.2k, G= 10

Preamplifier
AD8422

Use Gain 10 (for permitting DC offset of 300-500mV)

CMR:llI4dB (6011z), 95dB (95Hz) @gpin10o
Input Bias Current : 0.5pA max
Input Impedance: 200GOhm //2 pF

_A82.;c c de, hLab- E4-27

Title DNS EMG 8ch ADS1299_InputPreampAD8422 E14-274
Size: Letter Number:.I Revision: 7Ae 39 met7
I Cambhridge. MA02139 I , 1, a6dm
Date: 8/7/2019 Time: 3:43:44AM | Authod SeoUgHoYeon USA lb
File: DNS EMG 8ch ADS1299 InputPreamp AD8422.SchDoc
1 2 3 4
 I I
I 2 3 4
2 3 4

bsdp mlifier

R70B
DNS

+2V51 B
C87B

VNB R71 B -1 GNDI

4.99K 10nF
UIIB
II Vin- -+
R~BD 2 RG > 7 R72B
Vout IN

REF INPB)
RB ) RG ,4-99K
4Vin+>
UllB
8422BRMZ
R74B C88B

4.99K 100n
-V51

R75B
C
DNSi

Disable preamp by GAIN: 0- 1+19.8k/Rg

-deleting 4.99k on Vin- Vin+, Va, REF
- adding 4.99k on two DNS node use Rg -2.2k, G- 10

Preamplifier
AD8422

Use Gain 10 ( for permitting DC ofihet of 300-500mV)

CMRR: 114dB(60Hz), 95dB (95Hz)@ gain 10
Input Bias Cuent: 0.SpA max

Input Impedance: 200GOhm //2 pF

Tide DNS EMG 8ch ADS1299InputPreampAD8422 c "e,"'a-

E/-274
Size: Letter Number:.2 Revision: 75Am eM2139 Srensd
Date: 8/7/2019 Time: 3:43:44 AM Authod Seofi Ho Yeon USA ik
File: DNS EMG Sch ADS1299 InputPreamp AD422.SchDoc
1 2 3 4
 2 3 4

IA based preamplifier

R70C
DNS

+2V51 B
C87C
R71C GNDI
VINNC)
4.99K 0 OOnF
U11C
Vin-

+
RGIC )2 RG7 R2
Vout |INNC
6
RG2C n )+ RG 4.99K
4Vin+>
8422BRMZ

VINPC )88
G 4DI1
3 REERQC
100nF
-2V51

4.99K.9otoD~oe DNS s~=,2cG1

Disable preamp by GAIN : G= 1+19.8k /Rg

- deleting 4.99k on Vin-, Vint+, Vout, REF
- addng 4.99k on two DNS node use Rg=2,2k G= 10

rPreamplifier
|AD8422

|UseGain 10 ( for permitting DC offset of 300-500mV)

CMRR: l14dB (60Hz), 95dB (95Hz) @ gain 10
Input Bias Current: 0.5pA max

Input Impedance: 200GOhm //2 pF

ehalronics
Title DNS EMG 8ch ADS1299_InputPreampAD8422 c'""ediaLah-E14-274

Size: Letter Number:.3 Revision: 75Anherst Street3

Sie Cambridge,MAV02139 nieMb
Date: 8/7/2019 Time: 3:43:44AM Authod SeolgHoYeon USA
File: DNS EMG Sch ADS299 InputPreamp AD8422.SchDoc
2 3 4
I 2 3 4
2 3 4

IA based premplifier

R70D
DNS

+2V51 B
C87D
R7ID GNDI
4.99K U 1lD

)2 RG > 7 R7D
Vout |IN
6
3REF'''.IP

)
| RG2 RG ,4.99K
ViD+ >
A8422BRMZ

VINPD )-- G 4DI

R74D 100nF
C88D__

DNS

Disable preamp by GAIN :G 1+19.k /Rg

-deleting 4.99k on Vin-, Vin+-, Vout, REF
-adding 4.99k on two DNS node use Rg2.2kG 10

Preamplifler
AD8422

Use Gain 10 (for pemitting DCoffset of 300-500mV)

CMRR : l4dB(60Hz). 95dB (95Hz)@ gain 10
Input Bias Current: 0.5pA max

Input Impedance: 200GOhm //2 pF

Title DNS EMG 8ch ADS1299_InputPreampAD8422 c ed 'ih-E14-274

Size: Letter 75 A merst Street Mit
IizeNumber:.4
Revision:

Date: 8/7/2019 Time: 3:43:44AM Authosl SeogHoYeon

Cambridge,.M 02139 lonbd
USA
File: DNS EMG Sch ADS1299 InputPreamp AD8422.SchDoc
1 2 3 4
 2 3 4

Abased preamplfi

R70E
DNS

+2V51 B
C87E
R71E GNDI
4.99K 100nF
UllE
UIIE
IVin-

+
R~E)2 RG 7 R72E
Vout 'NN
6
3REF W.|IP)
RG2E44 RG ,49K
Vin+>
8422BRMZ
R74E C88E
VINPE )- - G 4DI
4.99K 100nF
-2V51

DNS

Disable preamp by GAIN: G= l+19.8k/Rg

- deleting 4.99k on Vin-, Vin+, Vout, REF
- adding 4.99k on two DNS node use Rg=2.2k, G=10

Preamplifier
AD8422

Use Gain 10 ( for permitting DC offset of 300-500mV)

CMRR: I14dB (60Hz), 95dB (95Hz)@gain 10
Input Bias Cunrent: O.SpA max

Input Impedance: 200GOhm //2 pF

Tite DNS EMG 8ch ADS1299_InputPreampAD8422 chara-E/4-274

75 Amherst Street mit
Size: Letter Number:.5 Revision: Canbidge s 02139 L M CId
Date: 8/7/2019 Time: 3:43:44 AM Autho5 SeoM Ho Yeon USA
File; DNS EMG Rch ADS1299 InnutPreamp AD8422.SchDoc
1 2 3 4

I
I 2 3 4
2 3 4

preamplifier
A based

R70F
DNS

+2V51 B
C87F
R71F R GNDI
4.99K o
00 OOnF
UllF
Vin-

+
RGIF )2 RG > 7 R72F
Vout 'IN
6
REF AW - . |MPF)
| GF 4 RG ,4.99K
VNr,+ >

R4 8422BRMZ C8
|_ VINF G 4DI
4.99K10n

R75F
C
DNS
RF

Disable preamp by GAIN: G - 1+19.8k /Rg

-deleting 4.99k on Vin-, Vin+,Vout, REF
- adding 4.99k on two DNS node use Rg=2.2k, G= 10

Preamplifier
AD8422

Use Gain 10 (for permiting DC offset of300-50mV)

CMRR: 114dB (60Hz), 95dB(95Hz)@gain 10
Input Bias Current: 0.5pA max

Input impedance: 200GOhm Y 2 pF

Title DNS EMG 8ch ADS1299 InputPreamp AD8422. C 0 -E4-274

Size: Letter Number.6 Revision: 75 Ane.t Str1et mgit

Date: 8/7/2019 Tne: 3:43:44 AM Auhoi6 SeoW Ho Yeon USA
File: DNS EMG 8ch ADS1299 InputPreamn AD422.SchDoc
1 2 3 4
 4
3
I 2 3 4

IA based preamplifier

R70G
DNS

+2V5I B
C87G
GNDI
VINNG R71G
499K 00
UliG

M
V

+
RGG)2RIG' 7 R72G
Vout INNG

3REF|
RGG4 RG ,4.99K
Vin+>
A8422BRMZ
R74G C88G
VINPG , ) G 4DI
100nF
-2 151
R75G C
DNS

Disable preamp by GAIN: G= 1+19.8k / Rg

deleting 4.99k onVi-, Vn+. Vout, REF
-adding 4.99k on two DNS node use Rg=2.2k, G= 10

Preamplifier
AD8422

Use Gain 10 ( for permitting DC offset of 300-500mV)

CMRR: 114dB (60Hz), 95dB(95Hz)@gain 10
Input Bias Current: 0.5pA max

Input Impedance: 200GOhm //2 pF

Title DNS EMG 8ch ADS1299_InputPreampAD8422.

Size: Letter I Number:.7
I~7
Revision:
ed/at b- E4-274
SAmbherst Skeet
Canbidge.M4 02139
:m .. Mi
meia
Date: 8/7/2019 Time: 3:43:44AM Authofl SeoMg HoYeon USA lob
File: DNS EMG Sch ADS1299 inputtPreamn ATIR407 VAehne
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R70H
DNS

+2V51 B
C87H
R71H 1-{OGNDI
4.99K 0O 1OnF
UIIH
I Vin-

+
R7 R72H
Vout
6
3REF ".''. INH
RG2 )4 RG ,4.99K
Vin+ >
D8422BRMZ
RJ74H C88H
VINPH( ) k G 4DI
4.99K100nF
-2VS1

C
DNSi

Disable preamp by GAIN: G- 1+19.8k/Rg

-deledt4.99kon m-,Vm+,Vout, RF
.

addng 4.99k on two DNS node use Rg-2.2k, G= 10

Use Gain 10 ( for permttiing DC of etof300-500mV)

CMRR: 114dB(60Hz), 95dB (9H z)@gain 10
Input Bias Current: O.SpA max

Input Impedance: 200Ghm //2 pF

Title DNS EMG 8ch ADS1299_InputPreampAD8422 a h-E14-274

Di
Size: Letter INumber:.8 Revision: 75Ande.SMe0239

Date: 8/7/2019 Tame: 3:44 AM Autha8 SeogHoYeon USA

File: DNS EMG 8ch ADS1299 InputPreamp AD8422.SchDoc
1 2 3 4
 I 3 4
3 4

INIP)
C1 UIC
ININ ) T2nF 60 BIASREF
IN2P 62 BIASINV
C2 RI
C3 2nF 976K 63 BIASIN
R2 64 AOU
IN2N ) 2n |N BIAS DRV RVED A
16 ,90K
15 190K _ _ADS1299

nF 1 IN2P r5V/90kohm= 12uA current output lmitatifon

IN3N 1 IN2N
IN4P
IN3P
IN3N
IN4 ) 10
1SRBI
IN8N SRB2
INBP
|IN6P
IlN7N )6 RESVI
ADNl
C77 00W l ADS 1299
2nF 7 " 9
IN7P )
GNDI

IN6P 2nF __
C9 C1 -Cl C12 C13
'IN5N - C4 10uFlF luF I100nF luF B

!NP ) _ 2nF
+2V5I

- --
- +3V31 GNDI
+3V31 +3V31

R'P3 R4 .RS
-C16 C17 C18
UlB 10n IuF 100nF IuF
39-1 Cs GPIO1 42
34 DIN GPI02

SC ___ - 4- SCLK GPI04 4 GNDI O o n onADS1299 GNDI

-7 - RYCKR6-R7R8 4R7 IL 24VREFP

35 CLK 1K0OK 1OK nF VREFN +2V 51
36I CnCnww zzz
R9 41 DAISY IN RIO > » > >> 000 C
RI 10K 10K
10K
R12
10K
ADS1299

aCLKSEL : High -Internal Clock Oeain+3V31

C21
luF IluF
C22

LED for ADC operation confirmation

GNDI GNDI GNDI -2V 5I

GC23 C24 C25 C27 ADD-AVSiiem cplingCap

C26
IOnF IOOnF luF 100nF luF GNDI 54-53: luF
+2V51 -2V51 +2V5I +2V51 -2V51 +2V51 58-59: luF

-2V5G
C28 C29 C30 C31 _C32 C33 C34 C35 C36 C37 - C38 C39 GNDI
luF I0OnF luF IO0nF IOOnF luF 100nF 1O0nF 100nF IOOnF IOOnF luF GNDI

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Size: Letter Number:. Revision: Cambridge. V 02139 MfgUS
Date: 8/7/2019 Time: 3:43:44 AM | Author: SeoMHoYeon USA lb
File: DNS EM GSch ADS1299 ADC sinleInput.SchDoc
112

- __A
I 2 3 4
2 3 4

+2V51
R5
3Wi
390K C83 B
UIOA
UlOB

VCM +A1
R5( 6D_
6
5
7A R60
390K
BIASRID
>
I 00nF
G GNDI

OPA2376
OPA2376 tuF

PA2376

C85

1luF
5V/390kohm 12uA current output limitation C86 GNDI
Gain :390k /10.2k= 38.2
(Typical value of DRL)
I0OnF

C
-2V51

Right Leg Driver& Shield Dver

OPA2376

-Invest the common mode signal and feedback

for input bias current return & common modelevel shifing

Title DNSEMG_8chADS1299_BiasDRV.SchDoc Biomecha'ro-cs

______________________________________MTMedia La - E4-2 74
Size: Letter Number:. Revision: 75 Amerst Street Md
Date: 8/7/2019 Time: 3:43:44 AM Author: SeoiU Ho Yeon USA
File: DNS EMG Sch ADS1299 BiasDRV.SchDoc
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.--__ --.
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PreAmplifier Stage ADS1299

DNS FMC SchA DNS FMGch DW iw schDoc A

VINPI
VINP2
VINP3 INP3 NSP MOSI (MS
VINP4
VINP2 Aso MSO
-VINR MP4
VVNP5 INSP SCLK
IN71P
DADY
VINP8
MP3
ININ BASSBIAS

IN5N
VINN3 V?
VINVN
VINN5 RNN5 1N4N
VINN6 VINNS JNSN
VINN7 MNN
VINN7 INN6
VINN8VINNN
Th17N
INNS,
PREAMP BIAS B
MASHD
GNDI PREAMP SHD
BIASSH1I3

GNDI

PREAMP SHD 1 2GD

PREAMP BIAS 3 4 ADS BIAS GV PREAMPSHD R13 BRD SHD
VINP 5 6 VINN8 0
VINNI 7| VINPS -R14
VINP2 9 0 VINN7 'DNS
VINN2 11 12 NP
.VINP3 13 14 VINN6
VIN3
l)GJD 15 16 VINP6
VINP4 17 18 VINNS GNDI
VINN4 19 20 VINPS

PC20V

Board Shield Multiplexer

Biasing Scheme :
1) GND Shield analog input by biasing
2) BIAS DRV (driven by ADS1299) 1)PREAMP-SHD signal
3) Active GND 2) GNDI D

Title DNSEMG_8chADS1299_Interface.SchDoc J" edich-E14-274

Size: Letter Number:. Revision: 75AnherstStreet n
_____________I________I___ Cambridge. M02139 L

,
Date: 8/7/2019 Time: 3:43:44 AM Author: Seo Ho Yeon USA
File: DNS EMGT ch ADS1299 Interface SchDoc
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AD8422_Preamp AD8422_Preamp
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VINPI VREF
VINN4

-
)

GNDI

DNS EMG 8ch

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2 InputPearp_AD8422.SchDoc AD8422_Preamp
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Channel 4 drive the DRL electrode 1P

1P INP6)
RG2
INN
VINN2 VNNE
-RG2 U INN2
FV54 R66
RG2
VrINN6 B

| VIN6 VNNU
REF:) GNDI GNDI

AD8422_Preamp AD8422_Preamp
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3GNDI V~
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GNDI

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DNS NI ch ADS:

VCM CH4
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)

Title DNS EMG 8ch ADS1299_PreampStage.SchDoc ntmeha- E/4274

Size: Letter Number:. 75 Amherst Skeet usd1
Revision: Cambridge. A02139
Date: 8/7/2019 Time: 3:43:44 AM I Author Seog Ho Yeon USA
File: DNS EMG 8ch ADS1299 PreampStage.SchDoc
I 2 4
2 4
 I 3 4
3 4

A
Communication Level Shifte

+3V3
+3V3 +5V

R76
100K

iC94
U13
+3V3 2 Al < oB 1 13 TXB0104| +5V
MCU MOSt) SV MOSI')
( MCU DRDY 3 A2 U B2 12 5V DRDY
(MCl Miso A3 > > B3 10 5 V MISO
MCU CLK 5 A4 B4 10|5V SCLK)
)

6NC 0NC |9 C95

IOOnF I0OnF

B
00(
OUTPUT EN

GND GND
.R77

GND GND

C
Pin Functions
PIN BALL
D, PW, OR RUT NO. YZT NO.
ROY NO. ZXU NO.
VCCA 1 1 B2 B2 A-port supply voltage 1.2 V S VCCA S 3.6 V and VCCA S VccB.
Al 2 2 Al A3 Input/output 1. Referenced to VccA.
A2 3 3 A2 83 Input/output 2. Referenced to VccA.
A3 4 4 A3 C3 Input/output 3. Referenced to VCCA.
A4 5 5 A4 D3 Input/output 4. Referenced to VccA.
NC 6 - - - No connection. Not internally connected.
GND 7 6 84 D2 Ground
OE 8 12 B3 C2 3-state output-mode enable. Pull OE low to place all outputs in 3-state
mode. Referenced to VccA.
D

Tite DNSEMG_8chCOMMLVSHIFT.SchDoc 75n nhrie E/4-

Size: Letter Number:. Revision: Cambridge,MA 2139 meRIM
Date: 8/7/2019 Time: 3:43:44AM Author: SeoMigHoYeon USA
File: DNS EMG 8ch COMM LVSHIFT.SchDoc
I 2

-4-
 I 3 4

312C A
SCL ----- 2C3 SCLE ( 12C3 SDA ) ( 12C3 SDAE
+3V3 +3V3 -++3V3
+3V3

D10A 2 DIOB 2 DI0C 2

GND
TPD4E004DRYR
GND
TPD4EO04DRYR
GND
TPD4E004DRYR DIOD 2
TPD4EO04DRYR
GND

R31 R32 R33 R34

( SPI3 MISO '. SPI3 MISOE |SPD MOSI .. SP3 MOSIE SPI3 SCK )- .. SPI SCKE
220 SPD3 NSS ', SPI3 NSSE B
R35 220 220
220 -R36 R37
+3V3 100K +3V3 IOOK +3V3 100K +3V3 -OOK

DlIA 2 DIB 2 DIIC 2 DIlD 9;GND

TPD4EO04DRYR GND TPD4EO04DRYR GND TPD4EO04DRYR GND TPD4E04DRYR
GND GND GND GND

9.39 R40 C
R41 R42
( USART3 RX '., USART3 RXE | USART3 RTS A USART3 RTSE ) USART3 CTS USART3 CTSE USART3 TX - - USART3 TXE
220 R43 220 220 220 R46
+3V3 100OK .1100K +3V3 -'00OK 100OK
+3V3 +3V3

D12A n D2C 2
TPD4EO04DRYR GND D12B 2 GND TPD4E004DRYR GND D12D 2 GND
GND TPD4EO04DRYR GND TPD4EO04DRYR
GND GND

Many parts ofthis schematic have been impoted from

Fle:SEAMANAGE_0_1 schematic witten by Jean
FrancoisDuval.

Title DNS EMG 8chDigitalCom Protection.SchDoc BiomecharoEcs

_____________________________________ XflMTMediaLah-E14-274

Size: Letter Number:. Revision: 75AnriStree2A 9 md

Dae: 8/7/2019 Time: 3:43:44 AM | Author SeogHoYeon USA
File: DNS EMG Sch DiitalCom Protection.SchDoc
I 2
 4
3
I 2 3 4

High-speed CommunicationI
and Itegated Power Supply
A

+5V +5V

II C75
22uF
C76
OOnF

GND GND

+3V31
+5V
UL L
r+3V3 Logic COMM Level Shifter
e, i '_ SchDoc 1 16

MCU OSI) MS.MOI S-MO goINA OUTA 13>' ADS MOSI)

MCU CLK) CLK W SCLK -5 OUTB 12 ADS SCLK
MCU DRDY MCU _DRDY V DRDY -" 6OUTC INC ADS DRDY B
MCU MI HSO 7V . OUTDIND10 10 (_DIS C77 --C8C79
6- 8 NN l 0 100nF 2F22uF

CO N R78 R79 ISOW7842DWE

C N00K 100K GNDI GNDI GNDI

GND GNDI fLC liter

fl;= 1/(2*pi* sqrt(L*c))=4.95kHz

'
GND Vripple= 400uVpp (270uVrms?)

Level Shifter Isolated Integrated Power Supply

ISOW7842
Required since MCU logic level is 3V3 and Isolator logic level is +5V
Vin Range: 3V 5.5V
(while power should be supplied by +5V) Vin Net: (+5V)
Vout: 3.3V (+3V3IS0L)
Table 2. Supply Configurations
Imax: 127mA, Nominal efficiency: 48%
Icc =20mA Vl
VRipple: 9OmVpp Shorted to Veo 5V 5V
Faw: 110kHz Shorted to GND2 or floag 5V 3.3 V
V
Shorted to ND2 or flomng 3.3 3.3V
(1) Vcc = 3.3 V. OI shorted to V9s(essentially Vo = 5 V) Is not recommended mode of configuron.
(2) The SEL pin has a weekpulldown iternally. Therefore for Viso = 3.3 V, the SEL pin should be
stronglyconnected to the GND2 pi in noisy system scenarios.

Tite DNSEMG_8chISOW7842_PWRCOMM_ISOL.Sc /hatro-ls

Me9adia La - El4-2 74
Size: Letter Number:. Revision: 75AnhertS e3ee 9 MRc
IICambr-idge.U4 02139 na a
Date: 8/7/2019 Time: 3:43:45 AM Author: SeoUg Ho Yeon USA
File: DNS~ EMG tchtISOW742 PWRCOMMNISO. Shfloc
DN EM
File Rch1SO784 PWROW SOLA~o
I 2
 4
3
I 2 3 4

54-9V SMPS 5VOUT PWR SVMT rX

+VB
32
2

ML2H A

GND
tor reu PWR ISOL
Stepown in
LMR16006Y

Vin Range: 9V-54V

Vin Net: (+VB Net)
Vut;: 5V (+5VP Net)

Fsw: 2.1MHz
Vripple: 2.15mVpp before LC filter
Imax: 0.6A
Isolated Integrated Power Supply
ISOW7842 Regulated Voltage Inverter
MAX889RESA
Vin Range: 3V-5.5V
Vin Net:(+5V) Vin Range: 2.7V-5.5V
Vout: 3.3V (+3V3ISOL) Vin Net: (+3V3_ISOL)
Vout: -3.3V (+-3V3ISOL)
Imaxt: 127mA, Nominal efficiency: 48%
5VIN_3V3_LDO Ic - 20mA Imax: 200mA (Nominal Converter Output) B
DNS EMG 8ch PWR 3V3LDO.SchDoc VRipple: 90mVpp Nominal efficiency: 74%
Fsw:l0kHz Iq_max:12mA
VRipple: Typical 1SmVpp
Fsw: 500kHz

3.3VLDO 2.5V LDO -2.5V LDO

TPS73533 TPS73525 TPS73525

Vin Range: 2.7V-6.5V Vin Range: 2.7V-6.5V Vin Range: 2.7V-6.5V

M Net: (+5V) Vin Net: (+3V3_ISOL) Vm Net: (+3V3ISOL)
Vout 5V (+3V3) Vout: 2.5V(+2V5_ISOL) Vout: 2.5V (+2iSOL)

Imax: 5O0mA (Nominal Converter Output) Imax: 500mA (Nominal Converter Output) [max : 500mA (Nominal Converter Output)
280mV dropout (@500mA) Typical 280mV dropout (Max 219mV) Typical 280mV dropout (Max 219mV)
13.2uVrms noise 13.2uVrms noise 13.2uVrms noise
PSRR: 40db (@2MHzwhich is the frequency of SMPS) PSRR: 28dB (@00kHz) PSRR.: 28dB (@00kHz)

Supplying MCU power (mau current draw 120mA) Supplying AVD of ADC &preamplifier Supplying AVDD of ADC & prenplifner C

rLEDsT

+5VR6

R15 -R16
1.96K -4.75K

D2
Dil

GND GND
D

A
R -(5.0V - 1.95VY0.64mA - 4.75 kohm (To minimize BOM)
R=(3.3V-1.95V)/0.7mA=1.93kohm U Tide DNS -_EMG
Size: Letter
_ -
8ch PWR.SchDoc
_-_
INumber Revision:
Biomechatromics
MiTMedia Lah - E14-274
Cambridge,A 02139 eiS
Date: 8/7/2019 Time: 3:43:45 AM Author: SeoBR Ho Yeon USA
File: NR FMr Reh PWR Rehnn

I 2
 4
3
I 22 3 4

W=>3LD

+5V +3V3
D3
LA

CDSU4148
U2B U2A
NC IN OUT 1
NC
:: 5 EN N 3
NC
TPS73533DRBR GND
B

=C40 TPS7;5331-ORBR - C41

2u2F 10nF 2u2F

GN DGND GND GNID

3.3V LDO
TPS73533

Vin Range: 2.7V-6.5V

Vin Net: (+5V)
Vout: 5V (+3V3)

Imax: 500mA
280mV dropout (@50mA)
13.2uVrus noise C
PSRR: 40db (@2MHz which is thefrequency of SMPS)

Supplying MCU power (max current draw 120mA)

Many parts of this schematic have been imported from

FlexSEAEXECUTE_0_2 schematic written by Jean
FrancoisDuval.
D

Title DNSEMG_8chPWR_3V3LDO.SchDoc Biomecharo-ics

______________________________________MTMedia La -E14-2 74

Size: Letter
Date: 8/7/2019
Number:.
Time: 3:43:45AM
Revision:
Author: SeolfgHoYeon
File: DNS EMG Sch PWR 3V3LDO.SchDoc
75AnsherstSet3eet
USAbrdeAl3 L mJt

1I 2

Ii'
 4
2
I 2 3 4

id Voltageinput 5V SNMPS

D4

TV
CDSU4148
C43

I100nF
+5Vp
D5 U3 I LI L2
A 5 VI w6 SW A
47uH 3.3uH B
DFLS2100-7

SHN0 FB 3 2 RP7
AS2100-7 54.9k
C4LMR106Y C45
4u7F
pC44 FB A 22uF C46

R18
10K

GND GNDG IMD

N7 GND
GND GND GND

2.1MHz
SHDN has a pull-up, float to LC fiter
eniable.
fc -/(2*pi* sqrt(L*c))=27.7kHz
C

Step-down input regulator

LMR16006Y

Vin Range: 9V-54V

Vin Net: (+VB Net)
V t: SV (+5VP Net)

Faw: 2.1MHz
Vripple: 2.15mVpp before LC filter
Imax: 0.6A

Many parts of this schematic have been imported from

FlexSEA EXECUTE_0_2 schematic written by Jean
FrancoisDuval.
D

Title DNSEMG_8chPWR 54-9VSMPS 5VOUT.Sch Biomechairocs

Size: Letter Number:. Revision: 75AnrstSre02139 L
Date: 8/7/2019 Time: 3:43:45 AM Author: SeoM Ho Yeon USA
File: DNS EMG Sch PWR 54-9VSMPS VOUT.SchDoc
I 2
 I 2 3 4
2 3 4

+5VP +5VU +5y

U9

R55 DO n 8
23.7k 2 D1 Out

3Vns In2 6 B
4 lim Gnd 5
TPS211 _ C80 -CSI
C82 R56 R57 0 1nF
100nF 4.75K 510 100nF I

GND GND GND GND GND GND GND

If the +5VP supply is available, it powers the lim=500/ilim=0.98A

circuit. Otherwise,+5VM is used.

rIn the auto-switching mode (DO= 1, DI = 0), an internal power

FT connects OUT to INI if the VSNS voltage is greater than 0.8
V. Otherwise, the FET connects OUT to the higher of INI and
IN2.The Truth Table illustrates the functonality ofVSNS.

With 23.7k & 4.7k itwill switcharound 4,V. C

Many parts of this schematic have been imported from

HexSEA MANAGE_ 0 1schematic written by Jean
FrancoisDuval.
+5VP: From Buck Converter of 54-9V Supply D
+SVU: From the USB connector

Title DNSEMG_8chPWR_5VMUX.SchDoc Bio ,Iechatro ics--

MiTMedia Ia - E14-274
Size: Letter I Number:.
I75 Amherst Street nmWiS
Revision: Cambridge,A02139
Date: 8/7/2019 Time: 3:43:45 AM Author: SeoUa Ho Yeon USA
File: DNS EMG Sch PWR 5VMUX.SchDoc
I 2

--- I,-
 4
I
3
2 3 4

ISOL_POSSUPPLY ISOL NEG SUPPLY +2V51

-"-T -
B . -ri
Th-

-2V51 J3

2
3
PC3V

GNDI

Additional Power Supply for Analog Buffer B

V3 Isolated Power Converter is integrated onanounicadten isolator

C
+3V31

R19
1.96K

D7
z

GNDT

L(3.3V - 1.95V)//0.7mA =1.93 kohm

I -(5.0V - 1.95V0.7mA =436 kohm
D

Title DNSEMG_8chPWRISOLSchDoc .iomeca"ron"cs _

___________________________________MTMedia Lab- E4-2 4

Size: Letter Number:. Revision: 75Anie.A2139 Stned

Ite 75Cambri,ee0239P
Date: 8/7/2019 Tume: 3:43:45 AM Author: Seofg Ho Yeon USA
File: DNS EMG Sch PWR ISOLSchDoc
1 2 3 4
 I 2 3 4
2 3 4

Voltage Inventer

+3V31
+3V31 +3 V31

C47
22uF -3V31 -3'V31 -2V51
U4 -R20
'100K U5 L3
IN AGND GNDI
2
2 +VI +VO 5
CAP+ FB 3.3uH B

4u7F GNDI GND SHDN 6 +3V3I 1OOK L4

CAP- OUT
MAXS88
C54
22uF
3.3uH
C55
10uF
2u2F

TPS72325
10OnF 1 2u2F I10uF T
Regulated Voltage Inverter
MAX889RESA GNDI
GNDI
-2.5VLDO LC filter
Vin Range: 2.7V-5.5V TPS73525
Vin Net: (+3V3_ISOL) fe= 1/(2*pi* sqrt(L*c))=27.7kHz
Vout: -3.3V (+-3V3_ISOL) LC iter Vin Range: 2.7V-6.5V
Vin Net:(+3V3ISOL)
Imax: 200mA, Nominal efficiency: 74% fc - 1/(2*pi* sqrt(L*c))=27.7kHz Vat: 2.5V (+2V5_ISOL)
tq_max: 12mA
VRipple: Typical 15mVpp Imax: 500mA (Nominal Converter Output)
Fsw: 500kHz C
Typical 280mV dropout (Max 219mV)
13.2uVrms noise
PSRR:2dB(@00kHz)
Supplying AVDD of ADC & preamplifier

Title DNS EMG 8ch PWRISOLNEGSUPPLYMAX I h-E4-274

Size: Letter Number:. Revision: 75A derstSe3 Stre

Date: 8/7/2019 Time: 3:43:45 AM Author: SeoBR HoYeon USA
File: DNSEMG Sch PWR ISO NEGSUPPLY MAX889SchDoc
I 2
 I 3I
I 2 3 4

+2V51

U12B U12A L7
NC IN ouT
5NC56 3.3uH
INC 5 N 3

T'PS73525DRBR GND

L"9 TPS7 S251-IRBR - _C90 - J.-C91 B

2u2F 10F2u2F -- L-C92 C93

I-- T1n -T T10uF T 1uF

GNDI

S73525 Max Current rating 500mA @2.5V

LC filter

f-1/(2*pi* t(L*c))=27.7H-

2.5V LDO
TPS73525

Vin Range: 2.7V-6.5V C

Vin Net: (+3V3ISOL)
Veut: 2.5V (+2V_ISOL)

max: 5OOmA
Typical 280mV dropout (Max 219mV)
13.2uVrms noise
PSR: 28dB (@00kHz)

Supplying AVDD of ADC & preamplifier

Tide DNSEMG_8chPWRISOLPOSSUPPLY.SchDoc B 'omecharonics

______________________________________ MTMeia Lah -E4-274
Sze: Letter Number:. Revision: 75AnherstStreet meJt
8//21 Iae Cambridge. M4 0:139 ui
Date: 8/7/2019 Time: 3:43:45 AM Author SeogHoYeon USA
File: DNS EMG Sch PWR ISOL POSSUPPLY.SchDoc
I 2
 4
3
I 22 3 4

+3V3
C56
[-f10GND
I10nFD
OOnF B
U6 SN65HVD75 (RS485 B)
'485RX |E RO
485RE 27 -R22
6 120
485 DE 3 DE M
485 TX ) DI OU R45

GND

Many parts of this schematic has been imported from

FlexSEAEXECUTE_0_2 written by Jean Francois
Duval.

Tide DNSEMG_8chRS-485.SchDoc Biomecha-rot E-cs

______________________________________MTMedia Lab -E14-2 74

Size: Letter Number: Revision: 7 AneSM02139 I t

Date: 8/7/2019 Time: 3:43:45 AM Author: SeoMHoYeon LISA lob
File: DNS EMG 8ch RS-485SchDoc
 I I
I 2 3 4
2 3 4

U7A U7B U7C

USART2DE PAWKUP 2 PBO PCO C57
USART2 RE I PAIWU
USART2 TX 1 PAl PBI PCI
2
USART2 RX I PB2 PC2
T SWO 5 I PO~ 27pF
2 51 PB3 A
PA4 PB4 GPIO PC4 EXTI4 2 U7D
SPIl SCK 2 GPIO PCS 2 PC4
5 PB5 3 PCs
SPIl MISO PAS PHO/OSC IN
SPII MOSI (LED R 56, PB6 PC6
2 PA6 PHI/OSCOUT
ED G56 PB? PC7 12MHz C
12C3 SCL CO PA?
PAS LED B PBS C58 PD2
LEDID 12C3SDAC PC'
4 PA9O USART3 TX 29- PB9
PBIO SP3 SCK 5 STM32F405RG
USB DM USART3 RX 3C SPI3MISO 5 Pci
PAlO PBII 27pF
USB DP 4 SPI3 MOSI 5 PCII
PA12 PB12
T JTMS PA13 USART3 CTS 3 GND
TSJTCK PB13 PC13
USART3 RTS
SP13 NSS 5 PA15 FPA14
PA153 3 PB14 PC14
PB15 PC15
STM32F405RG STM32F405RG STM32F405RG

+3V3
USB DP )USB DP
(USB DM E3 USB DM
B

U7E +3V3 +3V3

STM32F405RG
+3V3 L5a
L5 131VDDA
1k
NRST 7 T NRST
(USART2 RE iUAT DEE R23
1.1K
R24
IK
USART2 DE USART2
-

USART2 RX s'USART2 RX
( usART2 TX U ART2TX 12C3S A_COJ
12 U U 60 SDA3
C59 C60 VSSA > > > > BOOTO C61 SCL3 12C3 SCL CON
10nF
luF l00nF r- 1010K
rThis Ilkisto reduce theM

C62 C63
GND 2u2F 2u2F
GND GND SPI3 NSS
-P3 S
ev SPD3 MISO
SPIl MIO)SPI] MISO
SPIIMOSI SPII MSK '(SPI3 MO1SI' SPI3 MOSI C
( SP~SCK SPIl SCK SPI3 SCK
GND (1SP3 SCK

|PC4 EXTI4 sGPIO PC4 EXTI4

GPIO PCS5
Max current draw,i 7mA @ 168MHz loc (GPIOI PCS

(USART3 RTS |USART3 RTS

CTS
|USART3 CTS USART3
( R( T JCKT
TK)T USART3 RX ( USARTI RX
(TSO)T SWO ( USAT3 TX T3 IX
USART3 TX
+3V3 +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 -3V3

I 6I IC6 I I IC7 I I IC7

C64 C65 C66 C67 C68 C69 C70 C71 C72 C73
I C74
100nF 1OOnF 100nF 1I00nF 00nF 100nF OOnF OOnF x100nF 1OOnF x 0uF D

Tie DNS EMG 8chSTM32F4_MCU.SchDoc Biomechai -4oics

____________________________________ MTMediaLab -E14-2 74
GND GND GND GND GND GND GND GND GND GND GND
Size: Letter Number. Revision: 75AmherstStreet git
I ICambridge. MIA 0:139 Mr8s8
Date: 8/7/2019 Time: 3:43:45 AM Author SeogHoYeon U 0SA ISU
File:
File Sch
DNS FMG
EMGSchSTM3F4 MCI
DN STM3F4 CUTShnne
Sh~ ,
I 2
I 3 4

D8
:BHSMF-C 14 B
+3V3

-R26 kR27 .R28

80.6 80.6 980.6

-R29 0
z
80.6
R30
1.96K

2 G A 00 5 QBN 2 Q2A 5 2B

C
G

GND GND GND GND

R= (3.3V -195Vy0.7mA= 1.93 kohm

IF

Many parts of this schematic have been imported from

FlexSEA MANAGE 0_1 schematic written by Jean
FrancoisDuval.
D

Title DNSEMG_8chSTM32F4_MCULED.SchDoc
________________________________________
B "omechatro,2s
MTMedia~al,-E4-274
Size: Letter Number:. Revision: 75 Amrde.t 02J39 Itreet

Date: 8/7/2019 Time: 3:43:45 AM Author: SeoNHoYeon USA

File: DNS EMG Sch 9TM32F4 MCU LRDSchDnc
I 2
I
 - T-
I
I 2 3 4
I I

DI )DE TVSDIFFPAt. t
( MCU DM (DM ) GND

R52
( MCU DP ) (DP

)
21

Route as close to the

connector as possible.

tide DNS EMG_8chUSB_Protection.SchDoc Bi-mechatro -2cs

______________________________________ MTMedia Lah - El-2 74
Size: Letter Number. Revision: 75 Anthcrst Stree3
8//09Iie
Iae Cambridge. AM 02139
Dat: 8/7/2019 Time: 3:43:45 AM IAuthor Seofig Ho Yeon USA M
File: DNS EMG Sch USB Prteion. SchDoc
2 3 4
II
 I 2 4
2 4

STM32F405RG
DNS T M" 1 chDoc Digital Comm Protection
DNS EMG Sch Di talCorn Potecton SchDoc
A
12C3 SDA CON
W3 SMA 12C3 SCL CON
12CISCL
SF13 MOSI CON
SPF13MOSI SPD MOSI PU3 MOS0
SP13 MISO CON
SP13NMISO SPUz8 MISO S13 MISOE SPD SCK CON
SPDS_NK SMDSCK SP13SCKCE
SP13 NSS CON
SPJ3 NSS
USART3 CTS CON
USART3_CTS 0SART3CTS USART3 CTSE
USART3_RX USART3(RX USART3 RX CON
USART3~TX USART3 TX USART3 TXE USART3 TX CON
USART) RTS CON
USAT3_RTS USART3 RTS USAR'TRTSEF

A nc r1oo 1.,-..--- o42-COMMISOL +3V3

SchDoc DN '1G Reh ISOW7842 PWRCOMM TSOL.SchDoc

SP13 NSS CON 4 SP3 MISO CON G

SP13 SCK CON 5 6 SPI MOSI CON
MOSI ADS MOSI MCUMOSI SPI MOSI
SCLK ICUCLK
WSSCLK
12C3 SCL CON 7 80
I2C3 SDA CON 9110 RS485 A CON B
13 14 RS485 B CON
USART3 RTS CON 156 USART3 CTS CON
USART3 RX CON USART3 TX CON
C MM,
+3V3 P 19 20 GND
PC20V

USB Protection
DNS EMG Sch L SchDoc

LEDInterface USB DP CON

US DM USB DM CON
DM

+3V3 35
D0
,A___ RS-485DRV
DNS FMG 48 chDoc R- T JTCK 2
LED
T JTMS4
go-a 485 A CON T NRST C
T SWO 6
pwnV niTo v 585 BCON
4SK IOWA
HFW6R-2STElLF
AW 2 TX 485I

-
GND

+5VU
36
IVCC

T,-I T JTCK
T JTMS
USB DM CON 2 USB-

T NRST USB DP CON 3 USB+

T SWO
4
Ml M2 M3
GND
0473460001
D
GND
R53 R54
DNS DNS
Title DNSEMG_8ch vO_2.SchDoc Mitedaab-E14-274

Size: Letter S
Number Revision
75 AnherstStreet
Cambridge. MA 02139
Mit
anrms
GNDI GND Date: 8/7/2019 Time: 3:43:45 AM Author: Seog HoYeon USA
File: DNS EMG Sch vO 2.SchDoc
I 2

a
132
Appendix B

Bill of Materials

133
134
 Bill of Materials
Designator Manufacturer jQuantityI Value Description
C1, C2, C3, C4, C5, C6, C7, C8, C14 Kemet 9 2nF CAP CER2000PF25VNPO0402
C9 Taiyo Yuden 1 1OuF CAP CER 100UF 10VX5R 1210
C10, C11, C13, C16, C18, C21, C22, C25, C27,
C28, C30, C33, C39, C59, C84, C85 TaiyoYuden 16 1uF CAP CER1UF25VX5R0402
C12, C15, C17, C20, C23, C24, C26, C29, C31,
C32, C34, C35, C36, C37, C38, C43, C56, C60,
C61, C64, C65, C66, C67, C68, C69, C70, C71,
C72, C73, C76, C77, C80, C81, C82, C83, C86,
C87A, C87B, C87C, C87D, C87E, C87F, C87G,
C87H,C88A,C88B,C88C,C88D,C88E,C88F,
C88G, C88H, C94, C95 TDK Corporation 54 1OOnF CAP CER 0.1UF 25V X5R 0402
C19, C46, C52, C53, C55, C74, C92, C93 TDK Corporation 8 10uF CAP CER 1OUF 25V X5R 0603
C40, C42, C49, C51, C62, C63, C89, C91 TDK Corporation 8 2u2F CAP CER 2.2UF 25V X5R 0402
C41, C50, C90 TDK Corporation 3 10nF CAP CER 10OPF 25V 10% X7R 0402
C44 Taiyo Yuden 1 4u7F CAP CER 4.7UF 100V X7S 1210
C45 TDK Corporation 1 22uF CAP CER 22UF 35V 20% X5R 0805
C47, C54, C75, C78, C79 Samsung Electro-Mechanics America, Inc 5 22uF CAP CER 22UF 16V X5R 0603
C48 Samsung Electro-Mechanics America, Inc. 1 4u7F CAP CER 4.7UF 25V 10% X5R 0603
C57,C58 Johanson Technology Inc. 2 27pF CAP CER 27PF 50V COG/NPO 0402
D1, D2, D7 Panasonic Electronic Components 3 LNJ247W82RA LED RED RECTANGLE SMD
D3,D4 Comchip Technology 2 CDSU4148 DIODE GEN PURP 75V 150MA 0603
D5,D6 Diodes Incorporated 2 DFLS2100-7 DIODE SCHOTKY 100V 2A POWERD1123
D8 Avago Technologies US Inc. 1 HSMF-C114 LED CHIP RGB 1.6X1.5X0.35MM SMD
D9 Panasonic Electronic Components 1 LNJ347W83RA LED GREEN RECTANGLE SMD
D10, D11, D12 Texas Instruments 3 TPD4EO04DRYR 4 PAIR TVS FOR ESD PRO
D13 Texas Instruments 1 TPD2EUSB30DRTI DIODE TVS DIFF PAIR FOR ESD PRO
J1, J4 Molex Inc 2 PC20V CONN HEADER 1MM 20POS SMD GOLD
J2 Molex Inc 1 ML2H MICRO-LOCK PLUS RIGHT ANGLE HEAD
J3 Molex Inc 1 PC3V CONN HEADER 1MM 3POS SMD TIN
J5 Amphenol FCI 1 HFW6R-2STE1LF CONN FFC FPC TOP 6POS 1.00MM R/A
J6 Molex, LLC 1 0473460001 USB - micro B Receptacle Connector
Li Bourns Inc. 1 47uH FIXED IND 47UH 750MA 280 MOHM
L2, L3, L4, L7 TDK Corporation 4 3.3uH FIXED IND 3.3UH 900MA 190 MOHM
L5 Taiyo Yuden 1 1k FERRITE BEAD 1000 OHM 0402
L6 Murata Electronics North America 1 47uH FIXED IND 47UH 250MA 1.69 OHM
 Bill of Materials
Designator Manufacturer Quantity Value Description
Q1, Q2 Rohm Semiconductor 2 EMH10T2R TRANS PREBIAS DUAL NPN EMT6
R1 Panasonic Electronic Components 1 976K RES SMD 976K OHM 1% 1/10W 0402
R2, R58, R60 Panasonic Electronic Components 3 390K RES SMD 390K OHM 1% 1/10W 0402
R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R18,
R25, R59 Vishay Beyschlag 13 10K RES SMD 10K OHM 1% 1/1OW 0402
R13, R47, R48, R49, R50 Panasonic Electronic Components 5 0 RES SMD 0 OHM JUMPER 1/10W 0402
R14, R53, R54 3 DNS Do Not Solder
R15, R19, R30 Panasonic Electronic Components 3 1.96K RES SMD 1.96K OHM 1% 1/10W 0402
R16, R56 Panasonic Electronic Components 2 4.75K RES SMD 4.75K OHM 1% 1/1OW 0402
R17 Panasonic Electronic Components 1 54.9k RES 54.9K OHM 1/1OW 1% 0402 SMD
R20, R21, R35, R36, R37, R38, R43, R44, R45,
R46, R76, R77, R78, R79 Vishay Beyschlag 14 1OOK RES SMD 1OOK OHM 1% 1/1OW 0402
R22 Panasonic Electronic Components 1 120 RES 120 OHM 1/10W 1% 0402 SMD
R23, R24, R61, R64 Panasonic Electronic Components 4 1.1K RES SMD 1.1K OHM 0.1% 1/16W 0402
R26,R27,R28,R29 Panasonic Electronic Components 4 80.6 RES 80.6 OHM 1/10W 1% 0402 SMD
R31, R32, R33, R34, R39, R40, R41, R42 Panasonic Electronic Components 8 220 RES SMD 220 OHM 1% 1/1OW 0402
R51,R52 Panasonic Electronic Components 2 21 RES SMD 21 OHM 1% 1/10W 0402
R55 Panasonic Electronic Components 1 23.7k RES 23.7K OHM 1/1OW 1% 0402 SMD
R57 Panasonic Electronic Components 1 510 RES SMD 510 OHM 1% 1/1OW 0402
R62,R63,R65,R66,R67,R68,R69 Panasonic Electronic Components 7 2.2K RES SMD 2.2K OHM 0.1% 1/16W 0402
R70A, R70B, R70C, R70D, R70E, R70F, R70G,
R70H, R75A, R75B, R75C, R75D, R75E, R75F,
R75G,R75H -_16 DNS Do Not Solder
R71A, R71B, R71C, R71D, R71E, R71F, R71G,
R71H, R72A, R72B, R72C, R72D, R72E, R72F,
R72G, R72H, R73A, R73B, R73C, R73D, R73E,
R73F, R73G, R73H, R74A, R74B, R74C, R74D,
R74E, R74F, R74G, R74H Panasonic Electronic Components 32 4.99K RES SMD 4.99K OHM 1/16W 0402
U1 Texas Instruments 1 ADS1299 IC AFE 24BIT 16KSPS LN 64TQFP
U2 Texas Instruments 1 TPS73533DRBR IC REG LINEAR 3.3V 500MA 8SON
U3 Texas Instruments 1 LMR16006Y IC REG BUCK ADJ 0.6A 6SOT 2.1MHZ
U4 Maxim Integrated 1 MAX889 IC REG SWTCHD CAP INV ADJ 8SOIC
US Texas Instruments 1 TPS72325 IC REG LIN -2.5V 200MA SOT23-5
U6 Texas Instruments 1 SN65HVD75 TXRX 3.3V RS-485 ESD 8SON
U7 STMicroelectronics 1 STM32F405RG IC MCU 32BIT 1MB FLASH 64LQFP

L.
 Bill of Materials
Designator Manufacturer IQuantity Value Description
U8 Texas Instruments 1 ISOW7842 General Purpose Digital Isolator
U9 Texas Instruments 1 TPS2111 IC OR CTRLR SRC SELECT 8TSSOP
U10 Texas Instruments 1 OPA2376 IC OPAMP GP 5.5MHZ RRO 8VSSOP
U11A, U11B, U11C, U11D, U11E, U11F, U11G,
U11H Analog Devices 8 AD8422BRMZ IC OPAMP INSTR 2.2MHZ RRO 8MSOP
U12 Texas Instruments 1 TPS73525DRBR IC REG LINEAR 2.5V 500MA 8SON
U13 Texas Instruments 1 TXBO104 IC VOLT-LEVEL TRANSLATOR 14-QFN
1X CTS-Frequency Controls 1 12MHz CRYSTAL 12MHZ 18PF SMD

IL
138
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