st2052
st2052
Current limited
power distribution switches
Not recommended for new design
Features
■ 80 mΩ high-side MOSFET switch
■ 500 mA continuous current per channel
■ independent thermal and short-circuit
protection with overcurrent logic output
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■ Operating range from 2.7 V to 5.5 V
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■ CMOS- and TTL-compatible enable inputs
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SO-8
■ 10 ms OC_N fault-blanking
■ 2.5 ms typical rise time
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■
■
Undervoltage lock out
10 μA maximum standby supply current
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■ Ambient temperature range, -40 °C to 85 °C
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■ ESD protection
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Table 1. Device summary
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Order code
c t (s Package Packaging
ST2052BD(1)
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Tube
(50 parts per tube, 40 tube per box)
ST2052BDR(1)
r o SO-8 Tape and reel (2500 parts per reel)
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1. Not recommended for new design (refer to STMPS2252MTR). Contact ST sales office for availability.
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
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Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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4.2
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Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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1 Description
The ST2052 power distribution switches is intended for application where heavy capacitive
loads and short -circuits are likely to be encountered. These devices incorporate 80 mΩ
N-channel MOSFET high-side power switches for power-distribution systems that require
multiple powers switches in a single package. Each switch is controlled by an independent
logic enable input. Gate drive is provided by an internal charge pump designed to control the
power-switch rise times and fall times to minimize current surges during switching. The
charge pump requires no external components and allows operation from supplies as low as
2.7 V.
When the output load exceeds the current-limit threshold or a short is present, these
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devices limit the output current to a safe level by switching into a constant-current mode,
pulling the overcurrent (OCx) logic output low. A 10 ms deglitching circuit provides fault-
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When continuous heavy overloads and short-circuits increase the power dissipation in the
switch, causing the junction temperature to rise,
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a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
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shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the
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designed to current limit at 0.9 A.
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switch remains off until valid input voltage is present. These power-distribution switches are
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2 Block diagram
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uct
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Power switch
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3 Pin connections
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Table 2.
Pin
Pin functions
Symbol
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Description
1 GND Ground
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2 IN
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Input voltage
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3 EN1
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Enable input. Logic high turns on power switch IN-OUT1.
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4 EN2
OEnable input. Logic high turns on power switch IN-OUT2.
)-
5 OC2 Overcurrent. Logic output active low IN-OUT2.
6
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OUT2 Power switch output
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4 Electrical ratings
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Symbol Parameter Value Unit
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VI Input voltage range(1) -0.3 to 6 V
(1)
VO Output voltage range
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IO Continuous output current Internally limited
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ESD Electrostatic discharge 2 kV
TJ Junction operating temperature
1. All voltages are referred to GND.
b s -40 to 125 °C
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4.2 Recommended operating conditions
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Table 4.
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Recommended operating conditions
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Symbol
r o Parameter Min Typ Max Unit
let
VO Output voltage range(1) 0 5.5 V
IO Continuous output current (per switch) 0 500 mA
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5 Electrical characteristics
VI = 5.5 V, IO = rated current, VIEN = VI, TJ = 25 °C, unless otherwise specified. (See Note 1
on page 8).
VI = 5 V IO = 0.5 A 80 100
VI = 5 V IO = 0.5 A, TJ = 85 °C 90 120
VI = 5 V IO = 0.5 A, TJ =125 °C 100 135
(s)
Static drain-source
RDS(on) mΩ
ON-state resistance VI = 3.3 V IO = 0.5 A 90 125
VI = 3.3 V IO = 0.5 A, TJ = 85 °C 110
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VI = 3.3 V IO = 0.5 A, TJ = 125 °C 120 160
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VI = 5.5 V 2.5
tr Output rise time ms
VI = 2.7 V 3
VI = 5.5 V
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RL = 10, C L = 1µF
e 0.3
tf Output fall time
VI = 2.7 V
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ms
VIH
High level input
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VI = 2.7 to 5.5 V 2 V
voltage
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Low level input VI = 4.5 to 5.5 V 0.8
VIL V
voltage VI = 2.7 to 4.5 V 0.4
II
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Input current VIENX = 0 V or VI -0.5 0.5 μA
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ton PTurn-on time RL= 10 Ω, CL= 100 μF 20 ms
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Table 7. Current limit characteristics
Symbol Parameter Test conditions Min Typ Max Unit
O IOS
Short-circuit output
current
VI = 5 V, OUT connected to GND,
device enabled into short-circuit
0.7 1 1.3 A
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Max Unit
VIL
Low level input
2
o d 2.5 V
VHYS
voltage
Hysteresis
P r 100 mV
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VO = 5 V VO = 3.3 V 1 μA
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VI = 5.5 V, TJ = 25 °C
TFB Fault-blanking period 2 10 ms
(See Note 2 and Note 3)
Note: 1
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Pulse testing techniques maintain junction temperature close to ambient temperature:
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thermal effect must be takes into account separately.
2
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Specified by design, not production tested.
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3
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Guaranteed by design.
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Figure 4. Waveform - propagation delays (f = 1 MHz; 50% duty cycle)
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Table 11.
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SO8 - mechanical data O
Symbol
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Millimeters inches
Min
Pr
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
O E
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3.80
1.27
4.00 0.15
0.050
0.157
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Table 12.
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Tape and reel SO-8 mechanical data
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Millimeters inches
Symbol
Pr
Min Typ Max Min Typ Max
ete
A 330 12.992
ol
C 12.8 13.2 0.504 0.519
b s D
N
20.2
60
0.795
2.362
O T
A0 8.1
22.4
8.5 0.319
0.882
0.335
B0 5.5 5.9 0.216 0.232
K0 2.1 2.3 0.082 0.090
P0 3.9 4.1 0.153 0.161
P 7.9 8.1 0.311 0.319
7 Revision history
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Table 11.
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