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CW2 Exception (2)

The document outlines an in-class activity focused on exceptions, interrupts, and traps in ARM-V7 and Cortex processors, covering various topics such as CPU attention methods, exception handling sequences, and the organization of vector tables. It includes questions on the differences between polling and interrupts, software exceptions, privilege levels, and types of stack pointers. The activity is designed to assess students' understanding of the material from specified chapters in Hohl and Wolf's texts.

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4 views

CW2 Exception (2)

The document outlines an in-class activity focused on exceptions, interrupts, and traps in ARM-V7 and Cortex processors, covering various topics such as CPU attention methods, exception handling sequences, and the organization of vector tables. It includes questions on the differences between polling and interrupts, software exceptions, privilege levels, and types of stack pointers. The activity is designed to assess students' understanding of the material from specified chapters in Hohl and Wolf's texts.

Uploaded by

Abid
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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In-class activity and Participation

Lecture 3 (Exception/Interrupt)
Points 100
Name:
(Chapters: Hohl 14.2-14.8,15.2-15.6, Wolf 3.2)
ARM-V7:: (Mostly from Hohl Chapter 14 )

1. What is exception, interrupt and trap? What are the three ways to get CPU’s attention?
6

2. What is the diVerence between polling, exception/interrupt and CPU continuous


checking? 6
3. What is the register organization for diVerent exceptions? 5

4. What is the basic sequence to handle exceptions? Write down the steps. 6
5. What is vector table? How is it organized and mapped in memory (we can assume it
virtual memory)? What is VIC? Why it is needed? 9
6. What is the diVerence between exception handling and interrupt handling? 5

7. What are the software exceptions (SVC)? How can you resolve them? Explain them in
brief. 6
8. What is exception priorities? 3

9. What is FIQ and IRQ? 4


10. What is ‘Abort’? What are the types of ‘abort’? Explain both of the aborts in brief.
7

Cortex:: (Mostly from Hohl Chapter 15)


11. What are the modes in Cortex processors? What are the privilege levels? 6
12. What is the vector table in cortex processor? 4

13. What are the types of stack pointers in cortex processors? What are the use of them?
How are they used? 6
14. What are the registers used in cortex processors to handle exceptions? Write down the
sequence of operations to access and exit exceptions in cortex processors. 6

15. What is non-maskable and maskable exception? Explain them. 6


16. What is hardware, memory management, bus, and usage fault? Explain in brief.
6

17. How many interrupts possible in cortex-M and cortex-M4 processors? In reality how
many interrupts actually supported in TM4C123GH6PM? 5
18. Write down the steps to configure an interrupt. 4

19. How subroutines are managed in program? How program return back to caller
procedure? Explain with stack, RAS, local variables etc.
20. What is tail chaining and late arriving preemption? Explain in brief with example.

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