Timers, 7-SED, LCD

The CPU provides basic computational facilities.

Timer
■

RAM is used for program storage.

■

CPU RAM ROM

High-speed
device
CPU bus
Bus
interface High-speed bus
DMA Timers
controller

Low-speed bus
Bus
interface

Device
 Digital timer/counters are used throughout embedded

Timer designs to provide a series of time or count related events within

the system with the minimum of processor and software over
head. Most embedded systems have a time component within
• Free-run hardware counter that increments or decrements once for every clock cycle.
them such as timing references for control sequences, to provide
• counter runs continuously until the timer is disabled.
system ticks
The
for
countingsystems
operating
processand
restarts
even
automatically
the generation o
when the counter reaches 0 during down-counting or some maximum value during up-counting
waveforms for serial port baud rate generation and audible tones
• Timer/counters are normally defined in terms ofare
They theavailable
counter in size that
several they can
different typesprovide.
but are essen
• They typically come in 8, 16, and 24 bit tially
variants.
based around a simple structure as shown.
• Each timer has: C lo c k in p ut
• CVAL (Compare Value)
• CTL (Control Register: enable, mask,
status)
Divi d e d c lo c k
• A timer is associated with a C o u nt e r
counter. 0000000 0000000
• Counter: Simple 32-bit value Pr e -s c a l a r or
monotonically increasing at a c lo c k d ivi d e r
per-system specific frequency.
Int e rru p ts In p ut sig n a ls
• In ARM has 2-types of Timers
• Generic Timer I/ O
c o ntrol O ut p ut sig n a ls
• External Timers
 Counter vs. Timer
• Anything a timing mechanism depends on some sort of clock . This clock
could be internal such as PLL, RC and XTAL .
• This clock could also come from an external source such as feeding pulses to
the CPU.
• If the clock comes from an internal source it is known as a Timer
• if it comes from an external source it is known as a Counter.
 Block
Clock/Timer Tree
Diagramclock
• Clock/Timer tree is a sophisticated
distribution system
• Clock system allows the tuning of the
performance and power consumption of
the device to achieve best trade-off
• P = fCV2
• Clock Source
• High Frequency Clock Source
• Precision Internal Oscillator (PIOSC) –
16MHz
• Main Oscillator (MOSC)
• PLL (Phase Locked Loop) used – 5 MHz to 25
MHz (inclusive)
• PLL not used – 4 MHz to 25 MHz
• Low-frequency clock sources
• Internal Oscillator (LFIOSC) – 33MHz
• Hibernation Module RTC Oscillator (RTCOSC) –
32.768- kHz
 System Clock Frequency
• The system clock (SysClk) is the clock that is distributed to the processor and
the integrated peripherals after clock gating.
• The SysClk frequency is based on the frequency of the clock source and the
divisor factor.
 Precision Internal Oscillator (PIOSC)
• The microcontroller powers up with the PIOSC running. If another clock source
is desired, the PIOSC must remain enabled because it is used for internal
functions.
• The PIOSC can only be disabled during Deep-Sleep mode.
• It can be powered down by setting the PIOSCPD bit in the DSCLKCFG register.
• The PIOSC generates a16-MHz clock with a +/- accuracy.
• Deep Sleep Clock Configuration Register (DSCLKCFG)
 Main Oscillator (MOSC)
• The main oscillator supports the use of crystals from 5 to 25 MHz. The system
control's RSCLKCFG register can be configured to specify the MOSC as the
system clock or as the PLL input source.
• The MOSC can be selected as the oscillator source by programming the OSCRC
bit in the RSCLKCFG register. The NOXTAL bit in the MOSCCTL register allows
the user to turn off power to the MOSC if no crystal is connected reducing
power draw from the MOSC circuit.
 Phase Locked Loop (PLL)
• Phase locked loop is a device that is used to track the phase of an input signal
for a range of frequencies.
• When PLL is tracking the phase (by keeping the phase difference constant),
PLL in lock condition. Under lock condition, the PLL tracks
then PLL is considered
the incoming signal and any variations in the input signal frequency are
followed by thePhase
PLL locked
outputloop
(i.e.,isVCO
a device that is used to track the phase
output).
of signal
• In addition, the an input signal for a at
frequencies range
the of frequencies.
two inputs of phase detector are
exactly same under lock condition.
 Timer Types
• Generic Timer
• General Purpose Timer
• System Timer (SysTick)
• Watchdog Timer
 Generic Timer
• Central timing is derived from a clock input (may be a crystal oscillator)
• Clock may be divided using a simple divider
• Based on a power of two or through a pre-scalar which effectively scales down or divides
the clock by the value that is written into the pre- scalar register
• Divided clock is then passed to a counter which is normally configured in a
count-down operation
• Loaded with a preset value which is clocked down towards zero
• When a zero count is reached, this causes an event to occur such as an interrupt of an
external line changing state
• Final block is loosely described as an I/O control block but can be more
sophisticated
• Generates interrupts and can control the counter based on external signals
which can gate the count-down and provide additional control
 General Purpose Timer (GP Timer)
• A versatile timer module found in microcontrollers, designed to be
used for a wide range of timing applications as
• Counting events, generating pulses, measuring pulse width, or triggering
actions at specific time intervals, with flexible configuration options to suit
different needs within a system;
• It's a flexible timer that can be programmed to perform various timing
tasks depending on the application.
 System Timer (SysTick)
• Simple 24/32-bit down counter to produce a small fixed time quantum.
• Software uses SysTick to create time delays or generate periodic interrupts to
execute a task repeatedly.
• The timer counts down from N-1 to 0, and the processor generates a SysTick interrupt
once the counter reaches zero.
• After reaching zero, the SysTick counter loads the value held in a special register named
the SysTick Reload register and counts down again.
• The SysTick timer does not stop counting down when the processor is halted. The
processor still generates SysTick interrupts during the process of debugging
• Another usage of SysTick timer is to create a useful hardware timer for the
CPU scheduler in real-time operating systems (RTOS).
• When multiple tasks run concurrently, the processor allocates a time slot to each task
according to some scheduling policy,
• Processor utilizes a hardware timer to generate interrupts at regular time intervals
 Watchdog Timer
• I/O device that is used for internal operation of a system.
• Watchdog timer is connected into the CPU bus and also to the CPU’s reset line.
• The CPU’s software is designed to periodically reset the watchdog timer,
before the timer ever reaches its time-out limit.
• If the watchdog timer ever does reach that limit, its time-out action is to reset the 4.3
processor. In that case, the presumption is that either a software flaw or hardware
problem has caused the CPU to misbehave. Rather than diagnose the problem, the
system is reset to get it operational as quickly as possible.

Reset Time-out

Watchdog
CPU
timer
 Timer Modes
• The Timers have 4 different modes of operation. 2 of these modes must be
chosen at all times in order to set the timer. These modes are :
• Periodic vs. One-shot mode
• In periodic mode, the Timers continues counting after it reaches timeout. It merely
clears the timeout flag of the Timer and restarts.
• In one-shot mode, Timer stops counting after timeout.
• Up vs. Down counting mode.
• In the up mode, the timer starts from zero and counts up to the value set in the Interval
Load Value Register.
• In the down mode, the timer counts down from the value set in the Interval Load Value
Register to zero.
 Clock Types and Counter Modes
• Clock are 3-types based on specific process usage
• System clock - periodic ‘tick’ for the system clock
• Refresh clock - regular interrupt on every couple of cycles to perform a
dynamic memory refresh
• Audio clock - source of square waveforms for use as audio tones with the
built-in speaker.
• Counter have 6- modes
• Mode 0 (Interrupt on terminal count) - An initial value is loaded into the
counter register and this then immediately starts to count down at the
frequency determined by the clock input. When the counter reaches zero,
an interrupt is generated.
 Output goes high
pulled low, the counter
Count reloaded with the initial value and the
3426523
process repeated.down
This is mode 3 with the 8253.
Counters Modes by 1 on
Lo a d initievery
a l v a lu e
(0000004)
clock O ut p ut g o e s lo w
• Mode 1 (Programmable one-shot ) - Create a single pulse with a 0000004
programmable
0000001 cycle
duration. The pulse length is first loaded into the counter. When the counter reaches
Output goes low
zero, the counter output goes low thus ending the pulse.
C o u nt 0000000
0000003
O ut p ut g o e s hig h
• Pulse duration is determined by the initial down
value loaded into the counter times the clock by 1 on
period. Clock e v e ry
0000002
• Can be used to provide pulse width c lo c k
modulation for power control where the Gate c y cle 0000001
gate is connected to a zero crossing or similar
detector or clock source to create a periodic
Output Length 0000000
= counter value x
signal.
clock period
• Mode 2 (Rate Generator) Programmable
- Divide by one-shot timer counter mode
N mode where N is defined by the initial C lo c kThe pulse duration is determined by the initial value loaded
value loaded into the counter. When the into the counter times the clock period. While this is a common
timer/counter mode, many devices such as the 8253 incorporat
counter reaches zero, the output is pulleda Oreset.
ut p ut
If the gate signal is pulled low and then high again to creat
low, the counter reloaded with
Ratethe initial(divide
generation value and
a newbyrising
N) edgethewhile
process repeated
the counter is counting down, the curren
count value is ignored and replaced by the initial value and th
Square wave rate generator
 Counters Modes
• Mode 3 (Square wave rate generator) - Similar to mode 3 except that
the waveform is a square wave with a 50:50 mark/space ratio.
• Mode 4 (Software triggered strobe) - When mode 4 is enabled, the
counter will start to count as soon as it is loaded with its initial value.
When it reaches zero, the output is pulsed low for a single clock
period and then goes high again.
• can be used as a software-based watchdog timer where the output is
connected to a non-maskable interrupt line or a system reset
• Mode 5 (Hardware triggered strobe) - Mode 5 is similar to mode 4
except that the retriggering is done by the external gate pin acting as
a trigger signal.
 Counting Modes
• 3- counting modes
• Up-counting mode: counter starts from 0 to a constant and then restarts
from 0. Software sets up the constant and stores it in a special register
called the auto-reload register (ARR). For example, if ARR is 4, the counter
value is 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, and repeats until the timer is disabled.
Counting Period of Sawtooth Waveform= (1 +ARR) x (1/fclk_cnt)
• Down-counting mode: counter starts from the auto-reload value down to 0
and then restarts from the auto-reload value. For example, if ARR is 4, the
counter value is 4, 3, 2, 1, 0, 4, 3, 2, 1, 0, and repeats until the timer is
disabled.
• Center-aligned counting mode: which performs up-counting and down-
counting alternatively. For example, if ARR is 4, the counter value is 0, 1, 2,
3, 4, 3, 2, 1, 0, and repeats until the timer is disabled. Counting Period of
Triangle Waveform= 2 x ARR x (1/fclk_cnt)
 1
Counting Period =(1 + ARR) x f

Counting Modes
CLOCK_CNT

------------------"------------------, __ ,-- Overflow ----· Overflow ----· Overflow

value
(ARR)

1
auto- ,
=
Counting Period (1 + ARR) x f
CLOCK_CNT
reload ,,-----------------' .. ________________ ,
value
(ARR)

Underflow Underflow , Underflow

/
,,// /
/ /

auto-
reload
value
(ARR)

. -----------------------------------"!
1
Counting Period = 2 x ARR x f Underflow
CLOCK_CNT
 Counter Update Events
• 3-update events
• Overflow: In up-counting mode, overflow occurs when the
counter is reset to 0.
• Underflow: In the down- counting mode, underflow occurs when
the counter is reset to ARR.
• Both: In the center-aligned counting mode, underflow and
overflow occur alternatively.
 Timer/Counter Special Usages
• Compare Output
• Input Capture
• PWM
Output
15.1 Timer Organization and Counting Modes
Compare Output
asic diagram of the output compare of a timer. The timer counter
A timer is a free-run hardware counter that increments or decrements
apture/compare register (CCR) holdsThe
clock cycle. thecounter
value runs
that continuously
is compareduntil the timer is disabled.
• Comparator consistently
processcompares the counterwhen
restarts automatically valuethewith some
counter given0 during dow
reaches
constant, some maximum value during up-counting. Software can select the frequen
t channels shareanthe
• Generates sameclock
output free-run
or thattimer
the free-run
ansointerrupt counter. Therefore,
counter
if they are increments
equal. theor decrements at some desir
es the timer counter withIffour CCR
a timer registers
works simultaneously
as output compare, as shownandin Figure 15-1, the comparat
• Software can program the constant value to control the timing of outputs or
dent interrupts.
outputs based on thecompares
comparison results.value with some given constant, and generates an
the counter
interrupt if they are equal. Software can program the constant value to con
• Clock
imer to drive
counter the timer
(CLOCK_CNT) counter (CLOCK_CNT)
can beor slowed
of outputs interrupts.down bycana be slowed down by a
constant
constant
o generate factor
output called
that spansprescaler
over a longto aperiod.
long
Constant
period. Value
Generating
fcwcK PSC Set by software
A=B an interrupt if
fcwcK_CNT = +1 equal
Timer
Counter
es the timer's resolution, but decreases theClock
chance of overflow
Counter++ (or Counter--)
Signal
roves the energy efficiency. for each clock cycle
 Applications
• Output Compare is used to Generate certain digital waveforms for control
purposes
• Many applications in microcontroller applications:
• Start analog devices
• Control speed of motors
• Control power output rate
• Communications
• Control servo
 Output Compare
Example
• Example: Generate a waveform that is 1-cycle high, 2- cycle low, 3-cyle high, 1-
Example:
cycle low, Generate a waveform that is 1-cycle high, 2-
and repeating
• The MCU cycle low, 3-cyle
may generate outputhigh,
events 1-cycle low, and
(transitions) repeating
at 220 (current time), 221,
223, 226,
The227 and so
MCU on with
may initial output
generate state as events
low (transitions) at 220
(current time), 221, 223, 226, 227 and so on with initial
state as low
220 221 222 223 224 225 226 227

1 2 3 1
 processor chip, external crystal oscillators, or some internal trigger signal such as the
Example
output of another timer. External clocks are preferred over internal clocks because
external clocks are more accurate than internal clocks.

16-bit Auto
Reload Register
Clock (ARR)
selection
Internal Clocks

Trigger & Clock 16-bit Prescaler CK_CNT 16-bit Counter

External Clocks
Controller (PSC) (CNT)

Internal Trigger Input

16-bit Capture Compare

Re ister 1 CCR1
16-bit Capture Compare
I CNT > CCR1 ? I Channel 1
Re ister 2 CCR2 I CNT > CCR2 ? I Output Channel 2
16-bit Capture Compare I CNT > CCR3 ? I Controllers
L __ _ _ _
Channel
Channel
3
4
Re ister 3 CCR3
I CNT > CCR4 ? I
16-bit Capture Compare
Compare
Re ister 4 CCR4
Four Channels
 Example
• Timer counter (CNT) has 16 bits.
• The capture/compare register (CCR) holds the value that is compared with the
timer counter.
• Output channels share the same free-run timer counter
• Timer hardware compares the timer counter (CNT) with CCR registers simultaneously
and generates independent outputs based on the comparison results.
• Timer counter (CLOCK_CNT) can be slowed down by prescaler
• Large prescaler reduces the timer's resolution, but decreases the chance of overflow
and underflow and improves the energy efficiency.
• Different clocks can drive the timer.
• Can be built-in clocks within the processor chip, external crystal oscillators, or some
internal trigger signal such as the output of another timer.
• External clocks are preferred over internal clocks because external clocks are more
accurate than internal clocks.
 Counting Period= (1 +ARR) x - 1-
( NT) Counter f cLocK_CNT

Timing Diagram
Auto Reload \
Value (ARR) -------------- -

I I I
I I I
Compare/Capture _____ TI ___ _ _ ____ I_____ _ _____ TI ___ _
Value(CCR)

I I I
I I I
0
i
Timer Output ! Toggle i Toggle ! Toggle

Output Toggl:oc]R '" o""'"' )1/ o"""' )1/ 0

"''"'

Mode _______,_ _ ________.,.I

y
1. .

Timer Output Set

1
Output Period= 2 x (1 +ARR) x - -
fcLocK_CNT
High Mode wlth(OC]REF) High

None one-pulse
None one pulse 30V
Mode i

Timer Output Set Set Set

(OCREF) High High

with one pulse 30V

- .
____I,_ __ .____,____,I_ ____ ,______
1
Output Period= (1 +ARR) x - -
fcLocK_cNT
 Input Capture
• Hardware automatically logs the counter value into a special register (called
CCR) and generates 15.1 - an interrupt
Timer Organizationwhen the desired
and Counting Modes event occurs.
• Typically, the interrupt handler needs to copy register CCR to a user buffer to
record the timing
If the of pastofevents.
function a timer is input capture (see Figure 15-2), the hardware automatically
logs the counter value into a special register (called CCR) and generates an interrupt when
• Software calculates the
the desired difference
event between
occurs. Typically, two
the interrupt logged
handler values
needs to andCCR
copy register finds
to a the
time span of two events.
user buffer to record the timing of past events. Then, software calculates the difference
between two logged values and finds the time span of two events.
Generating
an interrupt
Edge
Detector ··.... Trigger
External \\he copy
Signal Captured
Value
Timer CCR Register
Counter
Clock Counter++ (or Counter--)
Signal for each clock cycle

Figure 15-2. A timer is used as input capture. The edge detector triggers the hardware to copy
 Applications
• Many applications in microcontroller applications:
• Measure rotation rate
• Remote control
• Sonar devices
• Communications
• Generally, any input that can be treated as a series of events, where the
precise measure of event times is important
• An event is a transition of binary signal
Example: How many events make up the following
waveform
Example: The input is understood as events occurring at
the following times: 220, 221, 223, 226, and 227 with
• An input digitalized and then times captured
• initial
The inputstate as lowas events occurring at the following times: 220, 221,
is understood
223, 226, and 227 with initial state as low
 Operation
• A timer can be used for triggering an output at a specified time to
general output signals (PWM output, comparator output)
• Input capture is to find the time span between two rising or falling
transitions in an internal or external signal.
• Capture occurs on (1) either rising or falling edges, (2) only falling edges, or
(3) only rising edges.
• When the desired transition is detected, the timer hardware automatically
captures this time instant by copying the value of the free-run counter
(CNT) to the compare and capture register (CCR).
• At the same time, the timer hardware generates an interrupt or DMA
request and sets the CCIF flag in the status register (SR)
 • Similarly, the difference between a rising edge and a falling ed
Operation 1 pulse width.

• Input capture measures

the time span between
(9 (9
two events
---+1.----T-i_m_e_s-pa-n----.-+1---· time
• If the input signal is
periodic, the difference
of the counters
captured at two External Signal 1
consecutive rising
edges or at two One falling trans ition and one rising transition
consecutive falling
edges measures the External Signal 2
period of the
waveform.
Only falling transitions or only rising transitions
• Similarly, the difference
between a rising edge
and a falling edge
t
CCR_ Last
t
CCR_New
measures the pulse
width If up-counting , no overflow or underflow:
Time Span = CounterClockPeriod x {CCR_New - CCR_Last)
 If up-counting , no overflow or underflow:
Time Span = CounterClockPeriod x {CCR_New - CCR_Last)

Operation 2 Figure 15-18. Input capture measures the time span between two events.

!------------- Time span ------------j

• Measuring the
pulse width if the
timer is up- External Signal
counting
I
• Calculate the pulse counter : I
width, the period, I
I
I
I
and the duty cycle ARR ---r----- -------..,-
of the input 1 1

waveform by using CCR_New ----}---- -

two or three I
consecutive I
I
captures I
• when measuring CCR_Last
a time span
longer than the
counting period,
software must
consider the / '' OC++; OC++; OC++; ";7
overflow and
underflow events Capture Capture
of the free- Interrupt Interrupt
running counter. OC: overflow counter
Time Span = CounterClockPeriod x (CCR_New - (CCR_Last) + ( 1 + ARR) x OC)
 Pin Requirements
• Each input channel has a configurable input source, a digital input filter, and
an edge detector.
• Input source of the capture module has a few options.
• Capture signal can be an external signal applied to different timer channels (i.e., on different GPIO
pins) or an internal trigger signal made by other timers.
• Edge detector can be programmed to detect only falling edges, only rising edges or
both.
• Filter specifies the number of events needed to validate a transition on the input. If we
need to capture each valid transition, software should disable the external trigger
filtering by setting the external trigger filter (ETF) to zero.
• Digital input filter removes noise pulses in an input signal. For example, if the input signal of a push
button takes 10 internal clock cycles to become stable, then we can make the filter duration last
longer than 10 clock cycles.
15.4.3 Interfacing to Ultrasonic Distance Sensor
Example: Ultrasonic
Application:Sensor
Sonar Device
An ultrasonic distance sensor has one transmitter and one receiver. The transmitter
generates short bursts of high-frequency ultrasonic waves. The receiver detects any wave
• Ultrasonic
reflected back fromdistance
the target, sensor
as shownhas one15-28.
in Figure transmitter and one receiver.
• Transmitter
Without generates
contacting with the targetshort bursts
physically, of high-frequency
it measures ultrasonic
the difference waves.
in time between
• Receiver
sending waves anddetects any
receiving wave waves.
reflected reflected
Theback from
distance the target
is then calculated asPing)))
follows: sensor:
ultrasound
• Distance: . Round Trip Timex Speed of Sound distance detection device
Distance =
2

Application: Sonar Device

One example application is an automatic door opener, which opens a door when a person
approaches. Compared with optical distance sensors, ultrasonic distance sensors are low
cost but less accurate.

Ping))) sensor: ultrasound

distance detection device
 Application: Speedometer
How to detect the speed
• How to of
detect the speed of a treadmill?
a treadmill?

Magnet sensor Microcontroller

Waveform

http://class.ece.iastate.edu/cpre288 12
 PWM
• PWM is a simple digital technique to control the value of analog variable.
• PWM uses a rectangular waveform to quickly switch a voltage source on and off to
produce a desired average voltage output.
• Although the output is binary at any time instant, the average output over a time span
can be any value between 0 and the maximum voltage.
• Percentage of time in the on state within one period is proportional to the mean value
of the voltage output. Consequently, when software changes the duration of the on
state, the output voltage is adjusted accordingly to emulate an analog signal.
• PWM is used to control motor speed, torque control, digital encoding in
telecommunication, DC-to-DC power conversion, audio amplification, LED
brightness control, etc.
 must be at least 120 Hz to prevent the flickering effects that humans can see.
pulse on time (T0 n)

Duty Cycle
duty cycle = x 100%
pulse switching period (T5 )
T The average value of a simple PWM output based on a sawtooth carrier signa
on X 100%
Ton +Taff constant reference, as illustrated in Figure 15-9 and Figure 15-10, is linearly propo
• Average value of a simple 1
toPWM
the dutyoutput
cycle. based on a sawtooth carrier signal
and a constant reference,
pulse switching period = - - - - - - - - - - -
PW M switchingThe linearly
duty cycle
frequency proportional to the duty cycle.
is defined as follows:

Duty
• duty
ng the cycle
cycle, iscandefined
software control this as follows:
average value. In the LED example,
duty cycle =
pulse on time (T n)
x 100%
0
ness is determined by the PWM duty cycle. Figure 15-9 and Figure 15-10 give
pulse switching period (T5 )
mples in which the average output is 1/6 and 1/2, respectively.
T
Counter
on X 100%

Auto Reload
Switching period Ts
Carrier Signal
Ton +Taff
Value (ARR)
Com pa ref
where Reference
Signal
Capture
Value (CCR)
1
pulse switching period = - - - - - - - - - - -
PW M switching frequency

By changing the duty cycle, software can control this average value. In the LED ex
!
I
!
I
I
i
the brightness is determined by the PWM duty cycle. Figure 15-9 and Figure 15-
I :
Taff !Toni three examples in which the average output is 1/6 and 1/2, respectively.
v r--------<!r''-,:!

PWM Counter
Output Switching period Ts
Auto Reload Carrier Signal
Value (ARR) Reference
Average
Output Com pa ref Signal
--------- - ---------- - --------- - ------ Capture
Value (CCR)

Figure 15-9. Example of simple PWM when duty cycle is 1/6

 PWM Output
• PWM output signal is determined by three factors:
• Comparison between the timer counter (CNT) and the given reference
valued stored in the compare and capture register (CCR),
• PWM output mode, and
• Polarity bit.
• PWM modes:
• PWM Mode 1: If the counter is less than the reference signal, the timer
reference output (OCREF) is then held at logic high; otherwise, it is held at
logic low.
• PWM Mode 2: The timer reference output (OCREF) in mode 2 is the
opposite of mode 1. If the counter is greater than the reference signal,
OCREF is then held at active; otherwise, OCREF is held at inactive.
 • PWM Mode 2: The timer reference output (OCREF) in mode 2 is the opposite of
mode 1. If the counter is greater than the reference signal, OCREF is then held at
PWM Modes
active; otherwise, OCREF is held at inactive.

PWM Reference Output (OCREF)

PWMMode Counting Mode
Logic High Logic Low
Up-counting CNT < CCR CNT CCR
Model
Down-counting CNT .$. CCR CNT > CCR
Up-counting CNT CCR CNT < CCR
Mode2
Down-counting CNT > CCR CNT .$. CCR
Table 15-3. Timer reference output (OCREF) of PWM mode 1 and mode 2
• OCREF is an internal output, which always uses active high logic. However, the
actual output (OC or OCN) can be active high or active low.
• In active high, a high voltage represents logic high (or called active), and a low voltage
represents logic low (or called inactive).
• The output of active low is the opposite of active high.
• Selection of active high or active low is controlled by the polarity bit
eF)2 In sum, the actual PWM output (OC or OCN) is determined by both the PWM mod
Average
the polarity bit.Output
e2
PWM Signal Period
Figure 15-11 shows an example of the timer reference output
e 15-11. Reference output (OCREF) in PWM mode 1 and PWM mode 2
(OCREF) for center-cou

eriod:
re • For up- or down-counting:
15-11. Reference output (OCREF) in PWM mode 1 and PWM mode 2
Auto-Reload Value
(ARR)

n-counting:
Period:
Clock Period of Timer
wn-counting:
PWM Period = (1 +ARR) x
1 + Prescaler CCR
Clock Period of Timer
PWM Period = (1 +ARR) x
nting mode: 1 + Prescaler
• For center-counting mode:
Clock Period of Timer
unting
PWMmode:
Period= 2 x ARR x - - - - - - - Reference
- Output
1 + Prescaler
Clock Period of Timer
(OCREF)

PWM Period= 2 x ARR x - - - - - - - -

1 + Prescaler
PWM Mode 1
Average
M mode and the polarity bit, the duty cycle of the main output OC Output

• PWM Duty Cycle:

output OCN in up-counting or down-counting is
i t

CCR Reference Output !

(OCREF)

Duty Cycle = ARR +l Average

Output
CCR
{ 1- - - PWM Mode 2
--
ARR+ 1
xample of PWM mode 1 output on up-counting. The duty cycle of
 Timer Bit Size and Maximum Delay Size
• Assuming we running on a TM4C Tiva C Cortex-M4 which runs at 16MHz by
default , lets see how that affects our Timer.
• 16MHz literally means ------ 16 000 000 clock cycles per second.
• To find the time taken for 1 clock cycle, which is also known as the clock period, all we
have to do is (1/16 000 000) = 62.5x10-9 s = 62.5 ns
• Therefore, it takes 62.5 nanoseconds to run a single clock cycle at 16MHz.
• Now, if we have selected the 16-bit Timer mode, the largest value that can
provide is 216 = 65,536
• To find the maximum delay we can achieve , all we have to do is multiply the value
above by our clock period.
• 65536 * 62.5e-9 = 4.096 milliseconds.
• If we select the 32-bit mode, the largest value is 232 = 4294967296
• 4294967296 * 62.5e-9 = 268.435 seconds
Setting the Delay unit : microsecond, millisecond,
second
• 16MHz = 16 000 000 clock cycles per second.
• So if we want to create a delay interval (timer limit) of 1 second, all we have to
do is load 16 000 000 into the Timer Interval Value Load Register
• TIMER0_Limit = 16000000 -1
• Because the counter counts from zero in an up-counter mode and to zero in a down-
counter mode we, we have to subtract 1 from the 16000000.
• Following the same calculation, if we want to create a millisecond delay Timer
function, we will have to load the value 16 000 into the Timer Interval Value
Load Register.
• TIMER0_Limit = 16000 -1
• Because 1 millisecond = 0.001 seconds. So, 0.001 * 16000000 = 16000
 7-Segment Display
• Consists of seven LEDs (hence its name) arranged in a rectangular fashion
• Each of the seven LEDs is called a segment because when illuminated the
segment forms part of a numerical digit (both Decimal and Hex) to be
displayed.
• An additional 8th LED is sometimes used within the same package thus
allowing the indication of a decimal point, (DP) when two or more 7-segment
displays are connected together to display numbers greater than ten.
• 2-types
• Common Anode (CA): all the anode connections of the LED segments are joined
together to logic “1”.
• Common Cathode (CC): all the cathode connections of the LED segments are joined
together to logic “0” or ground.
CA vs CC
7-Segment Display Segments for all
Numbers
Individual Segments Illuminated
Decimal Digit
a b c d e f g
0 × × × × × ×
1 × ×
2 × × × × ×
3 × × × × ×
4 × × × ×
5 × × × × ×
6 × × × × × ×
7 × × ×
8 × × × × × × ×
9 × × × × ×
 LCD (Liquid Crystal Display)
HD44780LCD Connection
Display Diagram
• Each character can be displayed with help of many
pixels (not just 7-LEDs)
(8-bit data
• Assume atleast bus)
Each character has 40 pixels
40 pixels
o

The image pattern is encoded

• The image pattern is encoded
o
1 1
1 0
LCD Display
1
0
1
0
0
1
(40 pixels) 1 0 0 0 1
• N x K characters oin a Note that it is possible to change
display

LED+
Image

LED-
VDD
1 1 1 1 0

VSS

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7
RW
5V
the FONT

VO

RS

E
• N characters per line 1 0 1 0 0 Pattern
• K lines 1 0 0 1 0
• (20 x 2) 5V Write
1 0 0 0 1 Backlight
Only 0 0 0 0 0 (optional)

Microprocessor
NxK
Display Memory (DDRAM)
N Characters per line R
(It stores all characters GPIO
K lines
received.) Pins
11110
e.g., 20x2
10001
10001 LCD Display
11110 COM
o Read/Write (RW) connects to the ground if processor does not read data from LCD
 HD44780 Connection Diagram
HD44780 Connection
(8-bitDiagram
data bus)(8-bit data bus)
• Read/Write (RW) connects to the
LCD Display

ground if processor does not read

LED+

LED-
VDD
VSS

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7
RW
5V

VO

RS

E
data from LCD
• LED+ and LED- pins provide 5V voltage
5V Backlight
(optional)

for backlights. Microprocessor 2

3
• Enable (E) pin provides clock signal GPIO
Pins 4
• Register Select (RS) 5
6
• RS=0: data on the data bus is a command 7
Upper bits
• RS = 1: data on the data bus is actual
data. } Saves four pins for the processor

• Saves four pins for the processor

} For each 8-bit data, transfer the upper 4 bits first and then the lower 4 bits.

• For each 8-bit data, transfer the upper

4 bits first and then the lower 4 bits.
 Addressing
Addressing
Display DRAM
0x38
0x61 0x00

0x39 0x013 8

0x014 a
h

8 2x20
0x38
0x68 0x040 20x2

0x053
GPTM Module for TM4C123GH6PM