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Assignment 3_FET Amplifiers

The document is an assignment on electronic circuit design, consisting of 24 questions related to FETs, bias arrangements, and amplifier characteristics. It includes calculations for voltages, gains, and circuit analysis based on provided figures. The questions cover various aspects of JFETs and common source amplifiers, requiring identification and computation of parameters like VGS, ID, and output voltages.

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16 views

Assignment 3_FET Amplifiers

The document is an assignment on electronic circuit design, consisting of 24 questions related to FETs, bias arrangements, and amplifier characteristics. It includes calculations for voltages, gains, and circuit analysis based on provided figures. The questions cover various aspects of JFETs and common source amplifiers, requiring identification and computation of parameters like VGS, ID, and output voltages.

Uploaded by

talhaalinaseer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Electronic Circuit Design

Assignment No 3

Q.No.1. Identify the type of FET and its bias arrangement in figure 1. Ideally what is VGS?
Q.No.2. Calculate the dc voltages from each terminal to ground for the JFET in figure 2.

Figure 1

Q.No.3. Identify each characteristic curve in figure 2 by the type of FET that it represents.

Figure 2

Q.No.4. In figure 3 ID = 2.83mA. find VDS and VGS. VGS(off) = -7V and IDSS = 8mA.

Q.No.5. If a 50mV rms input signal is applied to the amplifier in figure 3, what is the peal to peak output voltage?
gm = 5000µS.

Q.No.6. If 1500 Ω load is ac coupled to the output in figure 3, what is the resulting output voltage (rms) when a
50mV rms input is applied? gm = 5000µS.

Q.No.7. Determine the voltage gain of each common source amplifier in figure 4.

Q.No.8. Draw the ac and dc equivalent circuits for the amplifier in figure 5.

Q.No.9. Determine the drain in figure 5 given that IDSS = 12.7mA and VGS(off) = -4V. The Q-point is centered.

Q.No.10. What is the gain of the amplifier in figure 5 if C2 is removed?

Q.No.11. A 4.7 KΩ resistor is connected in parallel with RL in figure 5. What is the voltage gain?
Figure 3

Figure 4

Figure 5

Q.No.12. For a common source amplifier in figure 6, determine ID, VGS, VDS, for a centered Q-point. IDSS = 9mA
and VGS(off) = -3V.

Q.No.13. If a 10mV rms signal is applied to the input of the amplifier in figure 6, what is the rms value of the output
signal?

Figure 6
Q.No.14. Determine VGS, ID, VDS for the amplifier in figure 7. IDon is 8 mA at VGS 10 V, VGS(th) = 2.5 V, and gm =
3000µS.

Figure 7

Q.No.15. Determine Rin seen by the signal source in figure 8. IGSS = 25 nA at VGS = -15V.

Q.No.16. Determine the total drain voltage waveform (ac and dc) and the vout waveform in figure 9. gm = 4.8 mS,
and IDSS = 15 mA. Observe that VGS = 0V.

Figure 8

Figure 9

Q.No.17. For the unloaded amplifier in figure 10, find VGS, ID, VDS and the rms output voltage Vds. IDon = 8 mA at
VGS = 12V, VGS(th) = 4V, and gm = 4500S.

Figure 10

Q.No.18. For the Source Follower in figure 11, determine the voltage gain and the input resistance. I GSS = 50 pA at
VGS = -15V and gm = 5500 µS.
Q.No.19. If the JFET in figure 11, is replaced with one having gm = 3000 µS what are the gain and the input
resistance with all other conditions the same.

Figure 11

Q.No.20. Find the gain of each amplifier in figure 12.

Q.No.21. Determine the voltage gain of each amplifier in figure 12, when capacitively coupled load is changed to 10
KΩ.

Figure 12

Q.No.22. A common gate amplifier has a gm = 4000 µS, and Rd 1.5 KΩ. What is its gain?

Q.No.23. What is the input resistance of the amplifier in question 22?

Q.No.24. Determine the voltage gain and input resistance of the common gate amplifier in figure 13.

Figure 13

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