Scribd
Upload
2 views

Lab Manual for Exp 5 - Multiplexer

The document outlines an experiment aimed at designing and verifying combinational circuits using a 4X1 multiplexer. It includes details on the apparatus required, the theory behind multiplexers, a truth table, and a procedure for constructing circuits such as a full adder and logic gates. The document also mentions the use of circuit diagrams for various configurations but does not provide specific observations or conclusions.

Uploaded by

godofdevil190
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
2 views

Lab Manual for Exp 5 - Multiplexer

The document outlines an experiment aimed at designing and verifying combinational circuits using a 4X1 multiplexer. It includes details on the apparatus required, the theory behind multiplexers, a truth table, and a procedure for constructing circuits such as a full adder and logic gates. The document also mentions the use of circuit diagrams for various configurations but does not provide specific observations or conclusions.

Uploaded by

godofdevil190
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 3

Design of Combinational Circuits using 4X1 Multiplexer

Exp. No: 5 Date:

Aim: To design and verify combinational circuits using 4X1 Multiplexer

Apparatus: Breadboard, Digital trainer board, IC 74153, IC 7432, and wires.

Theory:
A multiplexer or data selector is a logic circuit that accepts several data i/ps
and allows only one of them at a time to get through the output. The selection of
desired data i/ps is controlled by the select lines. Normally there are 2^N input lines
and n-select lines whose bit combination decide which i/p has to be selected. The
MUX IC has an enable i/p to control the operation of the unit where the enable i/p is
given in binary state. The circuit functions as a normal multiplexer when it is in other
state i.e. o/p is disabled.

Truth Table:

Inputs Output
E S1 S0 U

Procedure:

1. Make necessary connections for the full adder, logic gates using multiplexer.
2. Provide inputs and check for the corresponding outputs to verify the truth table.
Circuit Diagram:

a) 4X1 Multiplexer I/O Connection:

b) Full Adder using MUX:

c) NAND and NOR gate using MUX:


d) 8X1 MUX using 4X1 MUX:

Observations:

Conclusion:

Signature

You might also like