Current Applied Physics 48 (2023) 42–46

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Current Applied Physics

journal homepage: www.elsevier.com/locate/cap

Fabrication of suspended graphene field-effect transistors by the

sandwich method
Hyunsuk Shin a, Sungbae Lee b, *
a
Department of Physics and Photon Science, Gwangju Institute of Science and Technology, Gwangju, 61005, Republic of Korea
b
The School of Energy Engineering, Korea Institute of Energy Technology (KENTECH), Naju, 58330, Republic of Korea

A B S T R A C T

A novel fabrication technique that can be used for making a series of suspended graphene field-effect transistors on Si-substrate is discussed. The electrical properties
of graphene channel can be significantly degraded by defects and chemical residues between graphene and substrate. To minimize electrical degradation, a method of
physically suspending graphene from the substrate has been considered while maintaining its structural integrity. To address this problem, we employed a sandwich
method to fabricate a suspended GFET, realizing 76% device fabrication yield that is higher than those realized by the other methods. Furthermore, the degradation
of electrical properties due to external factors decreased. As our method has a mechanically stable structure, it can be imposed to make electrical devices with various
two–dimensional (2D) materials. Our method can also be applied to the engineering of future devices in various applications because a large amount of electrically
clean samples can be manufactured at once.

1. Introduction [14], a cell for high-resolution transmission electron microscopy

(HRTEM) [15], and an ultra-fast suspended self-biasing graphene
Owing to its outstanding electrical and mechanical properties, the modulator [16]. For these reasons, the production of suspended GFETs is
discovery of graphene by Geim and Novoselov in 2004 enabled many important to fully utilize the intrinsic properties of graphene.
applications [1–3] such as quantum hall effects, quantum dots, Unfavorably, the fabrication of suspended GFETs is problematic.
weak-localization [4–6], photodetectors [7], gas sensors [8], and flex­ Although the conventional method has proven to be effective for pro­
ible displays [9]. To understand the electrical properties of ducing individual working devices in several experiments, it is difficult
low-dimensional novel materials such as graphene, a field-effect tran­ to manufacture numerous devices concurrently in one large-scale sub­
sistor (FET) is often used in experiments. A FET can change the Fermi strate, with acceptable consistency for wider applications. This is not
level of the channel material through the electric field, allowing it to only because of the energetically unstable nature of 2-D materials in
measure microscopic changes in drain current [10]. general but also because graphene, during its chemical and physical
The electrical transport properties of 2D materials such as graphene steps regarding suspension, can easily be broken or sag down into the
are significantly affected by the inhomogeneity of a substrate owing to trench, leading to lower yields in device fabrication.
the lack of bulk screening effects. For most graphene FETs fabricated on There are two options for fabricating suspended GFETs. The first
Si/SiO2 substrates, dislocations or defects on the surface of the oxide method is to transfer the graphene onto the substrate with a pre-
layer tend to trap charges at the graphene-oxide interface, and such designed trench. The second method is to fabricate the trench after
trapped charges act as a scattering center in the graphene layer, as the graphene is transferred. The problems with both methods will be
emphasized by Martin et al. in 2008 [11]. Thus, the most fundamental discussed later in this paper along with the proposed solutions. Our
solution to this problem is to physically separate the active graphene fabrication process is based on a mass production approach using large-
channel from the substrate. Adopting the idea of suspension, Bolotin area chemical vapor deposition (CVD) graphene, produced by LG Elec­
et al. showed that the mobility of graphene can be as high as 200,000 tronics. A sheet of graphene is transferred to the substrate by a wet
cm2V− 1s− 1 at 5 K [12], and Du et al. demonstrated the ballistic transport transfer step before being patterned to a suitable shape by optical
properties of graphene FETs (GFET) under 100 K [13]. Furthermore, lithography and reactive ion etching (RIE). The formation of a trench for
suspended GFETs have been engineered for various applications based the suspension of the graphene active channel is achieved through wet
on the intrinsic properties of graphene, such as a visible light emitter etching. All fabrication steps were chosen based on the possibility of

* Corresponding author.
E-mail address: [email protected] (S. Lee).

https://doi.org/10.1016/j.cap.2023.01.012
Received 28 September 2022; Received in revised form 6 January 2023; Accepted 29 January 2023
Available online 2 February 2023
1567-1739/© 2023 The Authors. Published by Elsevier B.V. on behalf of Korean Physical Society. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
H. Shin and S. Lee Current Applied Physics 48 (2023) 42–46

2. Fabrication of devices

The substrate in use was a <100>-oriented Si wafer with a 300-nm-

thick SiO2 layer. The CVD graphene that we used in experiments was
provided by LG Electronics. Our fabrication methods were developed in
three stages. Each method is distinguished into metal­
–graphene–substrate (MGS), graphene–metal–substrate (GMS), and
metal–graphene–metal–substrate (MGMS) according to the sample
structure. There are no differences in the techniques used in each
fabrication step, but structural differences distinguish each method
owing to the variation of the order of the steps. The fabrication of GFET
comprises five main processes. First, lithography was required for the
contact pads and source–drain electrodes. Photolithography or e-beam
lithography was chosen depending on the line-width of the devices.
Second, 5 nm of Ti/50 nm of Au were deposited for fabricating the
Fig. 1. Three types of fabricated device set-ups for suspended GFET—ideal electrode using the e-beam evaporator. Third, we used the conventional
MGS, GMS, and MGMS set-up. wet transfer method for transferring the CVD graphene onto copper foil
[17]. Fourth, the sheet of transferred graphene was etched by O2 plasma
mass production. However, these processes, although they allow for using the RIE technique. RIE was performed using a MINIPLASMA sta­
mass production of identical devices, also cause other technical chal­ tion of Plasmart with an O2 gas pressure of 30 mTorr, a power of 50 W,
lenges, such as the formation of hyper-surface tension leading to the and total etching time of 60 s. Finally, a portion of SiO2 layer under the
ripping of the graphene film during the drying stage of chemicals. Such active channel of graphene was etched using a
technical challenges are the ones we are hoping to overcome with this hydrofluoride-ammonium fluoride mixture, also known as a buffered
proposed fabrication technique. oxide etchant (BOE – Sigma Aldrich). The etching rate was set to 1.5
In this study, we demonstrate the technique of fabricating many nm/s for the SiO2(100) layer with 90 s of total etching time.
suspended GFETs simultaneously by employing a sandwich method. The Fig. 1 shows the schematics for the three proposed fabricated device
resulting ratio of successfully suspended graphene after wet etching of set-ups. For the MGS set-up, graphene was transferred onto the sub­
SiO2 substrate was over 76%. Moreover, the electrical measurements of strate. Subsequently, the metals were deposited onto the graphene sheet.
the current–voltage (I–V) characteristics were obtained for comparing Thereafter, graphene was patterned and etched into the planned design.
the acting channel materials before and after suspension. Finally, the substrate was etched to fabricate the trench under the
channel. For the GMS set-up, electrodes were deposited before the
graphene was transferred. After the transfer, graphene was patterned to

Fig. 2. (a) AFM image of MGS set-up. Highlighted region (white-dotted box) indicates the graphene flake under the metal. (b) Line profile graph of the MGS set-up.
The inset image shows the final results for the MGS set-up. (c) AFM image of GMS set-up. Highlighted region (white-dotted box) indicates the graphene flake under
the metal. (d) Line profile graph of the MGS set-up. The inset image shows the final results for the GMS set-up.

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H. Shin and S. Lee Current Applied Physics 48 (2023) 42–46

Fig. 3. (a) SEM image of the MGMS set-up. The upper part of the image corresponds to the graphene area that is suspended. The lower part of the image corresponds
to the absence of the graphene area. (b) Top-down view of the fabricated suspended GFET. (c) AFM image and surface profile of the trench without graphene. The
height difference is measured as ~160 nm, and (d) AFM image and surface profile of the trench with graphene. The height difference is measured as ~65 nm.

fit in the FET device set-up. Lastly, the substrate was etched using BOE. the trench. It is considered to have inevitably occurred during the
In the MGMS set-up, we placed the graphene between the double- etching/washing step. Fig. 2 (c) and (d) show the AFM image and the
layered metals. At first, electrodes were deposited onto the substrate. corresponding line profile of the GMS set-up. The AFM image clearly
Secondly, graphene was transferred to the substrate via the wet transfer shows the folded problem of the GMS set-up. The inset of Fig. 3 (d)
method. Third, the top layer of metal was fabricated on top of the gra­ shows an image of the resultant device developed based on the GMS set-
phene sheet. Fourth, the graphene was patterned using the RIE tech­ up.
nique. Lastly, the substrate was etched using BOE to define the trench. To summarize the drawbacks of the two preceding methods, the MGS
The attempts to order the fabrication steps for high-yield and set-up exhibited an undercutting problem during the etching process,
structurally stable devices for suspended GFETs were developed in three and the GMS set-up exhibited a folded graphene problem, although it
steps. The first trial was a conventional method (MGS set-up) related to was free from the undercutting problem. To overcome all these prob­
Du’s study conducted in 2008 [13]. After the non-suspended GFET was lems, the MGMS set-up was proposed. In this set-up, there are two layers
fabricated, the device was wet-etched to develop a trench under the of metals. Each metal has a different purpose during the process—the
active graphene channel. Thus, there was an extremely high probability purpose of the bottom metal layer is related to the undercutting prob­
of the collapse of the active channel. Fig. 2 (a) and (b) show the atomic lem, whereas the purpose of the top metal layer is to hold the graphene
force microscopy (AFM) image and the line profile of the MGS set-up. during the etching step to prevent it from sagging. As a result, the sus­
Through the graphene boundary under the electrode, we confirmed pended GFETs were successfully developed in our methods, and the
that the substrate under the electrode can also be etched during the sample production using the MGMS set-up achieved a 76% success rate.
etching process. The inset of Fig. 2 (b) shows a schematic of the resulting Fig. 4 shows the structure of the MGMS set-up based on AFM data and
shape of the device, following the MGS set-up. The result clearly shows scanning electron microscopy (SEM) images. AFM data shows that the
that the etchant was drawn into the gap between the graphene and SiO2 depth of the trench without the graphene channel is ~160 nm, whereas
by the capillary-tube effect, and the substrate was etched not only for the it is ~65 nm in the presence of graphene channel. It is clear that the
channel region but also for the entire region covered with graphene, graphene inside the channel is suspended ~100 nm from the substrate,
irrespective of the presence of metal. which is roughly the depth of the trench formed by etching SiO2.
Our second attempt followed to address the undercutting problem. In
the GMS set-up, the trench was etched after the metallization of elec­ 3. Results and discussion
trodes. The graphene sheet was transferred afterward. In this case, the
metal successfully acted as a passivation layer in the etching process. For the test of the electrical performance of the devices, the electrical
Therefore, the trench was well-defined, as expected, unlike the GMS set- output was measured by SCS-4200 in a high vacuum (<10− 7 Torr) at
up case. This method may not cause any problems when a device with a room temperature. For improving the contact and electrical properties,
smaller channel length is fabricated. However, for devices with a larger thermal annealing was performed for devices in a vacuum chamber
size, during wet etching of the oxide layer, the graphene sheet also (<10− 7 Torr, 180 ◦ C, 30 min). The IV measurement scheme was used to
sagged down gradually, and was folded through the surface profile of ensure the establishment of the ohmic contacts in all of the devices that

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H. Shin and S. Lee Current Applied Physics 48 (2023) 42–46

Fig. 4. (a) Total resistance–gate voltage graph, with bias voltage of 1 mV. The
gray symbols correspond to the non-suspended GFET, and the red symbols
correspond to the suspended GFET. In addition, the closed symbols correspond
to the backward sweeping mode and the open symbols correspond to the for­
ward sweeping mode of the gate voltage. Furthermore, sweep directions are
indicated by arrows. (b) Dirac voltage hysteresis versus carrier density. (c)
Electron mobility versus Dirac voltage. (b), (c) Black symbols correspond to the
non-suspended GFET, and the red symbols correspond to the suspended GFET.
(For interpretation of the references to colour in this figure legend, the reader is
referred to the Web version of this article.)

survived through physical and chemical processes. These pre-selected

devices with ohmic contacts become the base of the presented statis­
tics. The total resistance of a device can be represented by the following
equation [18]:
⎡ √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ⎤
( )2̅ − 1
eμ Wch Cox
Rtotal = Rs + ⎣ FE n20 + •VG0 ⎦ (1)
Lch e

where Rs is the series resistance (not comprising the channel resistance),

e is the charge of the electron, μFE is the field-effect mobility, Wch is the
channel width of graphene, Lch is the channel length of graphene, n0 is
the residual carrier density, Cox is the capacitance per unit area, and VG0
= VG – VDirac is the gate voltage difference from Dirac voltage. The fitting
parameters are n0 and μFE for this equation.
Fig. 4 (a) shows the electrical properties of a GFET that is modified by
the applied gate voltage through an over-doped Si back gate. The elec­
trical properties of a device for both before suspension (black data
points) and after suspension through chemical wet etching (red data
points) are compared. In this device, the Dirac voltage exists in the
negative voltage region (VDirac < 0 V) before etching, but after the
physical elimination of the substrate, the Dirac voltage is shifted into the
positive voltage region (VDirac > 0 V). The hysteresis, according to sweep
direction, decreased after the suspension of the channel.
In the same manner, we tested 25 samples. Overall, as can be
observed from Fig. 4 (b), the carrier density (n) at Dirac point decreased
after the suspension of the graphene channel. These electrical results
supported that our graphene FET was well-suspended because the
charged impurity at the surface of substrate cannot affect the graphene
channel. As a result, our devices enable improved understanding of the
intrinsic properties of graphene. The decreasing carrier densities induce
reduction of hysteresis according to the gate sweep direction. We
expressed this hysteresis as a difference of the Dirac voltage through the
sweep direction (|VDirac, forward –VDirac, backward|). On average, hysteresis
decreased from 5.6 V before suspension to 3.26 V after suspension. The
hysteresis was caused by the charge carrier that was trapped in the SiO2
substrate under the graphene channel [19]. In the case of the suspended
graphene FET, the effect of the trapped charge decreased because of the
physical separation of the acting channel and substrate.
Furthermore, the Dirac points were shifted toward the positive
voltage region. Before and after the suspension of graphene, the average
Dirac point for all the samples was − 19.2 V and 6.11 V, respectively. The
shifting of the Dirac point is attributed to surface contamination during
the fabrication processes. Before each measurement, thermal annealing
was conducted to reduce the effect of chemical residues. In our results,
the change in the Dirac point from n-doped region to p-doped region was
caused by the physical separation from the oxygen vacancy inside SiO2
[20]. Fig. 4 (c) shows the result of the Dirac point distribution and the
mobility difference between the electron and hole (|μe- μh|). The carrier
mobility was comparable for the two cases. Before device suspension,
(caption on next column) the average electron mobility was 2217.7 cm2V− 1s− 1. After device sus­
pension, the average electron mobility was 2587.4 cm2V− 1s− 1. How­
ever, the asymmetry in transport was decreased after suspension.
According to the type of charged impurity, the scattering probabilities of
electrons and holes are different [21]. If the sign of charge carrier and

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H. Shin and S. Lee Current Applied Physics 48 (2023) 42–46

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