Hardware And Virtual

Machine

COMPUTER SCIENCE 9618 PAPER 3

Hardware And Virtual Machine Software
CPU architecture is the design of a computer's central
processing unit. For example Von Neuman Architecture.

Every computer uses Von Neumann architecture, but

advancements in computer technology have led to more
complex processor designs

Complex Instruction Set Computer (CISC)

It is design to carry out a given task with as few lines of
assembly code as possible .
CISC processor is based on single instruction but
complex which need to be converted by the processor
into a number of sub-instruction to carry out the
required operation .

1 2 3

2 x
ADD x,y
3

4 y

Memory
Question : Difference Between Fixed length instruction and
Variable length instruction ?

Instruction 1 → Fixed Length instruction

Fix the amount of memory it will consume e.g 16 bits, 4 bits.

Instruction 2 → Variable Length instruction

It can take as much space as it wants.

Question : Difference between Hardwired Control Unit and

Programmable Control Unit ?

Hardwired Control Unit

Uses Logic Circuits
Flip Flop

Programmable Control Unit

Use programs, code will compile, run, generate output
 Features Of CISC
CISC has more instructions
CISC has fewer registers
CISC instructions are more complex
CISC has many instruction formats
CISC uses multicycle instruction
CISC uses variable length instruction
CISC has poor pipelining
CISC requires more complex circuits
CISC has more addressing modes
CISC makes less use of RAM
CISC has programmable Control Unit

Note : CISC emphasizes on Hardware ( Means more complex

hardware circuits would be required to handle complex tasks

Reduced Instruction Set Computer (RISC)

With fewer instructions, the processor achieves better
performance, as it doesn’t need to break down complex
instructions, and Assembly Code is broken into a number of
single cycle instructions.
 1 2 3

1
LOAD A,X
LOAD B,Y 2 x
ADD A,B
STORE Z 3

4 y

Memory

A B Z

Features Of RISC
Risc has fewer instructions.
Risc has many registers
Risc instructions are simpler
Risc has few instruction format
Risc usually uses single cycle instructions
Risc uses fixed length instructions
Risc has better pipelineability
Risc requires less complex circuit
Risc has fewer addressing modes
Risc makes more use of RAM
Risc has hardwired control unit

Note: Emphasize on software.

 Pipelining
It is the way of improving computer performance

Explanation
Let's assume that we are doing laundry.

One washer (takes 30 min)

One drier (takes 40 min)
One folder (takes 20 min)

It takes 90 minutes to wash, dry and fold 1 load of laundry.

How long does 4 loads take?

The Slow Method

1 2 3 4 5 6

W D F

W D F

W D F

W D F

If each load is done sequentially it takes 6 hours

 Laundry Pipelining
1 2 3 4 5 6

W D F

W D F

W D F

W D F

Question : What is meant by pipelining?

Pipelining is instruction level parallelism which means

multiple operations are performed in single cycle.
Execution of an instruction is split into number of stages.
When first stage for an instruction is completed, the first
stage of the next instruction can start executing.
Another instruction can start executing before the
previous one is finished.
Processing of a number of instructions can be done
simultaneously.
5 Stages of Processor

1. Fetch Instruction.
2. Decode Instruction.
3. Execute Instruction.
4. Access operand in memory.
5. Write result to register.

OPCODE: What do we need to do (Decoded Instruction)

OPERAND: What do we need to do it to (Data)

There are 4 instructions ABCD

Without Pipelining

Means 1 instruction is taking 5 cycles each so if there are 4

instructions how many cycles would they need ?
 With Pipelining

By the help of pipelining only 8 cycles were used so How

many cycles were saved ?

Interrupt Handling In CISC

Detect Interrupt: The processor detects an interrupt
signal from a device or software event.
Save Current State: It saves the program counter and
other registers to resume later.
Identify Interrupt: The processor looks up the interrupt
type in the Interrupt Vector Table to find the relevant
service routine.
Execute ISR: It jumps to the Interrupt Service Routine
(ISR) to handle the specific task.
Restore and Resume: After the ISR finishes, the processor
restores the saved state and continues the main
program.
 Interrupt Handling In RISC
Interrupt Detection: When an interrupt signal is received,
the RISC processor pauses its current operations to
address the interrupt.
Flushing the Pipeline: Since RISC uses a pipelined
approach, it discards (or "flushes") all remaining
instructions in the pipeline to prevent partial operations
from affecting the interrupt handling.
Saving State: The processor saves the current state, such
as the program counter and register values, to ensure it
can resume normal operations after the interrupt is
handled.
Executing the Interrupt Service Routine (ISR): The
processor jumps to the appropriate Interrupt Service
Routine, which is a set of instructions designed to handle
the specific interrupt.
Restoring State and Resuming: Once the interrupt is
serviced, the processor restores the saved state and
continues executing the main program.
 Four Basic Computer Architecture
Flynn’s Classification : based on number of instructions and data

Instruction stream : Sequence of instructions executed by the

processing unit
Data stream : Sequence of data or temporary result called by
instruction stream

SISD : Single instruction, Single data

SIMD : Single instruction, Multiple data
MISD : Multiple instruction, Single data
MIMD : Multiple instruction, Multiple data

Single Instruction Single Data

Data Processor Instruction

Source

There is only one processor

The processor executes one set of instruction on one set of data.

Note : Each task is processed in a sequential order

 Single Instruction Multiple Data

Processor

Data Processor Instruction

Source
Processor

uses many processor.

Each processor has several ALU
Each ALU executes the same set of instruction on different
set of data at the same time.

Application

Processor

Image 3 Increase
Processor
pixels Brightness
Processor

3 pixel = 3 processors
Each processor will increase
brightness of each pixel
 Multiple Instruction Single Data

Processor

Data Processor Instruction

Source
Processor

There are several processors

Each processor executes different sets of instruction on one
set of data at the same time.

Multiple Instruction Multiple Data

Processor

Data Processor Instruction

Source
Processor

There are several processors

Each processor executes a different set of instruction.
Each processor operates on different set of data.
 Massively Parallel Computers
Massive : large number of processors.
Parallel : to perform a set of coordinated computations simultaneously.

Question : Describe what is meant by Massively Parallel

Computers?

large number of processors.

working collaboratively on the same program.
working together simultaneously on the same program.
communicating via message interface.
 Issues In Massively Parallel Computers
HARDWARE :

Processors need to be able to communicate

So that processed data can be transferred from one
processor to another.
So it's a very challenging topology.

Software :

Appropriate programming language should be used.

which allows data to be processed by multiple
processors simultaneously.

Question : Explain one of the hardware issues in massively

parallel computers?

Communication between the processors is the main issue

As each processor needs a link to every other processor
so it’s a very challenging topology.

Characteristics Massively Parallel Computers

Large number of processor
Collaborative and simultaneous processing
Network infrastructure
Communicate by sending messages.
 Conditions for massively parallel computers
No single processor
should have separate buses.

Question : What changes would be required to this program

code in order to transfer it into Massively Parallel
Computer?

Split into blocks of code so that it can be processed

simultaneously instead of sequentially.
Each block is processed by a different processor which
allows each of the processor to simultaneously process
the different blocks of code independently.