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Computer Organization and architecture

Presentation · October 2018

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Subarna Shakya
Tribhuvan University
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Introduction
 Overview

Why study computer organization and architecture?

Design better programs, including system software such as compilers,
operating systems, and device drivers.

Optimize program behavior.

Evaluate (benchmark) computer system performance.

Understand time, space, and price tradeoffs.

Computer organization

Encompasses all physical aspects of computer systems.

E.g., circuit design, control signals, memory types.

How does a computer work?

Computer architecture

Logical aspects of system implementation as seen by the designer.

E.g., instruction sets, instruction formats, data types, addressing
modes.

How do I design a computer?

2
 Computer Components

• At the most basic level, a computer is a device consisting of

three pieces:
A processor to interpret and execute programs
A memory ( Includes Cache, RAM, ROM)
to store both data and program instructions
A mechanism for transferring data to and from the outside world.
I/O to communicate between computer and the world
Bus to move info from one computer component to another

3
1.3 An Example System

Consider this advertisement:

What does it all mean??

4
Architecture & Organization 1

Architecture is those attributes visible to the
programmer

Instruction set, number of bits used for data
representation, I/O mechanisms, addressing
techniques.

e.g. Is there a multiply instruction?

Organization is how features are implemented

Control signals, interfaces, memory technology.

e.g. Is there a hardware multiply unit or is it done by
repeated addition?
Architecture & Organization 2

All Intel x86 family share the same basic architecture

The IBM System/370 family share the same basic
architecture

This gives code compatibility

Organization differs between different versions

Structure & Function

Structure is the way in which components relate to
each other

Function is the operation of individual components as
part of the structure
Function

All computer functions are:

Data processing

Data storage

Data movement

Control
Functional view

Functional view of a computer

Data
Storage
Facility

Data
Control
Movement
Mechanism
Apparatus

Data
Processing
Facility
Operations (1)

Data movement

e.g. keyboard to screen

Data
Storage
Facility

Data
Control
Movement
Mechanism
Apparatus

Data
Processing
Facility
Operations (2)

Storage

e.g. Internet download to disk

Data
Storage
Facility

Data
Control
Movement
Mechanism
Apparatus

Data
Processing
Facility
Operation (3)

Processing from/to storage

e.g. updating bank statement

Data
Storage
Facility

Data
Control
Movement
Mechanism
Apparatus

Data
Processing
Facility
Operation (4)

Processing from storage to I/O

e.g. printing a bank statement

Data
Storage
Facility

Data
Control
Movement
Mechanism
Apparatus

Data
Processing
Facility
 Structure - Top Level
Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
Structure - The CPU
CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
 Structure - The Control Unit
Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
What is a program?

A sequence of steps

For each step, an arithmetic or logical operation is
done

For each operation, a different set of control signals is
needed
Function of Control Unit

For each operation a unique code is provided

e.g. ADD, MOVE

A hardware segment accepts the code and issues the
control signals
Components

The Control Unit and the Arithmetic and Logic Unit
constitute the Central Processing Unit

Data and instructions need to get into the system and
results out

Input/output

Temporary storage of code and results is needed

Main memory
Computer Components:
Top Level View
Instruction Cycle

Two steps:

Fetch

Execute
Fetch Cycle

Program Counter (PC) holds address of next
instruction to fetch

Processor fetches instruction from memory location
pointed to by PC

Increment PC

Unless told otherwise

Instruction loaded into Instruction Register (IR)

Processor interprets instruction and performs required
actions
Execute Cycle

Processor-memory

data transfer between CPU and main memory

Processor I/O

Data transfer between CPU and I/O module

Data processing

Some arithmetic or logical operation on data

Control

Alteration of sequence of operations

e.g. jump

Combination of above
Instruction Cycle -
State Diagram
Interrupts

Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing

Program

e.g. overflow, division by zero

Timer

Generated by internal processor timer

Used in pre-emptive multi-tasking

I/O

from I/O controller

Hardware failure

e.g. memory parity error
Interrupt Cycle

Added to instruction cycle

Processor checks for interrupt

Indicated by an interrupt signal

If no interrupt, fetch next instruction

If interrupt pending:

Suspend execution of current program

Save context

Set PC to start address of interrupt handler routine

Process interrupt

Restore context and continue interrupted program
Instruction Cycle (with Interrupts) -
State Diagram
Memory Connection

Receives and sends data

Receives addresses (of locations)

Receives control signals

Read

Write

Timing
Input/Output Connection(1)

Similar to memory from computer’s viewpoint

Output

Receive data from computer

Send data to peripheral

Input

Receive data from peripheral

Send data to computer
Input/Output Connection(2)

Receive control signals from computer

Send control signals to peripherals

Receive addresses from computer

e.g. port number to identify peripheral

Send interrupt signals (control)
CPU Connection

Reads instruction and data

Writes out data (after processing)

Sends control signals to other units

Receives (& acts on) interrupts
Buses

There are a number of possible interconnection
systems

Single and multiple BUS structures are most common

e.g. Control/Address/Data bus (PC)

e.g. Unibus (DEC-PDP)
Expansion Buses

These are “slots” on the motherboard

Examples

ISA – Industry Standard Architecture

PCI – Personal Component Interconnect

EISA – Extended ISA

SIMM – Single Inline Memory Module

DIMM – Dual Inline Memory Module

MCA – Micro-Channel Architecture

AGP – Accelerated Graphics Port

VESA – Video Electronics Standards Association

PCMCIA – Personal Computer Memory Card International
Association (not just memory!)
3 ISA
slots

Pentium 6 SIMM 2 DIMM

5 PCI slots
CPU slots slots
What is a Bus?

A communication pathway connecting two or more
devices

Usually broadcast

Often grouped

A number of channels in one bus

e.g. 32 bit data bus is 32 separate single bit channels
Data Bus

Carries data

Remember that there is no difference between “data”
and “instruction” at this level

Width is a key determinant of performance

8, 16, 32, 64 bit
Address bus

Identify the source or destination of data

e.g. CPU needs to read an instruction (data) from a
given location in memory

Bus width determines maximum memory capacity of
system

e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus

Control and timing information

Memory read/write signal

Interrupt request

Clock signals
Bus Interconnection Scheme
Single Bus Problems

Lots of devices on one bus leads to:

Propagation delays

Long data paths mean that co-ordination of bus use can
adversely affect performance

If aggregate data transfer approaches bus capacity

Most systems use multiple buses to overcome these
problems
Traditional Bus Architecture
High Performance Bus
Bus Types

Dedicated

Separate data & address lines

Multiplexed

Shared lines

Address valid or data valid control line

Advantage - fewer lines

Disadvantages

More complex control

Ultimate performance
Bus Arbitration

More than one module controlling the bus

e.g. CPU and DMA controller

Only one module may control bus at one time

Arbitration may be centralised or distributed
Centralised Arbitration

Single hardware device controlling bus access

Bus Controller

Arbiter

May be part of CPU or separate
Distributed Arbitration

Each module may claim the bus

Control logic on all modules
Timing

Co-ordination of events on bus

Synchronous

Events determined by clock signals

Control Bus includes clock line

All devices can read clock line

Usually sync on leading edge

Usually a single cycle for an event
Synchronous Timing Diagram
 PCI
•Currently by far the most popular local I/O bus, the Peripheral
Component Interconnect (PCI) bus was developed by Intel and
introduced in 1993

•PCI is a 32-bit bus that normally runs at a maximum of 33 MHz.

•The key to PCI's advantages over its predecessor, the VESA

(Video Electronics Standards Association) local bus, lies in the
chipset that controls it.
 PCI
•The speed of the PCI bus can be set synchronously
or asynchronously

• In a synchronized setup (used by most PCs), the

PCI bus runs at half the memory bus speed; since
the memory bus is usually 50, 60 or 66 MHz, the PCI
bus would run at 25, 30 or 33 MHz respectively.

• In an asynchronous setup the speed of the PCI bus

can be set independently of the memory bus speed.
 PCI
•Most peripherals use PCI connections
•The PCI bus is the first bus to popularize bus mastering; probably
in part because for the first time there are operating systems and
software that are really capable of taking advantage of it.

•The PCI bus is part of the Plug and Play standard developed by
Intel, with cooperation from Microsoft and many other companies.
PCI systems were the first to popularize the use of Plug and Play.
PCI

Peripheral Component Interconnect

Also called “Local Bus”

History

Developed by Intel (1993)

Very successful, widely used

Much faster than ISA

Gradually replacing ISA

Configuration

Parallel, multi-drop
PCI

Used for…

Just about any peripheral

Can support multiple high-performance devices

Graphics, full-motion video, SCSI, local area networks,
etc.

Specifications

64-bit bus capability

Usually implemented as a 32-bit bus

Runs at 33 MHz or 66 MHz

At 33 MHz and a 32-bit bus, data rate is 133 Mbytes/s
PCI Bus

Peripheral Component Interconnection

Intel released to public domain

32 or 64 bit

50 lines
PCI Bus Lines (required)

Systems lines

Including clock and reset

Address & Data

32 time mux lines for address/data

Interrupt & validate lines

Interface Control

Arbitration

Not shared

Direct connection to PCI bus arbiter

Error lines
PCI Bus Lines (Optional)

Interrupt lines

Not shared

Cache support

64-bit Bus Extension

Additional 32 lines

Time multiplexed

2 lines to enable devices to agree to use 64-bit transfer


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PCI Commands

Transaction between initiator (master) and target

Master claims bus

Determine type of transaction

e.g. I/O read/write

Address phase

One or more data phases