Assignment (1)

▪ Team members:

Name Code Section

Mohamed Nader Baz 2100405 2
Mahmoud Hossam Mohamed Ahmed 2101408 2
Mostafa Medhat Mohamed 2100731 2

Assignment (1):
Comparison of Modern Semiconductor Devices:
• TFET
• FinFET
Items of comparison:
1. Structure
2. Mechanism of operation
3. Performance parameters
4. Applications
 Assignment (1):
TFET (Tunnel Field Effect Transistor):
Structure:
TFET structure is similar to a simple p-i-n diode structure with reverse biased at a gate terminal.
Similar to MOSFET, TFET has three terminals drain, gate, and source. The channel is placed
between the drain and source and the gate is mounted over the channel, and isolated by a
dielectric material.

The most distinctive feature of TFET is its drain and source doping. In conventional MOSFET
the doping of Drain and Source is similar while in TFET it is different in nature. The doping of
drain and source are n-type and p-type respectively or vice versa and the channel region is
small doped or intrinsic. Under the gate

the dominant carrier in the channel defines the type of TFET. If the dominant carriers are
electrons in the channel, then it is n-TFET, and opposite to this If the dominant carriers are holes
in the channel, then the TFET is p-type

For an n-type TFET, the drain is doped n+ while the source is doped p+. For a p-type TFET, the
drain is doped p+ while the source is doped n+. The channel is an intrinsic or lowly doped p-type
or n-type semiconductor. The channel is separated from the gate electrode by a dielectric,
similar to a conventional MOSFET.

n-TFET p-TFET
Operation:
Band to Band tunnelling is the working principle of TFET. The charge carriers leave the source
by tunnelling and enter into the channel this mechanism is done by BTBT. According to BTBT, the
charge carriers tunnel into the conduction band from the valence band through the energy band
gap or vice versa.

At the condition of off-state in an n-type TFET, the gate voltage is almost zero and at this
condition source region’s valance band lies below the channel’s conduction band and the
valance band and conduction band are misaligned, and BTBT is inhibited. however, it shows an
extremely low level of drain current. When the positive gate voltage increases at a sufficient
level above the zero volt, the density of the charge carrier increase under the gate, and the
conduction band of the channel push down and get aligned with the valence band of the source
as a result the electrons easily tunnel into conduction band through valance band. Due to
positive bias at the drain, these electrons are swept into the drain.

In p-type TFET at off-state condition, the gate voltage is almost zero. At this condition valance
band of the channel region lies below the conduction band of the source region, and BTBT is
inhibited and shows drain current at an extremely low level. when the negative gate voltage
increases at a sufficient level, the valance band of the channel pushes up and gets aligned with
the conduction band and the holes are injected into the channel by tunnelling, and these holes
are swept to the drain region because the drain is negative biased
a is a cross section of p-type TFET with applied source (VS ), gate (VG ) and drain (VD ) voltages.

b Schematic energy band profile for the off state (dashed blue lines) and the on state (red lines)
in a p-type TFET. In the off state, no empty states are available in the channel for tunnelling from
the source, so the off current is very low. Decreasing VG moves the valence band energy (EV ) of
the channel above the conduction band energy (EC ) of the source so that interband tunnelling
can occur.

This switches the device to the on state, in which electrons in the energy window, ΔΦ (green
shading), can tunnel from the source conduction band into the channel valence band.
Electrons in the tail of the Fermi distribution cannot tunnel because no empty states are
available in the channel at their energy (dotted black line), so a slope of less than 60 mV
decade−1 can be achieved.

C indicates the schematic transfer characteristics

Performance parameters:
1. Subthreshold Swing (SS): The voltage required to change the current by
one order of magnitude (10x) in the subthreshold region.
TFET
- Achieves an SS < 60 mV/decade due to its quantum tunnelling
mechanism
-Enables ultra-low voltage operation and reduced power consumption.
2. ON-State Current (ION): The current flowing between the source and
drain when the transistor is fully ON
TFET
-has Lower ION due to limited tunnelling probability, typically in the range
of microamperes (µA).
-Not suitable for high-speed or high-performance applications.
3. OFF-State Current (IOFF ): The leakage current flowing when the
transistor is OFF.
TFET
-has Extremely low IOFF, almost negligible due to minimal thermal injection.
-Contributes to its ultra-low power consumption.
4. Other parameters
TFET device has other parameters such as source doping concentration,
gate dielectric, body thickness, and channel length and their impacts on
performance.
source doping should be slightly greater than drain to avoid an ambipolar
effect (happens when doping concentration of source and drain is equal as
they are opposite nature),and To increase Ion current
the gate dielectric thickness should be small,
a high dielectric material should be used, an optimum body thickness (10
nm to 20 nm)
an optimum channel length should be used to get the best performance
from TFET. If the channel length is reduced beyond a critical channel
length, a direct leakage current occurs from source to drain.

Applications:
Key Strengths of TFETs:
• Ultra-low power consumption.
• Excellent subthreshold slope (<60 mV/decade).
• High efficiency at low supply voltages.
So, it is used in application as
1. Low-Power IoT Devices (Internet of Things applications)
2. Wearable Electronics (like smartwatches, fitness trackers, and
medical monitoring devices)
3. Biomedical Devices (implantable devices such as pacemakers or
biosensors)
4. Memory Applications (used in non-volatile memory)
5. Extreme Low-Power Processors
FinFET (Fin field-effect transistor)
Structure:
-FinFET is a type of field-effect transistor (FET) that has a thin vertical fin
instead of being completely planar. The gate is fully “wrapped” around the
channel on three sides formed between the source and the drain. The
greater surface area created between the gate and channel provides better
control of the electric state and reduces leakage compared to planar FETs.
Using FinFETs, results in much better electrostatic control of the channel
and thus better electrical characteristics than planar FETs.
-They are 3D structures called “Tri-gate Transistors” and they can be
implemented either on bulk silicon or SOI wafer.
-In FinFET, the channel is vertical. So, the height of the channel determines
the width of the device. The perfect width of the channel is given by:
Width of Channel = 2 X Fin Height + Fin Width
Operation:
-Operates similarly to traditional MOSFETs but with enhanced gate control.
- The FinFET has 4 modes of operation: Short-Gate (SG) mode,
Independent-Gate (IG) mode, Low-Power (LP) mode and Hybrid mode.
1. Short-Gate (SG) Mode: The front gate and the back gate are shorted
together for better driving strength. If one of the input is affected, then the
operation would be controlled either by the front or back gate. This leads to
improving efficiency and achieving low leakage.
2. Independent-Gate (IG) Mode: The front gate and the back gate are given
two independent input voltages respectively to increase the flexibility in the
circuit design and to reduce the number of transistors.
3. Low-Power (LP) Mode: A low voltage is applied to n-type FinFET and a
high voltage is applied to p-type FinFET back gates. So, the threshold
voltage of the devices varies which reduces the leakage power dissipation.
4. Hybrid Mode: This mode is a combination of (IG) and (LP) modes. It has
the convenient properties of both the modes.
Operation of N-Type FinFET:
1 [Vgate < 0V, Vsource = 0V, Vdrain = +ve] (OFF-State):
• the channel remains non-conductive.
• The source and drain are isolated because the channel is not formed.
2 [Vgate > Vth, Vdrain = +ve, Vsource = 0V] (ON-State):
• When a gate voltage is applied, it creates an inversion layer along the
fin.
• The gate voltage induces a conductive channel in the fin, allowing
current to flow from the source to the drain.
• The tri-gate design ensures strong electrostatic control, reducing
leakage and short-channel effects.
3 Control of Current:
• The gate controls the channel width and thickness effectively due to
the 3D design.
• Higher gate voltage increases the carrier density in the channel,
enhancing current flow.
Performance parameters:
1. Subthreshold Swing (SS): The voltage required to change the current by
one order of magnitude (10x) in the subthreshold region.
FinFET
- Limited to 60 mV/decade due to its thermal carrier injection.
-Efficient but not as energy-saving as TFET.
2. ON-State Current (ION): The current flowing between the source and
drain when the transistor is fully ON
FinFET
-has High ION , typically in milliamperes (mA), due to strong carrier mobility
in the channel.
-Ideal for high-performance processors and applications.
3. OFF-State Current (IOFF ): The leakage current flowing when the
transistor is OFF.
FinFET
-Moderate IOFF , but significantly lower than traditional planar MOSFETs due
to its tri-gate design.
4. Power Consumption: The total power dissipated during operation,
influenced by both dynamic and static power.
-Higher power consumption than TFET, but much lower than planar
MOSFETs.
-Optimized for balancing performance and power in high-speed circuits.
I-V Characteristics of FINFET
Assignment (5):
Energy Band Diagram

At Equilibrium Under Applied Bias

-the PN junction is in a state of balance - Forward Bias: The bands flatten,
-The conduction and valence bands bend reducing the barrier for charge carriers,
near the junction, indicating the built-in facilitating current flow.
electric field. The Fermi level remains - Reverse Bias: The bands bend further,
constant across the structure, showing increasing the barrier and preventing
no net current flow. current flow except for a small leakage
current.
 At Equilibrium Under Applied Bias
1. The field is negative in this 1. Reduced Field at Forward Bias:
diagram, which indicates its In forward bias the electric field
direction is from the n-side to the magnitude decreases, which
p-side reduces the barrier for carrier
2. Peak Electric Field: The peak of movement. This leads to
the electric field is at the junction, increased current flow across the
where the charge separation is junction.
greatest. This is due to the built-in 2. Increased Field at Reverse
potential across the junction. Bias(if applicable) : In reverse
3. Depletion Region: The electric bias the electric field magnitude
field is confined to the depletion increases, which widens the
region. Outside this region, the depletion region and increases the
electric field is approximately zero barrier for carrier movement,
since there are no free charges to reducing current flow.
sustain it. 3. Impact on Depletion Width: The
bias affects the depletion width,
with forward bias reducing and
reverse bias increasing the width.

At Equilibrium Under Applied Bias

1- The potential increases sharply near 1- Forward Bias (Positive Voltage is
the depletion region, indicating the Applied):
presence of a built-in potential barrier. The external voltage reduces the built-in
2- The potential is constant in the neutral potential barrier, lowering the potential
regions (p-side and n-side), as no electric difference across the junction.( The
potential step becomes smaller)
field exists in these areas due to the 2- Reverse Bias (If Negative Voltage is
absence of net charge. Applied):
3- The height of the potential step The external voltage increases the built-in
corresponds to the built-in voltage of the potential, widening the potential step
junction. This is determined by the across the depletion region. (The
difference in Fermi levels of the p-side potential step becomes higher)
and n-side before contact. 3- Depletion Region Changes:
Forward bias narrows the depletion
region (lower barrier), while reverse bias
widens it (higher barrier).
4- Potential Gradient:
→Under forward bias, the slope of the
potential step decreases, indicating
reduced resistance to carrier flow.
→Under reverse bias (if applicable), the
slope becomes steeper, signifying a
stronger barrier against carrier flow.

C-V characteristic

1. Capacitance Rise: The capacitance increases with the gate voltage initially. This
behaviour is typical as the depletion region width decreases with increased forward
bias, leading to higher capacitance.
2. Peak Capacitance: The curve shows a peak in capacitance at around 0.4 V. This peak
can indicate the transition point where the depletion region reaches its minimum
width.
3. Capacitance Drop: After the peak, the capacitance decreases sharply. This might
suggest strong inversion or the onset of breakdown if the device is being pushed
beyond typical operating conditions.
4. Device Characteristics: The overall shape of the curve can be used to extract
parameters such as doping concentration and built-in potential.
 I-V characteristic
1. Threshold Voltage: The curve shows a sharp increase in current starting around 0.4 V.
This is likely the threshold or turn-on voltage of the diode, where it begins to conduct
significantly.
2. Forward Bias Region: Beyond the threshold voltage, the current increases
exponentially with voltage. This is typical for diodes, as they exhibit exponential I-V
characteristics in the forward bias region due to the p-n junction's behaviour.
3. Low Current Region: Before reaching the threshold voltage, the current remains very
low, indicating the diode is in the off state.
 At Equilibrium Under Applied Bias
1- The green curve represents the 1- reduction in the barrier
electrons density 2- enhanced carrier injection (typical in
2- The purple curve represents the holes forward bias conditions)
density 3- If reverse bias were applied instead,
3- The depletion width is Asymmetric as the depletion region would widen, and
NA>ND carrier densities near the junction would
decrease.
 Assignment 7

C-V characteristic
1- High-Frequency C-V Curve is the red curve:
The behaviour at inversion suggests that this is a high-frequency C-V curve. In
high-frequency measurements, minority carriers cannot respond to the AC signal,
resulting in the observed flat capacitance in inversion.
2- low-Frequency C-V Curve is the green curve:
At low frequencies, the minority carriers have enough time to respond to the AC
signal. As a result, in the inversion region, the capacitance in the low frequency
curve increases and approaches the oxide capacitance (Cox)
3- Oxide Capacitance (Cox ):
The maximum capacitance value in the accumulation region corresponds to Cox,
which depends on the oxide thickness (tox) and permittivity (εox).
4- Threshold Voltage (Vth ):
The threshold voltage can be determined as the gate voltage at which the
transition into inversion occurs.
 Assignment 8

Comments
1- Threshold Voltage Behavior:
→ The curve shows a clear transition region where the surface potential (Φs) sharply
increases with gate voltage (VG).
→ This transition indicates the threshold voltage (Vth) of the MOS capacitor, marking the onset
of strong inversion.
2- Subthreshold Region (VG <Vth):
→For negative and slightly positive gate voltages, the surface potential remains relatively low
and changes slowly.
3- Strong Inversion Region (VG >Vth):
→At gate voltages beyond the threshold voltage, the surface potential flattens out and
approaches a saturation level.
 MATLAP code:
% MOS Structure Simulation - Plot 1: VG vs phi_s
% Constants Definition
K = 1.3806e-23; % Boltzmann constant (J/K)
T = 300; % Temperature (K)
q = 1.6021e-19; % Electron charge (C)
epsilon_0 = 8.85e-14; % Permittivity of free space (F/cm)
epsilon_Si = 11.8 * epsilon_0; % Permittivity of silicon (F/cm)
epsilon_SiO2 = 3.9 * epsilon_0; % Permittivity of SiO2 (F/cm)

% Silicon Parameters
ni = 1e11; % Intrinsic carrier concentration (cm^-3)
NA = 4e15; % Doping concentration (cm^-3)
V_bulk = 0; % Bulk potential (V)

% Oxide Parameters
t_ox = 5.5e-7; % Oxide thickness (cm)
C_ox = epsilon_SiO2 / t_ox; % Oxide capacitance per unit area (F/cm^2)
phi_f = (K * T / q) * log(NA / ni); % Fermi potential (V)

% Input Range for Surface Potential

phi_s = -0.4:0.01:1.2; % Surface potential (V)
phi_s_length = length(phi_s);

% Preallocate Arrays for Outputs

Qs = zeros(phi_s_length, 1); % Charge density (C/cm^2)
VG = zeros(phi_s_length, 1); % Gate voltage (V)
psi_B = phi_f * ones(phi_s_length, 1); % Bulk potential (V)

% Calculate Qs and VG for Each Surface Potential

A = sqrt(2 * epsilon_Si * K * T * NA); % Constant factor in Qs equation

for i = 1:phi_s_length
% Intermediate calculations
exp_phi_s = exp(phi_s(i) * q / (K * T));
term1 = exp(-phi_s(i) * q / (K * T)) + phi_s(i) * q / (K * T) - 1;
term2 = (ni^2 / NA^2) * (exp_phi_s - phi_s(i) * q / (K * T) - 1);
B = sqrt(term1 + term2);

% Qs and VG calculations
if phi_s(i) <= 0
Qs(i) = A * B;
else
Qs(i) = -A * B;
end
VG(i) = V_bulk + phi_s(i) - Qs(i) / C_ox;
end
% Plot VG vs. phi_s
figure;
plot(VG, phi_s, 'b-', 'LineWidth', 1.5);
hold on;
plot(VG, 2 * psi_B, 'r--', 'LineWidth', 1.5);
xlim([-3, 10]);
ylim([-0.4, 1]);
xlabel('V_G (V)');
ylabel('\phi_s (V)');
grid on;
plot(-10:10, zeros(1, 21), 'k--');
plot(zeros(1, 21), -10:10, 'k--');
legend('\phi_s', '2\psi_B', 'Location', 'NorthWest');
title('Surface Potential vs.Gate Voltage');
 Assignment 9

Comments
1. Curve Characteristics:
o As Φs increases from negative to positive values, the charge density
initially decreases, reaches a minimum, and then increases again.
2. Regions of Operation:
o Accumulation: For negative surface potential (Φs<0), the charge density is
high. This indicates a high density of majority carriers accumulating at the
surface.
o Depletion: Near Φs=0 (tell reaching Φf), the charge density is at its
minimum. This corresponds to the depletion region where the majority
carrier concentration is reduced.
o Inversion: For positive Φs, the charge density increases slowly in weak
inversion then sharply, indicating the onset of inversion where minority
carriers dominate (strong inversion).
 MATLAP code:

K = 1.3806e-23; % Boltzmann constant (J/K)

T = 300; % Temperature (K)
q = 1.6021e-19; % Electron charge (C)
epsilon_0 = 8.85e-14; % Permittivity of free space (F/cm)
epsilon_Si = 11.8 * epsilon_0; % Permittivity of silicon (F/cm)
epsilon_SiO2 = 3.9 * epsilon_0; % Permittivity of SiO2 (F/cm)

ni = 1e11; % Intrinsic carrier concentration (cm^-3)

NA = 4e15; % Doping concentration (cm^-3)
V_bulk = 0; % Bulk potential (V)
t_ox = 5.5e-7; % Oxide thickness (cm)
C_ox = epsilon_SiO2 / t_ox; % Oxide capacitance per unit area (F/cm^2)
phi_f = (K * T / q) * log(NA / ni); % Fermi potential (V)

phi_s = -0.4:0.01:1.2; % Surface potential (V)

phi_s_length = length(phi_s);

Qs = zeros(phi_s_length, 1); % Charge density (C/cm^2)

A = sqrt(2 * epsilon_Si * K * T * NA); % Constant factor in Qs equation

for i = 1:phi_s_length
% Intermediate calculations
exp_phi_s = exp(phi_s(i) * q / (K * T));
term1 = exp(-phi_s(i) * q / (K * T)) + phi_s(i) * q / (K * T) - 1;
term2 = (ni^2 / NA^2) * (exp_phi_s - phi_s(i) * q / (K * T) - 1);
B = sqrt(term1 + term2);

% Qs calculation
if phi_s(i) <= 0
Qs(i) = A * B;
else
Qs(i) = -A * B;
end
end

figure;
semilogy(phi_s, abs(Qs) / q, 'g-', 'LineWidth', 1.5);
hold on;
xlim([-0.4, 1]);
ylim([1e10, 1e14]);
xlabel('\phi_s (V)');
ylabel('|Q_s| / q (cm^-2)');
grid on;
plot(zeros(1, 21), logspace(10, 16, 21), 'k--');
title('Charge Density vs. Surface Potential');
 2nd Milestone: Project
▪ Team members:

Name Code Section

Mohamed Nader Baz 2100405 2
Mahmoud Hossam Mohamed Ahmed 2101408 2
Mostafa Medhat Mohamed 2100731 2

▪ Project:
➢ Simulation of advanced Solid-State Devices (TFET: Nanowire Gate-All-Around
Tunnel Field-Effect Transistor) using SILVACO TCAD tools.

▪ Introduction:
➢ This project focuses on the simulation of advanced solid-state devices, specifically
the Cylindrical Nanowire Gate-All-Around Tunnel Field-Effect Transistor (NW-GAA-
TFET), using SILVACO TCAD tools. The NW-GAA-TFET is a promising candidate for
low-power and high-performance applications due to its superior electrostatic
control and efficient carrier tunneling mechanism.
▪ Objective:
1. To simulate the electrical characteristics of the NW-GAA-TFET.
2. To analyze the energy band diagrams and electric field distributions.
3. To evaluate the device performance under different biasing conditions.

▪ Methodology:
1. Device Structure: The NW-GAA-TFET is modeled with a cylindrical nanowire
structure, providing gate-all-around control for enhanced electrostatic
performance.

2. Simulation Tools: SILVACO TCAD tools are used for the simulation, including device
modeling, meshing, and solving semiconductor equations.
3. Parameters: Key parameters such as doping concentrations, oxide thickness, and
gate materials are defined to accurately represent the device.
 ▪ Script (code) used in SILVACO TCAD:
# SILVACO 2D Cylindrical NW-GAA-TFET #
go atlas

####### VARIABLES ############################################################

#Channel Length
set Lg=.200

#Radius
set R=.035

#Oxide Thickness
set tOX=.0045

#Source Doping
set doping_p=1e19

#Drain Doping
set doping_n=1e19

#Channel Doping
set doping_channel=1e17

#Gate Metal Work Function

set gate_wf=4

#Insulator Permittivity
set insul_perm=25

#Drain and Source Length

set Lds=.080
#
####### MESH #################################################################
#
MESH CYLINDRICAL
#
X.MESH loc=0.0 spacing=.01
X.MESH loc=$R-.005 spacing=.001
X.MESH loc=$R spacing=.0005
X.MESH loc=$R+.005 spacing=.01
X.MESH loc=$R+$tOX+.0015 spacing=.01

Y.MESH loc=0 spacing=.02

Y.MESH loc=0.01 spacing=.02
Y.MESH loc=$Lds-.005 spacing=.001
Y.MESH loc=$Lds spacing=.0001
Y.MESH loc=($Lg+$Lds)/2 spacing=.02
Y.MESH loc=$Lg+$Lds spacing=.01
Y.MESH loc=$Lg+$Lds+.005 spacing=.01
Y.MESH loc=$Lg+$Lds+$Lds-.01 spacing=.02
Y.MESH loc=$Lg+$Lds+$Lds spacing=.02
#
####### REGIONS ##############################################################
#
# Source Left
REGION NUM=1 NAME=Source MATERIAL=silicon \
Y.MIN=0.01 Y.MAX=$Lds X.MIN=0 X.MAX=$R

# Channel Right
REGION NUM=3 NAME=Channel MATERIAL=silicon \
Y.MIN=$Lds Y.MAX=$Lg+$Lds X.MAX=$R

# Drain right
REGION NUM=4 NAME=Drain MATERIAL=silicon \
Y.MIN=$Lg+$Lds Y.MAX=$Lg+$Lds+$Lds-.01 X.MAX=$R

# Gate Oxide
REGION NUM=5 MATERIAL=sio2 \
Y.MIN=$Lds Y.MAX=$Lg+$Lds X.MIN=$R

# Source Air Left

REGION NUM=6 MATERIAL=air \
Y.MIN=0 Y.MAX=$Lds X.MIN=$R

# Drain Air right

REGION NUM=7 MATERIAL=air \
Y.MIN=$Lg+$Lds Y.MAX=$Lg+$Lds+$Lds X.MIN=$R
#
####### ELECTRODES ###########################################################
#
ELECTRODE NAME=SOURCE MATERIAL=Aluminum \
Y.MIN=0 Y.MAX=.01 X.MIN=0 X.MAX=$R

ELECTRODE NAME=DRAIN MATERIAL=Aluminum \

Y.MIN=$Lg+$Lds+$Lds-.01 Y.MAX=$Lg+$Lds+$Lds X.MIN=0 X.MAX=$R

ELECTRODE NAME=GATE MATERIAL=Aluminum \

Y.MIN=$Lds Y.MAX=$Lg+$Lds X.MIN=$R+$tOX X.MAX=$R+$tOX+.0015
#
####### DOPING ###############################################################
#
DOPING GAUSSIAN material=Si p.type concentration=$doping_channel \
Y.min=$Lds Y.max=$Lds+$Lg X.max=$R \
Y.char=0.01 X.char=0

DOPING GAUSSIAN material=Si p.type concentration=$doping_p \

Y.min=0.01 Y.max=$Lds X.max=$R \
Y.char=0.025 X.char=0

DOPING GAUSSIAN material=Si n.type concentration=$doping_n \

Y.min=$Lds+$Lg Y.max=$Lg+$Lds+$Lds-.01 X.max=$R \
Y.char=0.025 X.char=0
#
####### QUANTUM MESH #########################################################
#
qtx.mesh loc=0 spac=0.0050
qtx.mesh loc=$R-.005 spac=0.0005
qtx.mesh loc=$R spac=0.0001

qty.mesh loc=$Lds-.050+.01 spac=0.00025

qty.mesh loc=$Lds+.01 spac=0.00010
qty.mesh loc=$Lds+.050+.01 spac=0.00025
#
####### MODELS ###############################################################
#
material material=Si me.tunnel=.22 mh.tunnel=.12
material material=SiO2 permittivity=$insul_perm
contact name=GATE workfunc=$gate_wf

models qtunn.dir=ydir bbt.nonlocal temperature=300 \

fermi ni.fermi srh auger cvt \
fldmob conmob bgn print

method itlimit=5

output band.temp band.param traps u.srh j.electron j.hole j.total qfn qfp
OUTPUT CON.BAND VAL.BAND
#
####### CALCULATIONS #########################################################
#
Loop steps=2

# Fig. 3b in [1] Id-Vg characteristics values

assign name=Vn n.value=(1.2, .05)

solve init

solve name=DRAIN vDRAIN=0 vstep=0.025 vfinal=$Vn

save outf=quantumex24_Vg0_Vd$'Vn'.str

log outf=quantumex24_idvg_Vd$'Vn'.log
solve name=GATE vGATE=-0.0 vstep=-.05 vfinal=-.5
solve name=GATE vGATE=-0.5 vstep=0.05 vfinal=1.5

save outf=quantumex24_Vg1.5_Vd$'Vn'.str

log off

L.END
#
####### TONYPLOT #############################################################
#
tonyplot quantumex24_Vg1.5_Vd1.2.str
tonyplot -overlay quantumex24_idvg_Vd0.05.log quantumex24_idvg_Vd1.2.log \
-set quantumex24.set

quit
 ▪ parameters:
Parameters Value
Channel length 0.2 um
Radius 0.035 um
Oxide thickness 0.0045 um
Source doping 1019
Drain doping 1019
Channel doping 1017
Metal work function 4
Insulator permittivity 25
Drain and source length 0.080 um

▪ Device characteristics:

In this section, a description of the key aspects of the device is provided with a graph
representing variation across the device, focusing on the following elements:

1. Layout: The structural design and material composition of the device.

2. Energy Band Diagram: The energy band profile across the device under various bias
conditions.
3. Electric Field: The spatial distribution of the electric field and its role in device
operation.
4. Electric Potential: The potential variation across the device and its impact on
carrier transport.
5. Doping: The doping profile and its influence on the device’s characteristics.
6. I-V Characteristics: The current-voltage behavior that illustrates the device's
operational performance.
7. Tunneling: The band-to-band tunneling mechanism, highlighting its efficiency and
significance in the device operation.
▪ Layout:

Source

Gate
Drain

Comments:
• Structure and Composition: The layout clearly represents the NW-GAA-TFET
structure, highlighting the key regions: Source, Drain, and Gate. The material
distribution (Silicon, SiO₂, Air, and Aluminum) .
• Device Dimensions: The nanometer-scale dimensions ensure compatibility with
modern device scaling requirements. The compactness of the layout enables
efficient electrical control and minimized parasitics.
• Material Significance: The high-k dielectric (likely SiO₂) at the gate ensures better
control of the channel and minimizes gate leakage currents, enhancing the overall
device performance.
 ▪ Energy band diagram:

Comments:

The energy band diagram of the (NW-GAA-TFET) illustrates its operating principle: band-to-
band tunneling (BTBT):

• Conduction and Valence Bands: Sharp bending near the tunneling junction
indicates strong gate control and electric fields, enabling efficient tunneling for
current flow.
• Quasi-Fermi Levels: Show the non-equilibrium carrier distribution due to applied
bias, with electron and hole flow driven by band alignment.
• Regions of Operation:

➢ Source Region: No tunneling occurs as conduction and valence

bands are well-separated.
➢ Tunneling Junction: Strong band bending allows tunneling.
➢ Drain Region: Flattened bands indicate carrier flow to the drain.
▪ Electric field:

Comments:
• The graph is consistent with the operation of a NW-GAA-TFET. The electric
field is positive throughout due to the applied bias conditions and the device's
unidirectional operation. The sharp peak at the tunneling region highlights
efficient band bending for tunneling, and the gradual decay ensures reduced
leakage in the off state.
• Tunneling Efficiency: The high electric field at the tunneling junction reduces
the energy barrier width, facilitating efficient tunneling of carriers.
• Gate Control: The positive electric field reflects strong gate control over the
channel, a key feature of the GAA structure.
• Low Leakage: Outside the tunneling region, the field diminishes, reducing
leakage currents in the off state.
• Why Positive?
The direction of the electric field is defined as positive when it points in the
direction of electron acceleration (or from higher potential to lower potential):
• Source to Drain: The positive gate and drain biases create a field that
accelerates electrons from the source toward the drain.
• Band Bending: This aligns with the steep energy band slope in the tunneling
region (as seen in the previous energy band diagram).
 ▪ Electric Potential:

Comments:

• Tunneling Region: The sharp potential rise at the tunneling junction indicates strong
gate control and efficient tunneling conditions.
• Low Power Operation: The gradual potential increase across the channel and the
drain region ensures minimized leakage and efficient current flow.
• Gate Control: The steep potential increase in the tunneling region demonstrates
the influence of the gate on modulating the channel potential.
▪ Doping
Comments:
• Non-Uniform Doping: The doping profile is not uniform, exhibiting regions with
varying doping concentrations. This is typical in NW-GAA-TFETs to achieve desired
device characteristics.
• Channel Region: It's the region with a low or moderate doping concentration
corresponds to the channel region. This is crucial for controlling the flow of current
between the source and drain.
• Source/Drain Regions: The regions with higher doping concentrations are the
source and drain regions. These heavily doped regions provide a high carrier
concentration for efficient injection and collection of charge carriers.

• Channel Engineering: The non-uniform doping profile is likely designed to optimize

the channel properties for better device performance. For instance, a lightly doped
channel can reduce short-channel effects and improve subthreshold swing.

• Gate Control: The precise doping profile around the gate region is critical for
achieving strong gate control over the channel current. This is a key factor in
determining the device's performance metrics such as on-current, off-current, and
subthreshold swing.
▪ I-V characteristic:

Comments:

1. Subthreshold Region:
- For both Vd = 0.05V and Vd = 1.20V, at lower gate voltages (Vg), the drain current
(Id) remains very low. This indicates the device is in the subthreshold region, where
the channel is not fully turned on.

2. Threshold Voltage (Vt):

- The threshold voltage (Vt) is the gate voltage at which the device starts to conduct
appreciable current. In this curve, Vt appears to be around 0.2V for both drain
voltages.

3. Linear Region:
- As Vg increases beyond Vt, the device enters the linear region. Here, Id increases
linearly with Vg. This region is characterized by a low drain voltage, where the
channel resistance is relatively high.

4. Saturation Region:
- For higher Vg values, the device enters the saturation region. In this region, Id
starts to saturate and becomes less sensitive to further increases in Vg. This is due
to velocity saturation of the carriers in the channel.
▪ Tunneling rate:

Comments:
• The plot is characteristic of the NW-GAA-TFET, showing the nonlocal band-to-
band tunneling (BBT) rates for electrons and holes. The sharp peaks correspond
to efficient tunneling regions, whereas the flat regions represent reduced leakage
in the off state.
• Tunneling Dynamics: The steep rise and decay in the BBT rates highlight a strong
electric field in the tunneling region, ensuring a high tunneling current while
minimizing leakage outside this region.
• Gate Control: The distinct difference between electron and hole tunneling rates
indicates effective gate modulation, aligning with the unidirectional behavior of
the device.
• Low Leakage Behavior: Beyond the tunneling junction, the tunneling rates
diminish rapidly, reflecting strong suppression of leakage currents in the off state,
which is crucial for low-power operation.
• Bias Dependence: The observed tunneling behavior aligns with the applied bias
conditions, ensuring efficient operation under designed electrical parameters.
 ▪ Conclusion:

The simulation of the Cylindrical Nanowire Gate-All-Around Tunnel Field-Effect Transistor

(NW-GAA-TFET) using SILVACO TCAD tools has provided valuable insights into the device's
performance and potential for low-power applications. Here are the detailed conclusions
drawn from the study:

1. Superior Electrostatic Control:

o The NW-GAA structure offers enhanced electrostatic control over the
channel compared to traditional planar devices. This is evident from the
sharp band bending observed in the energy band diagrams, which facilitates
efficient band-to-band tunneling (BTBT).
2. Efficient Carrier Tunneling:
o The energy band diagrams, and electric field distributions highlight the
efficient carrier tunneling mechanism in the NW-GAA-TFET. The strong
electric field at the tunneling junction reduces the energy barrier width,
enabling effective tunneling of carriers even at low operating voltages.
3. Low Power Operation:
o The NW-GAA-TFET demonstrates excellent potential for low-power
applications. The steep band bending and strong gate control result in a
subthreshold swing below 60 mV/decade, which is significantly better than
conventional MOSFETs. This allows for reduced power consumption while
maintaining high performance.