Towards Machine Learning for Placement and Routing in Chip Design: a

Methodological Overview
Junchi Yan1∗ , Xianglong Lyu1 , Ruoyu Cheng1 , Yibo Lin2∗
1
Department of CSE, and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University
2
Department of EECS, Peking University
{yanjunchi,kyle lyu,roy account}@sjtu.edu.cn [email protected]
arXiv:2202.13564v1 [cs.LG] 28 Feb 2022

Abstract Placement can be regarded as a much more compli-

cated variation of 2D bin packing problem with geo-
Placement and routing are two indispensable and metrical constraints. The latter is known to be NP-
challenging (NP-hard) tasks in modern chip de- hard [Hartmanis, 1982]. The objective of placement is corre-
sign flows. Compared with traditional solvers using lated to both the logical interconnection of the circuit design
heuristics or expert-well-designed algorithms, ma- and the geometrical locations of logical components. As the
chine learning has shown promising prospects by quality of a placement solution cannot be accurately evalu-
its data-driven nature, which can be of less reliance ated until routing, resulting in a long feedback loop in the de-
on knowledge and priors, and potentially more sign flow, modern placement needs to reduce routing conges-
scalable by its advanced computational paradigms tion and improve routability in early stage. Routing has been
(e.g. deep networks with GPU acceleration). This proven to be an NP-hard problem [Hartmanis, 1982], even in
survey starts with the introduction of basics of the simplest case with only a few two-pin networks. Given
placement and routing, with a brief description on the placement solution, it connects the pins of millions of net-
classic learning-free solvers. Then we present de- works with physical wires subjecting to the limited routing
tailed review on recent advance in machine learning resources and complicated geometrical design rules. Routing
for placement and routing. Finally we discuss the is tightly coupled with placement and an excellent placement
challenges and opportunities for future research. solution leads to better chip area utilization, timing perfor-
mance, and routability.
There are also surveys on routing and placement.
1 Introduction [Huang et al., 2021] summaries a comprehensive review of
The scale of integrated circuits (ICs) has increased dramati- existing ML studies for EDA field, most of which belongs
cally, posing a challenge to the scalability of existing Elec- to the four categories: decision making in traditional meth-
tronic Design Automation (EDA) techniques and technolo- ods, performance prediction, black-box optimization, and au-
gies. The increasing circuit density incurs additional issues tomated design, ordered by increasing degree of automation.
for very large scale integration (VLSI) placers and routers as Although it covers various stages in the EDA flow, it pro-
the feature size of modern VLSI design continues to drop and vides shallow analysis for specific tasks, placement and rout-
on-chip connectivity gets increasingly sophisticated. Due to ing, compared to ours. [Hamolia and Melnyk, 2021] intro-
increased on-chip connectivity, concentrated needs, and re- duces the ISPD 2015 dataset for comparison between classic
stricted resources, modern designs are prone to congestion methods and ML algorithms. [Rapp et al., 2021] categorizes
issues and wire-length minimization, which has become a how ML may be used and is used for design-time/run-time
critical task at every stage of the design process. Accord- optimization and exploration strategies of ICs, along with
ingly, placement and routing – the elements of the design cy- trends in the employed ML algorithms. [Markov et al., 2015]
cle physically arranges the locations and the courses of nets – reviews the history of placement research and the progress
becomes more crucial in modern VLSI. leading up to the state of the art. However, they only consider
Placement and routing are two of the most critical but time- classic placer in the past 50 years, which is complementary to
consuming steps of the chip design process. Placement as- our survey which focuses on learning-based placer in recent
signs various logic components like logic gates and functional years.
blocks into discrete sites in the physical layout of a chip, and
routing finishes the physical wiring of interconnections. The
goal of placement and routing is to optimize power, perfor- 2 Problem Background and Classic Solvers
mance, and area (PPA) metrics within constraints, e.g., place-
ment density and routing congestion. This section starts with the problem formulation and main-
stream solvers which are traditionally learning-free. We then
∗
Correspondence author. introduce recent applicable learning techniques.
 Cell Placement multiple metal layers are adopted for routing, a vertical di-
Macro Global Detailed Global Detailed mension is introduced to the grid graph, where abutting metal
Placement Placement Placement Routing Routing layers are connected through vias in the 3D grid graph.
Detailed Routing works on a fine-grained 3D grid graph
Placement Routing
compared with global routing, considering complicated de-
Figure 1: Example of a simplified placement and routing flow. sign rules. Each grid edge provides unit routing resource such
that a detailed routing path on the grid does not violate the de-
2.1 Placement Problem sign rules like minimum metal width and spacing. Detailed
routing also needs to consider preferred routing directions,
Placement can be performed at different levels. In general, where abutting routing layers prefer perpendicularly routing
the global placement involves macro placement and standard directions. Consecutive grid edges following the preferred di-
cell placement, as shown in Figure 1. The detailed placement rection (e.g., in X or Y direction) of their corresponding layer
includes legalization, wirelength and routability refinement. are described as a routing track. Typical detailed routing algo-
Global Placement. It is one of the most crucial but time- rithms take global routing segments as guidance. Each global
consuming steps in the chip design process, which can be routing segment provides rough hints for the topologies of
cast as a constrained optimization problem. It assigns ex- nets, and detailed routing needs to finalize the actual routing
act locations for various components of a netlist including paths on the fine-grained grid graph. Nets unable to be routed
macros and standard cells within the chip layout. Standard without conflicts on the grid graph can cause design rule vio-
cells are basic logic cells, i.e., logic gates, and macros are pre- lations, which is a widely-used metric to describe the quality
designed IP blocks, e.g., SRAMs. A good placement leads to of detailed routing solutions or how congested a design is.
better chip area utilization, timing performance, and routabil-
ity, while inferior placement assignment will affect the chip’s 2.3 Classic Placement Solvers
performance and even make it nonmanufacturable. The history of VLSI placement can trace back to the
Formally, the input of global placement is a netlist that 1960s [Breuer, 1977; Fiduccia and Mattheyses, 1982], when
can be represented by hypergraph H = (V, E), where partition-based methods adopted the idea of divide-and-
V = {v1 , v2 , · · · , vn } denotes set of nodes (cells), and conquer: netlist and chip layout are partitioned recursively
E = {e1 , e2 , · · · , em } denotes set of hyperedges (nets). Hy- until the sublist can be solved by optimal solvers. This hi-
peredge ei ∈ E is a subset of nodes. We seek to deter- erarchical structure makes them fast to execute and natu-
mine locations of macros and standard cells (xi , yi ) which ral to extend for larger netlists at the cost of solution qual-
are further combined into two vectors ~x = (x1 , . . . , xn ) ity, since each sub-problem is solved independently. Multi-
and ~y = (y1 , . . . , yn ). Wirelength minimization is one of level partitioning methods based on Fiduccia–Mattheyses
the main objectives for placement. HPWLN (~x, ~y ) is usually heuristics [Agnihotri et al., 2005; Caldwell et al., 2000] were
adopted to approximate wirelength during placement as: developed afterwards. Analytical placers appeared in
X  the early 1980s, but were eclipsed by annealing meth-
HP W L = max xj − min xj + max yj − min yj ods [Kirkpatrick et al., 1983] inspired from annealing in
vj ∈ei vj ∈ei vj ∈ei vj ∈ei
ei ∈E metallurgy that involves heating and controlled cooling
for optimal crystalline surfaces. In practice, simu-
Detailed Placement. Solution from global placement is lated annealing (SA) optimizes a given placement solu-
often illegal: cells may overlap or occupy illegal sites, e.g. tion by random perturbations with actions such as shift-
between placement rows. This is because global placers are ing, swapping and rotation of macros [Ho et al., 2004;
unaware of these constraints. Detailed placement performs Shunmugathammal et al., 2020]. Although SA is flexible
legalization and quality refinement. The legalization removes and able to find the global optimum, it is time-consuming
overlaps between cells and snaps them to the sites of rows and hard to deal with the ever-increasing scale of circuit.
with minimum adverse impact on placement quality. The re- Later, analytical techniques have matured including force-
finement then takes a legal placement and further improves directed methods [Spindler et al., 2008] and non-linear op-
objectives wirelength and routability by locally moving cells. timizers [Chen et al., 2008b; Kahng and Wang, 2005]. In
comparison, the quadratic methods are efficient but show
2.2 Routing Problem relatively worse performance, while non-linear optimiza-
Routing often involves two cases: global and detailed routing. tion approximates the cost functions more smoothly with
Global Routing connects wires with metal resources on the cost of higher complexity. Recently, however, mod-
a grid graph G(V, E) representing the physical layout of a ern analytical placers e.g. ePlace [Lu et al., 2015] and
chip. Essentially, the physical layout is divided into rectangu- RePlAce [Cheng et al., 2018a] introduce electrostatics-based
lar areas with each area corresponding to a global routing cell global-smooth density cost function and Nesterov’s method
(G-Cell), denoting each vertex vi ∈ V . Each edge eij ∈ E nonlinear optimizer that achieve superior performance on
represents the joint boundary between abutting G-Cells vi and public benchmarks. They formulate each node of the netlist
vj . The capacity for an grid edge e, ce , is defined as the maxi- as positively charged particle. Nodes are adjusted by their
mum number of wires that can cross the grid edge. The usage repulsive force and the density function corresponds to sys-
ue is defined as the actual number of wires crossing the grid tem’s potential energy. These analytical methods update posi-
edge. The overflow oe is defined as max(0, ue − ce ). When tions of cells in gradient based optimization scheme and gen-
erally can handle millions of standard cells by parallelization based bounded-length min-cost topology improvement
on multi-threaded CPUs using partitioning to reduce the run algorithm that enables Steiner trees to change dynamically
time. for congestion optimization. NTUgr [Chen et al., 2009]
With increasing design complexity, optimizing tradi- replaces iterative NRR by enhanced iterative forbidden-
tional placement metrics (HPWL) alone is insufficient in region rip-up/rerouting (IFR). FastRoute [Pan et al., 2012],
practice [Alpert et al., 2010]. Therefore, routability-driven on the other hand, integrates several novel techniques:
placers are proposed to emphasize on routing failures. fast congestion-driven via-aware Steiner tree construction,
SimPLR [Kim et al., 2011] develops lookahead routing to 3-bend routing, virtual capacity adjustment, multisource
temporarily bloat cells, modulate target aspect ratio of multi-sink maze routing, and spiral layer assignment.
cell placement areas, and modify anchor positions dur- NTHU-Route 2.0 [Chang et al., 2010] improves NTHU-
ing quadratic placement. NTUPlace4 [Hsu et al., 2011] Route [Gao et al., 2008], an earlier version by a new
adopts probabilistic congestion estimation when modeling history-based cost function and new ordering methods for
pin density. There are also other optimization direc- congested region identification and rip-up and reroute.
tions such as timing-driven placement for optimizing cir- NCTU-GR 2.0 [Liu et al., 2013] outperforms the foregoing
cuit delay [Riess and Ettelt, 1995; Luo et al., 2006] and IC global routers by applying two bounded-length maze routing
power optimization for circuit power [Cheon et al., 2005; (BLMR) algorithms (i.e. optimal-BLMR and heuristic-
Lee and Markov, 2012]. Another trend is the increasingly BLMR), a rectilinear Steiner minimum tree aware routing
extensive use of intellectual property (IP) modules and pre- scheme , a collision-aware rip-up and rerouting scheme and
designed macro blocks. As a result, mixed-size place- a 3-D wire length optimization technique.
ment tools are becoming indispensable for physical design.
[Taghavi et al., 2005] proposes a hierarchical method to place Detailed Routing Solvers
large scale mixed size designs that may contain thousand of Since the 1970s, detailed routing has been exten-
macro blocks and millions of standard cells, based on min-cut sively researched (e.g. [Yoshimura and Kuh, 1982])
partitioning and simulated annealing which are both aware of , and rip-up and reroute, such as the one in
large macro cells. [Chen et al., 2008a] designs a novel con- Mighty [Shin and Sangiovanni-Vincentelli, 1987] has
straint graph-based macro placement algorithm that removes been the most common technique for detailed routing.
macro overlaps and optimizes macro positions and orienta- Nevertheless, when dealing with congested designs, such a
tions effectively and efficiently for modern mixed-size circuit sequential net-by-net method is unproductive and frequently
designs. results in unneeded detours. DUNE [Cong et al., 2001] and
MR [Chang and Lin, 2004] develop multilayer techniques
2.4 Classic Routing Solvers to handle full-chip gridless routing, in which the routing
Global Routing Solvers passes through a coarsening and uncoarsening phase. These
The global routing approaches can be divided into two types: multilevel routers, however, continue to use the sequential
concurrent and sequential. The sequential approach has been rip-up and reroute technique. Several attempts have been
proved to be very effective in practice and considerably faster made to evaluate nets more concurrently during detailed
than the concurrent approach, but it highly relies on the order- routing. Based on Boolean satisfiability, [Nam et al., 2002]
ing of the nets and thus, being prone to a sub-optimal solution. suggests a thorough FPGA router which delivers exceedingly
Concurrent approaches attempt to handle numerous nets long runtime despite good solution quality. Track assignment
simultaneously but are typically too expensive to be ap- is introduced in [Batterywala et al., 2002] as a step between
plied on today’s large designs, which may contain up to a global and detailed routing. Segments taken from the
million nets. BoxRouter [Cho and Pan, 2007] implements global routing solution are assigned to routing tracks in
progressive integer linear programming (ILP) and adaptive track assignment. [Ozdal, 2009] introduces an ingenious
maze routing to effectively diffuse the congestion. How- method for doing escape routing for dense pin clusters,
ever, its progressive ILP routing formulation only covers which is a major bottleneck in detailed routing. However, the
L-shape patterns, and it fails in difficult scenarios when technique is not recommended for solving detailed routing
most nets must be detoured in complex patterns. On top on a whole-chip scale. Routing frameworks based on rules
of it, BoxRouter 2.0 [Cho and Pan, 2007] further provides are well-suited to traditional design flow and have been in use
more powerful and systematic way of eliminating conges- for decades. To execute correct pin access, [Nieberg, 2011]
tion and assigning layers to wires. GRIP [Wu et al., 2009; computes various pin access path candidates and selected the
Wu et al., 2010] is based on a partitioning strategy in a full shortest paths from pins to grid points that did not violate
3D manner and obtains the best wirelength among the open any design criteria. RegularRoute [Zhang and Chu, 2011]
literature, but when compared to other recent global routers, frames the global segment assignment problem inside
GRIP requires prohibitive overall runtime. each group of routing tracks as a maximum weighted
Sequential approaches often use net decomposi- independent set problem, then used regular routing pat-
tion [Chu and Wong, 2007], maze routing [Lee, 1961], terns in a bottom-up layer-by-layer framework. Under
pattern routing [Kastner et al., 2002], or negotiation-based self-aligned double patterning limitations, [Xu et al., 2016]
rip-up and rerouting (NRR), and only one net is routed suggests a pin access-driven rip-up and reroute scheme.
at a time. Archer [Ozdal and Wong, 2009] explores the For mixed-cell-height circuits, [Li et al., 2018] introduces a
congestion histories, and adopts a Lagrangian relaxation- pin access-aware legalizing technique. Due to the spirited
ISPD’18 and ISPD’19 routing contest [Mantik et al., 2018; placement with the subsequent routing task, they also de-
Liu et al., 2019], some new work has been completed. velop a joint learning approach DeepPR via RL to fulfill both
[Kahng et al., 2018] divides each layer into parallel panels placement and routingfor macros. Table 2 compares learning-
and expressed the routing problem as an integer linear pro- based placers in terms of placement target and learning pro-
gram on each panel. [Sun et al., 2018] modifies the notion tocol.
of hit points and employs through violations to assign tracks.
Dr. CU [Chen et al., 2019] proposes an algorithm for finding 3.3 Prediction Model Embedded in Placement
the best path while keeping the minimum-area requirement ML also assists placers to optimize complicated objectives
in mind. The subsequent Dr. CU 2.0 [Li et al., 2019] like routability by embedding prediction models, as it is dif-
handles hard-to-access pins and new design rules including ficult to foresee routing congestion accurately during place-
length-dependent parallel run length spacing, end-of-line ment. [Huang et al., 2019] proposes the first routability
spacing with parallel edges, and corner-to-corner spacing. driven macro placement with deep learning. A CNN-based
routability prediction model is proposed and embedded into
3 Machine Learning for Placement a macro placer such that a good macro placement with
minimized design rule check (DRC) violations can be de-
3.1 Traditional Placers Enhancement rived through SA optimization process. [Chan et al., 2017]
presents a learning based algorithm to predict DRC violations
Most traditional placers mentioned above perform heavy nu- in detailed routing and automatically improve the routabil-
merical computation for large-scale optimization problem on ity of these designs. [Liu et al., 2021b] predicts congestion
the CPUs, which lacks exploration of GPU’s opportunity.
hotspots and then incorporates this prediction model into a
DREAMPlace [Lin et al., 2020] is inspired by the idea that placement engine, showing how an ML-based routing con-
the analytical placement problem is analogous to training a gestion estimator can be embedded into the global placement
neural network. They both involve optimizing parameters and
stage.
minimizing a cost function. Based on the state-of-the-art an-
alytical placement algorithm RePlAce, DREAMPlace imple- 3.4 Challenges and Limitations for Placement
ments hand-optimized key operators by deep learning toolkit
PyTorch and achieves over 30× speedup against CPU-based The major challenges for ML applications in placement lie in
tools. PL-GNN [Lu et al., 2021] presents a graph learning- two folds: long feedback loop and high requirement of scal-
based framework that provides placement guidance for com- ability. Placement objectives like routability cannot be evalu-
mercial placers by generating cell clusters based on logi- ated until routing finished; hence, it may take hours to obtain
cal affinity information and attributes of design instances. the feedback in the optimization loop, which is unaffordable
PADE [Ward et al., 2012] improves data path logic through to make thousands of queries. Modern placers need to han-
automatic data path extraction and evaluation, in which the dle tens of thousands of macros and millions of standard cells
placement of data path logic is conducted separately from within several hours. Such requirement of scalability is still
random logic. [Agnesina et al., 2020] proposes a deep re- beyond the capability of existing ML approaches.
inforcement learning (RL) framework to optimize the place-
ment parameters of commercial EDA tool. An agent learns 4 Machine Learning for Routing
to tune parameters autonomously, trained solely by RL from 4.1 Learning-aided Routability Prediction
self-search. Handcrafted features along with graph embed-
In the placement step, the essential requirements of routing
dings generated using unsupervised Graph Neural Networks
design guidelines must be considered. However, it is difficult
are adopted for generalization to unseen netlists.
to precisely and quickly estimate routing information during
the placement step, and researchers have lately used machine
3.2 Placement Decision Making learning to overcome this problem. Table 1 summarize the
Learning-based methods for placement decision especially recent efforts on routability prediction, which can be catego-
RL have been proposed to obtain the generalization ability. rized into congestion count prediction and congestion loca-
Existing RL applications have demonstrated the effective- tion prediction at different design stages. Congestion count
ness on macro placement, where there are typically fewer denotes congestion related metrics such as total congestion
than 1000 macros to place. Google [Mirhoseini et al., 2021] and number of design rule violations, while congestion loca-
proposes an end-to-end learning method for macro place- tions require detailed locations of congestion or design rule
ment that models chip placement as a sequential decision violations, usually represented as a 2D map.
making problem. In each step, the RL agent places one Congestion count. As mentioned above, it denotes the
macro and target metrics are used as reward until the last overall amount of routing congestion, useful to evaluate how
action. GNN is adopted in the value network to encode the good a placement solution is. Efficient prediction of con-
netlist information and deconvolution layers in the policy net- gestion count can reduce the turn-around time in the de-
work output the mask of current macro position. DeepPlace sign flow by avoiding the time-consuming routing stage.
[Cheng and Yan, 2021] first proposes a joint learning tech- [Qi et al., 2014; Zhou et al., 2019] capture multiple factors
nique for the placement of macros and standard cells by the in global routing and enable prediction of detailed rout-
integration of reinforcement learning with a gradient-based ing congestion using multivariate adaptive regression splines
classical cell placer ([Lin et al., 2020]). To further bridge the (MARS). [Tabrizi et al., 2018; Maarouf et al., 2018] attempt
 Task type Feature from Label at Publication Backbone models Benchmark
[Qi et al., 2014] MARS
Global Routing Detailed Routing [Zhou et al., 2019] ASIC
MARS
[Tabrizi et al., 2018] MLP ASIC
Congestion Count Cell Placement Global Routing [Maarouf et al., 2018] LR, RF, MLP FPGA
(Scalar or Vector as Labels) [Zhou et al., 2015] MARS
Cell Placement Detailed Routing [Chan et al., 2016] ASIC
MARS, SVM
Macro Placement Global Routing [Cheng et al., 2018b] LR, RF, Boosting, MLP ASIC
Global Routing Detailed Routing RouteNet [Xie et al., 2018] FCN ASIC
PROS [Chen et al., 2020] FCN ASIC
[Pui et al., 2017] LR, SVM
Congestion Locations [Yu and Zhang, 2019]
Cell Placement Global Routing Conditional GAN
(2D Map as Labels) [Alawieh et al., 2020] FPGA
Conditional GAN
DLRoute [Al-Hyari et al., 2021] CNN
Cell Placement Detailed Routing J-Net [Liang et al., 2020] U-Net ASIC
Table 1: Summary of recent publications on learning-aided routability prediction in terms of congestion count and locations.

Target for placement Learning protocol

to predict global routing congestion at placement stage with Publication Macro Standard cell Module Reward using
linear regression (LR), random forest (RF), and MLP mod- [Cheng and Yan, 2021] RL DNN backprop CNN+GNN cell placement
els for datasets from ASIC and FPGA. Other studies like [Mirhoseini et al., 2021] RL NA GNN macro placement
[Vashisht et al., 2020] RL NA MLP macro placement
[Zhou et al., 2015; Chan et al., 2016] aim at predicting the [He et al., 2020] RL NA MLP macro placement
congestion count at detailed routing given cell placement, and [Lin et al., 2020] heuristic DNN backprop NA NA
[Cheng et al., 2018b] tries to predict the congestion count at Table 2: Comparison of learning-based placers. RL is the most
global routing given only macro placement. popular paradigm for macro placement, while learning for stan-
dard cell placement still relies on traditional placers for further en-
Congestion location. Its accurate prediction is necessary hancement. Note that [Cheng and Yan, 2021] is a joint learning ap-
to effectively guide the placement and routing optimiza- proach for solving placement of macro and standard cells, whereby
tion, as it can help reserve enough space for congested the two kinds of components are sequentially arranged by rein-
regions. RouteNet [Xie et al., 2018] is the first attempt forcement learning and neural network formed gradient optimiza-
to utilize CNN to forecast the locations of design rule tion respectively and reward is based on the full placement result.
[Lin et al., 2020] is not a RL method, thus there is no reward func-
checking (DRC) hotspots given cell placement and global
tion.
routing information. A customized fully convolutional
network (FCN) is constructed taking features like rect-
angle uniform wire density (RUDY), as a pre-routing
congestion estimator, and global routing congestion map. 4.2 Deep Neural Networks for Routing
Predicting global routing congestion locations at place-
ment is helpful to guide routability optimization in early Rather than the methods mentioned above predicting the
stages. Thus, PROS [Chen et al., 2020], [Pui et al., 2017], congestion information of placement, some works employ
[Yu and Zhang, 2019], [Alawieh et al., 2020], and DL- DNNs to directly handle routing problems, with a little or
Route [Al-Hyari et al., 2021] attempt to learn the correlation even without the assistance of traditional routing techniques.
between congestion locations at global routing and cell place- [Jain and Okabe, 2017] presents a fully convolutional neu-
ment. As both the features and labels can be represented as ral network learning to route a circuit layout with appro-
image-like tensors, many studies transform the problem into priate choices of metal tracks and wire class combinations.
image generation tasks and leverage FCN and conditional Encoded layouts containing spatial location of pins to be
GAN to build the correlation. [Liang et al., 2020] moves routed are fed into the network, and after 15 fully convolu-
one step further to directly predict congestion locations at tional layers followed by a comparator, 8 layout layers are
detailed routing (i.e., locations of design rule violations) produced, which are then decoded to obtain the routed lay-
from cell placement. A customized CNN architecture, J-Net outs. This work formulates routing as a binary segmenta-
(an extension of U-Net architecture), is proposed as opposed tion problem on a per-pixel per-layer basis, where the net-
to a plug-in use of machine learning modules. This work work is trained to correctly classify pixels in each layout layer
converts the density of pins and macros in placement results to be on or off. [He and Bao, 2020] models the circuit rout-
into images and optimizes an encoder-decoder model using ing as a sequential decision-making problem, and solve it by
a pixel-wise loss function. The network outputs a heat map, Monte Carlo tree search (MCTS) with DNN guided rollout.
showing where detailed routing congestion might occur. A recent study [Utyamishev and Partin-Vaisband, 2020] pro-
poses a global router that learns from routed circuits and au-
Among learning-aided prediction tasks, the more stages to tonomously routes unseen layouts. Different from traditional
skip in Fig. 1, the more difficult the tasks are, as we need routing flow, this approach redefines the global routing as a
to build models correlating with more stages. Thus, the ac- classical image-to-image processing problem and handles the
curacy requirement varies from task to task. Predicting con- imaging problem in a unified, single-step non-iterative man-
gestion locations at detailed routing at early stages like cell ner with a deep learning system, comprising a variational au-
placement or even macro placement can expedite the design. toencoder and a custom loss.
4.3 Reinforcement Learning for Routing specific optimization objectives toward cell density, global
RL is also a promising way to tackle routing, as it can be routability [Viswanathan et al., 2011], detailed routabil-
seen as a process that comprises decision-making phases. ity [Yutsis et al., 2014], and timing [Kim et al., 2015]. A
A DQN agent [Liao et al., 2020b], as one of the first at- popular benchmark for both placement and routing is the
tempts to combine RL with global routing, learns to de- ISPD 2015 [Bustany et al., 2015]. It consists of five cir-
cide the routing direction on a 3D grid graph at each step, cuits, and each of them has multiple floorplans produced
e.g. traveling north, south, and so on. For detailed routing, from setting different macro locations with predefined heuris-
[Liao et al., 2020a] presents an attention-based REINFORCE tics. ISPD announced two global routing contests in
method for obtaining routing orders, followed by a classical 2007 [Nam et al., 2007] and 2008 [Nam et al., 2008] and two
pattern router to finish the routing given the order, for small initial detailed routing contests in 2018 [Mantik et al., 2018]
benchmarks with up to thousands nets. [Lin et al., 2021] and 2019 [Liu et al., 2019], respectively, along with the
tackles routing ordering with an asynchronous actor-critic benchmarks.
framework for routing millions of nets and improves the so-
lution quality over the state-of-the-art detailed router with 6 Conclusion and Outlook
policy distillation. [Ren and Fojtik, 2021] employs a genetic
algorithm to generate initial routing choices and then uses In modern physical design flow, it takes human experts weeks
RL to progressively handle design rule violations in stan- to iterate the placement tools in order to produce solutions
dard cell routing. Regarding rectilinear Steiner minimum with no design rule check violations after routing stage. With
tree (RSMT) construction [Hartmanis, 1982], a process that rapid development of machine learning, a promising solution
is a fundamental problem in EDA and computer science and for this obstacle is to propose efficient and effective learning
typically runs millions of times in traditional global routers, framework for solving placement and routing either sequen-
REST [Liu et al., 2021a] is the first attempt to solve RSMT tially or concurrently. [Cheng and Yan, 2021] designs a joint
construction using a machine learning-based method. A new learning approach for either macro placement and routing or
concept, rectilinear edge sequence (RES), is proposed to en- placement of macros and standard cells. However, this is not
code an RSMT solution , and an actor-critic model is devised a complete design cycle since millions of or even billions of
to construct an RSMT. standard cells are left behind. For future works, learning-
based routing solvers merit particular attention as the final
4.4 Challenges and Limitations for Routing building block for the entire end-to-end learning paradigm.
Despite the existing efforts on learning-based routing, it is
difficult for current techniques to systematically outperform References
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