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4 CRC calculation unit

The document describes the CRC (cyclic redundancy check) calculation unit for the STM32F4xx family, which generates a CRC code from a 32-bit data word using a fixed generator polynomial. It outlines the main features, functional description, and registers involved in the CRC calculation process, including the data register, independent data register, and control register. The CRC unit is essential for verifying data integrity in applications such as Flash memory verification.

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Matteo Romani
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15 views

4 CRC calculation unit

The document describes the CRC (cyclic redundancy check) calculation unit for the STM32F4xx family, which generates a CRC code from a 32-bit data word using a fixed generator polynomial. It outlines the main features, functional description, and registers involved in the CRC calculation process, including the data register, independent data register, and control register. The CRC unit is essential for verifying data integrity in applications such as Flash memory verification.

Uploaded by

Matteo Romani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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RM0090 CRC calculation unit

4 CRC calculation unit

This section applies to the whole STM32F4xx family, unless otherwise specified.

4.1 CRC introduction


The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

4.2 CRC main features


• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
– X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X + 1
• Single input/output 32-bit data register
• CRC computation done in 4 AHB clock cycles (HCLK)
• General-purpose 8-bit register (can be used for temporary storage)
The block diagram is shown in Figure 8.

Figure 8. CRC calculation unit block diagram

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CRC calculation unit RM0090

4.3 CRC functional description


The CRC calculation unit mainly consists of a single 32-bit data register, which:
• is used as an input register to enter new data in the CRC calculator (when writing into
the register)
• holds the result of the previous CRC calculation (when reading the register)
Each write operation into the data register creates a combination of the previous CRC value
and the new one (CRC computation is done on the whole 32-bit data word, and not byte per
byte).
The write operation is stalled until the end of the CRC computation, thus allowing back-to-
back write accesses or consecutive write and read accesses.
The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the
CRC_CR register. This operation does not affect the contents of the CRC_IDR register.

4.4 CRC registers


The CRC calculation unit contains two data registers and a control register.The peripheral
The CRC registers have to be accessed by words (32 bits).

4.4.1 Data register (CRC_DR)


Address offset: 0x00
Reset value: 0xFFFF FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR [31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR [15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Data register bits


Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.

4.4.2 Independent data register (CRC_IDR)


Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[7:0]
Reserved
rw rw rw rw rw rw rw rw

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RM0090 CRC calculation unit

Bits 31:8 Reserved, must be kept at reset value.


Bits 7:0 General-purpose 8-bit data register bits
Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register.

4.4.3 Control register (CRC_CR)


Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET
Reserved
w

Bits 31:1 Reserved, must be kept at reset value.


Bit 0 RESET bit
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.
This bit can only be set, it is automatically cleared by hardware.

4.4.4 CRC register map


The following table provides the CRC register map and reset values.

Table 21. CRC calculation unit register map and reset values
Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1 0

CRC_DR Data register


0x00 Reset
0xFFFF FFFF
value
CRC_IDR Independent data register
0x04 Reset Reserved
0x00
value
CRC_CR RESET
0x08 Reset Reserved
0
value

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