Physics & Modeling of Microelectronic Devices

(MEL G214)
Lectures –19 & 20

Metal-Oxide-Semiconductor Capacitor
&
Metal-Oxide-Semiconductor Field Effect Transistor

Prof. Manish Gupta

EEE
Effects of Real Surfaces
Impact of gate work-function i.e. Φs ≠ Φm
• In general, the gate electrode is designed either with metal (such as
Aluminium or gold) or heavily doped poly-Silicon

• Let’s take an example in which gate is designed with aluminium (Φm = 4.1
eV)

• Work-function of intrinsic Si (Φs) = Eg/2 + ; ;Eg is bandgap and is affinity

• For intrinsic Si, Eg = 1.1 eV and = 4.05 eV, Φsi = 4.6 eV.

• This shows that Φsi ≠ Φm and Φm – Φsi = -0.5 eV, where Φsi is work-function
of intrinsic Si

BITS Pilani, K K Birla Goa Campus

Effects of Real Surfaces

• For p-type Si substrate, Φs = Eg/2 + + Φf

• Now, for p-type Si substrate, ΦMS = ΦM - Φsi – Φf = (-0.5- Φf) eV

BITS Pilani, K K Birla Goa Campus
Effects of Real Surfaces
• If the p-type Si doping is 1.5×1016 cm-3, Φf = 0.345 eV

Or ΦMS = (-0.5-0.345) eV = -0.845 eV

• MOS capacitor with Φs ≠ Φm and applied voltage = 0 V

BITS Pilani, K K Birla Goa Campus

Effects of Real Surfaces
Impact of gate work-function i.e. Φs ≠ Φm

Energy Band Diagram at Vg = 0 V

MOS capacitor is in depleted state Flat Band Condition; VFB1 is the
voltage equivalent of the ΦMS

BITS Pilani, K K Birla Goa Campus

Effects of Real Surfaces
Effects of Interface Charges
• The characteristics of ideal MOS structure is affected by the charges in the
insulator and at the semiconductor-oxide interface

• For example, Na+ (most common contamination) ions can be incorporated

unintentionally in the oxide during the growth or subsequent processing
steps
• Since sodium ions are positively charged (Qm), it induces negative charges
in the semiconductor substrate.
• The induced negative charge is greater if Na+ ions are present near the
interface

• Oxide also contains trapped charges (Qot) due to imperfection (or defects)
in SiO2

• Near the interface, a transition layer (SiOx) contains fixed charges (Qf)

• The charges present at the Si-SiO2 interface are called interface charges.
BITS Pilani, K K Birla Goa Campus
Effects of Real Surfaces
Effects of Interface Charges

• The extent of depletion in MOS system also depends on the oxide/interface

charges
• Thus, if the net charge contributed by the oxide is positive, the flat band
voltage VFB is

BITS Pilani, K K Birla Goa Campus

C-V Curve with Non-ideal Effects
Effects on C-V curve

• The flat band voltage gets shifted in the presence of non-ideal

effect.

BITS Pilani, K K Birla Goa Campus

Threshold Voltage (With non-ideal effects )

For non-ideal MOS capacitor or practical MOS capacitor

BITS Pilani, K K Birla Goa Campus

Threshold Voltage

Threshold voltage as a function of doping

BITS Pilani, K K Birla Goa Campus
Metal-Oxide-Semiconductor FET
(MOSFET)
• 3D Schematic view of n-type
MOSFET
• In a MOSFET, source and drain
regions are identical and heavily
doped (~ 1020 cm-3)

• As the source and drain regions are

identical, their functionality can be
interchanged

• Gate is designed with poly-Si

• SiO2 is used as a oxide layer

Energy band diagram along the x-direction

BITS Pilani, K K Birla Goa Campus

MOSFET Operation

• L is the gate length. It determines the technology.

• Along y-direction, 2 depletion regions are present i.e. at source side (p-n
junction) and at the drain side (p-n junction)

• When VGS = 0 V, and VDS = + ve (small in magnitude), the magnitude of

the current is very small as no. of electrons present underneath the gate
are very small
BITS Pilani, K K Birla Goa Campus
MOSFET Operation
• When VGS = + ve, and VDS = + ve but << (VGS - VTH ) the
magnitude of the current increases linearly as no. of electrons
present underneath the gate increases due to inversion

• In this region, channel is uniform in between source and drain

BITS Pilani, K K Birla Goa Campus

MOSFET Operation

• When VGS = + ve, and VDS = + ve but < (VGS - VTH ) the rate of
increase of current decreases as the electrons concentration
decreases near to the drain side due to increase in depletion
width near to the drain (reverse biased pn junction)
BITS Pilani, K K Birla Goa Campus
MOSFET Operation

• When VGS = + ve, and VDS = (VGS - VTH ) = VDS(sat) , the depletion
region near the drain side further increases and the channel gets
pinched-off towards the drain side

• The drain current tries to get saturate

BITS Pilani, K K Birla Goa Campus
MOSFET Operation

• When VGS = + ve, and VDS > VDS(sat), the depletion region near the
drain side further increases and the pinch-off point moves towards
to source

• The drain current gets saturated

BITS Pilani, K K Birla Goa Campus
Drain Current-Drain Voltage

BITS Pilani, K K Birla Goa Campus

Drain Current Equation of MOSFET
In general, drain current in a MOSFET is given by

(1)

VGS = Applied gate-to-source voltage,

VTh (or VT or VTn) = Threshold voltage
VDS = Drain-to- source voltage
Cox = Ci = Oxide capacitance or insulator capacitance
W = Width of the device in Z-direction
L = Gate length
BITS Pilani, K K Birla Goa Campus
Drain Current Equation of MOSFET
Case 1: VGS = 0 V, VDS << VGS - VT

• No inversion layer, ID (or IDS) = 0

Case 2: VGS = +ve V, VDS << VGS - VT

Using eq. 1

This region is called linear region as ID varies linearly with VDS

Case 3: VGS = +ve V, VDS >> VGS – VT = VDS(sat)

Using eq. 1 and substituting

VDS = VGS -VTh
This region is called non-linear region
BITS Pilani, K K Birla Goa Campus
Channel Conductance (g = 1/R)
Case 1: VGS = 0 V, VDS << VGS - VT

• Channel resistance is very high

Case 2: VGS = +ve V, VDS << VGS – VT (Linear region)

Case 3: VGS = +ve V, VDS >> VGS – VT = VDS(sat)

𝑉𝐷𝑆(𝑠𝑎𝑡) 𝐿
𝑅𝑐ℎ2 = = 2
𝐼𝐷 𝜇𝑛 𝐶𝑜𝑥 𝑊 𝑉𝐺𝑆 − 𝑉𝑇ℎ

BITS Pilani, K K Birla Goa Campus

Sub-Threshold Conduction in MOSFET
• Till now, it is assumed that if VGS < VTH, the drain current is zero.
However, it is not true. For VGS < VTH, the MOSFET is weakly
inverted (sub-threshold region)
• At the source end of the channel,
the electron concentration
crossing the pn junction is

• When the gate voltage is applied,

the barrier between source and
channel decreases

BITS Pilani, K K Birla Goa Campus

Sub-Threshold Conduction in MOSFET
• Once the barrier reduces, electron
diffuses from source to the channel
region. The diffusion current at any
point ‘y’ is given by

xn is the width upto which charges

extend in the weakly inverted region

• Drain current will become

BITS Pilani, K K Birla Goa Campus

Sub-Threshold Conduction in MOSFET

ID - VGS curve (transfer curve) of a

MOSFET, here y-axis is linear and x-
axis is linear

BITS Pilani, K K Birla Goa Campus

Transfer Characteristics (ID - VGS)
on Semi-log graph

BITS Pilani, K K Birla Goa Campus

Electron Mobility in MOSFET
• The mobility of electrons in the channel (or inversion layer) is
lower than that of bulk.

• Reason

• Due to the electron-electron repulsion

• Since the electrons lies very close to oxide-semiconductor

interface, the electrons get scattered by surface roughness

• Columbic interaction between the fixed oxide charges

• The degradation in the mobility increases with increasing gate

bias

BITS Pilani, K K Birla Goa Campus

Electron Mobility in MOSFET

• Two factors degrades the mobility, the transverse electric field (or
gate field or vertical field) and increasing temperature

BITS Pilani, K K Birla Goa Campus

Electron Mobility in MOSFET
Impact of Drain Bias
• The mobility depends also on drain bias or longitudinal electric field

• In general, mobility is constant and drift velocity increases linearly

with the electric field until field reaches Esat (saturation field)

• After Esat, drift velocity = saturation velocity

• The maximum electric field near the drain side is given by voltage
drop across the pinch-off region divided by the length of the pinch-off

BITS Pilani, K K Birla Goa Campus

Problem

Sketch the low and high-frequency behavior (and explain the

difference) of an MOS capacitor with a high-k dielectric (𝜖𝑟 = 25) on a
p-type Si substrate doped at 1017 𝑐𝑚−3 . Label the accumulation,
depletion and inversion regions. If the high frequency capacitance in
accumulation is 2𝜇𝐹/𝑐𝑚2 , calculate the dielectric thickness and the
minimum high frequency capacitance.

Ans: Tox = 11.6 nm, W = 0.103 mm, Cd,min = 0.101 mF/cm2

High frequency minimum capacitance : 0.0965 mF/cm2

BITS Pilani, K K Birla Goa Campus

Thank you

BITS Pilani, K K Birla Goa Campus