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2.moscapacitivemodel

The document discusses the MOS capacitive model, focusing on the dynamic response of MOSFET transistors and the sources of parasitic capacitances. It details the capacitances associated with the MOS structure, channel, and junctions, highlighting their significance in digital design. Additionally, it provides examples of capacitances in a 0.25 μm CMOS process and describes modern silicon transistor types, including traditional MOSFETs, SOI MOSFETs, and finFETs.

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giuseppe202323
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8 views

2.moscapacitivemodel

The document discusses the MOS capacitive model, focusing on the dynamic response of MOSFET transistors and the sources of parasitic capacitances. It details the capacitances associated with the MOS structure, channel, and junctions, highlighting their significance in digital design. Additionally, it provides examples of capacitances in a 0.25 μm CMOS process and describes modern silicon transistor types, including traditional MOSFETs, SOI MOSFETs, and finFETs.

Uploaded by

giuseppe202323
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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MOS Capacitive Model

Prof. A.D. Grasso


MOS Capacitive Model

• The dynamic response of a MOSFET transistor is a sole function of the time


it takes to charge/discharge the parasitic capacitances.
• MOS parasitic capacitances originate from three sources:
 the basic MOS structure,
 the channel charge and
 the reverse-biased PN junctions of drain and source.

Prof. A.D. Grasso


MOS Structure Capacitances
Polysilicon gate

• Both source and drain tend to extend


somewhat below the oxide by an amount xd,
called the lateral diffusion.
Source Drain
• This overlap is unavoidable and gives rise W
n+ xd xd n+
to a parasitic linear capacitance between
gate and source (drain) that is called the
Gate-bulk
overlap capacitance. Ld
overlap
Top view
 ox
cox  Capacitance per unit area
Gate oxide
tox tox
n+ L n+
Cgs ,ov  Cgd ,ov  Wxd cox
Cross section

Prof. A.D. Grasso


MOS Channel Capacitance

Cut-off Triode Saturation

Prof. A.D. Grasso


MOS Channel Capacitance

Cut-off Triode Saturation

Operation
Cgb Cgs Cgd
region
Cut-off CoxWL 0 0
Triode 0 (CoxWL)/2 (CoxWL)/2
Saturation 0 (2/3)(CoxWL) 0

•Most important regions in digital design: saturation and cut-off

Prof. A.D. Grasso


Junction Capacitances
Channel-stop implant
Let us consider the reverse-biased source-bulk NA+
pn junction. It consists of two components:
Side wall
•The bottom-plate junction, which is
Source
formed by the source region and the p W
ND
substrate.
Bottom
•The side-wall junction, formed by
the source region and the p+
xj Side wall
channel-stop implant.
Channel
LS Substrate N A

C jsb,tot  CsbA  Area  Csbp  Perimeter  K eqsbAC j 0,sbAWLS  K eqsbpC j 0,sbp 2 LS  W 

Similar results can be derived for the drain:

C jdb,tot  CdbA  Area  Cdbp  Perimeter  K eqdbAC j 0,dbAWLS  K eqdbpC j 0,dbp 2 LS  W 

Prof. A.D. Grasso


MOS Capacitive Model

CGD  Cgd  Cgd ,ov


CGS  Cgs  Cgs ,ov
CSB  C jsb,tot
CDB  C jdb,tot
•Aside from the MOS structure capacitances,

CGB  Cgb
all capacitors are nonlinear and vary with the
applied voltage

Prof. A.D. Grasso


Example

•Capacitances in 0.25 m CMOS process

Cox Cj mj b Cjsw mjsw bsw


(fF/m2) (fF/m2) (V) (fF/m) (V)
NMOS 6 2 0.5 0.9 0.28 0.44 0.9
PMOS 6 1.9 0.48 0.9 0.22 0.32 0.9

Example: For an NMOS with L = 0.24 m, W = 0.36 m,LD = LS = 0.625 m, VGS=0

CGS=CGD=Cgs,ov = Cgd,ov = Cox xd W = 0.11 fF


CGB = Cox WL = 0.52 fF
CSB=CDB=Cjdb,tot=Cjsb,tot = CjsbA = Cj LS W + Cjsw (2LS + W) = 0.9 fF

Prof. A.D. Grasso


Modern silicon transistors

•a. A traditional n-channel MOSFET uses a highly doped n-type polysilicon gate electrode, a
highly doped n-type source/drain, a p-type substrate, and a silicon dioxide or oxynitride gate
dielectric.
•b. A silicon-on-insulator (SOI) MOSFET is similar to the traditional MOSFET except the
active silicon is on a thick layer of silicon dioxide. This electrical isolation of the silicon
reduces parasitic junction capacitance and improves device performance.
•c. A finFET is a three-dimensional version of a MOSFET. The gate electrode wraps around
a confined silicon channel providing improved electrostatic control of the channel electrons.

Prof. A.D. Grasso


Modern silicon transistors

Prof. A.D. Grasso


Modern silicon transistors

Prof. A.D. Grasso

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