Genus: Logical & Physical Synthesis

21.1 Update
Agenda
• Paradigm
• RTL Floorplanning
• iSpatial
• PPA Improvements
• Low Power
• Clock Gating
• Advanced Node Synthesis
• DFT
• Joules

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Paradigm

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Digital Design & Implementation

Full Flow Technology Shifts

Genus
RTL Floorplanning

Early clock flow

Reuse Flow

Signoff accuracy
Digital Design Glitch Power Opt Path Based GigaOpt
Implementation
Activity Replay

Test Point Insertion

Joules Innovus

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Genus Key Features
iSpatial Physical Synthesis Compus: Next-Gen Compiler Power Leadership

Stimulus

Genus
Genus Genus

Joules
Innovus Innovus
TM

Innovus

• Unified Genus™/Innovus™ PlaceOpt • Joules integration

• Accurate predictability • Aggressively flatten logic levels • Activity driven implementation
• Best PPA • Improved PPA • Integrated power activity refresh
• Fastest TAT • Left-shift glitch

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Machine Learning Technology for Digital Flow

• Innovus ML: Delay Prediction

Improved PPA (WNS, TNS, Pwr)
Digital Implementation
Up 20% better PPA, up to 10x productivity

• Tempus PI: Voltage-aware timing

Tempus Signoff • Tempus PBA: Fast PBA Better timing signoff accuracy and run-time using ML
• Tempus ECO: Improved ECO

• Conformal Smart LEC

Conformal Formal Verification • Logical Equivalency Check
Faster TAT using ML generated proof flows

Accelerated Library development

Library Characterization • Liberate ML: Characterization
Example: 47% of libs interpolated 98%+ Pass Rate

Design for Manufacturing • ML-DFM: Yield Hotspot prediction & In-design detection and fixing

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Genus 21.1 – Predictability and PPA for Challenging Designs
• Productivity
Implementation Flow o ~10% TAT improvement – SOCV, complex SDC
o RTL floorplanning – GigaPlace GXL

Synthesis • PPA – 5-10% improvement

o CSA/mux, tree mapping, multibit mapping, new power flow, …
iSpatial – power optimization PhysRes
iSpatial o

o Joules integration – Smart XOR, Data gating, replay, glitch…

CCOpt • Syn Turbo = Tighter alignment of Genus & Innovus

o TAT and PPA improvements
o Better conditioning of design going into iSpatial & using PhysRes
RouteOpt inside Innovus – Reduced pessimism

• Advanced nodes
o 3nm-and-beyond synthesis

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This slide contains forward-looking statements regarding Cadence's business or products. Actual results may differ materially from the information presented here.
RTL Floorplanning

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RTL Floorplanning More info in
the Flows
Improve productivity & time to market! presentation

• Enable physically-aware PPA exploration without a

starting floorplan RTL

• Genus uses Innovus GigaPlace-GXL technology at

generic gates Genus™
o Requires GigaPlace-GXL option (INVS48) syn_generic
+ Gigaplace-GXL

syn_map
• Basic macros placement & power domains
iSpatial
• RTL floorplanning is for prediction only
o This is NOT a production quality floorplan
o The use is to allow early design cycle use of early physical and
iSpatial Physical-aware
PPA reports
• Advanced floorplanning for production possible with
Innovus iSpatial cockpit

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iSpatial

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What Is Genus iSpatial?
• Unified common physical optimization flow.
o Directly calls the GigaPlace™ Engine and GigaOpt™ Optimizer from the Innovus system in the physical synthesis stage.

• Unified placement, routing, and optimization engine from front end to back end.

• Improves predictability of front-end synthesis to back-end

Genus

syn_gen -physical
placement and routing.
syn_map -physical • Provides accurate prediction of PPA, including timing, area,
leakage and congestion for RTL designers.
DFT Insertion
• Allows Innovus place_opt_design to run faster.
iSpatial
• Innovus POD can inherit placement and optimization data to save full
flow runtime.
Innovus

• Contains placement and optimization data.

DB • Reduces optimization efforts that waste runtime, area, and power.
Netlist Handoff:
Reduced • Shortens turnaround time toPPA prediction
Handoff:
Regular place_opt • Reasonable Genus runtime so RTL designer can iterate and get
place_opt feedback fast.
TAT gain with • Fast convergence and gives predictive results ready to hand-off.
DB handoff
About 50%~60% of regular POD runtime.
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iSpatial, More Details

• Faster flow to believable results

• 4-5 hrs / M instances runtime
iSpatial • Area predictability within 3% of POD
• Path Delay within 5% of POD
• Accurate congestion hotspot prediction

GigaPlace • Slack and Power-Driven Placement

• Accurate Congestion Feedback based on Global Routing

• Faster Global Optimization based on critical views

• Relaxed physical constraints for faster critical path optimization
• Genus mapper-based restructuring (more details on next
GigaOpt based
Physical Optimization
slide)
• AAE based Delay Calculation (full AOCV/SOCV support)
• Full MMMC support
• Multi Bit Flip Flop Merging
• Early Clock Flow

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 Physical Restructuring of critical TNS logic
(Simple Example) iSpatial Genus Engine
Generic
gates Gen
Gen Post-placement un-
map of region
Gen

Restructure/Remap
Structure+
slacks Mapping for better
remaped timing/power using
map P&R timing
remaped
environment
placed
The logic cone is
re-integrated
After placement and clock Innovus
tree synthesis, netlist can Post-cts remaped

be restructured to improve No longer need to

the design efficiency and manually
map
optimize timing, power, or
remaped
resynthesize
area – when the true
critical paths are visible.

Supports multiple features including MMMC, ECF, useful skew, MBIT, ILM, AAE timing correlation, etc.
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Driving placement / clock tree in Genus
• iSpatial is intended for PPA prediction

• Innovus settings for achieving predictability have been added to Genus 21.1
o Prior releases used a “postload” file, which has been deprecated with 21.1

• Advanced floorplanning and implementation-specific physical features should

be added in Innovus prior to incr-placement.

• Early Clock Flow (ECF) is supported with read_clock_tree_spec

o Only ECF related commands or attributes can be in this file
o If there are other commands/attributes, the run will error out

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Driving placement / clock tree in Genus (Cont.)
• To set up Innovus for iSpatial, set the attributes directly in the Genus script

=> Must be set before syn_opt –spatial

• In 21.1 Genus, we support most of the Innovus attributes in Genus, including:

o design_*
o opt_*
o place_*
o route_* (except route_design_detail)
o timing_*
o reorder_*
o floorplan_*
o delaycal_*

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Driving placement / clock tree in Genus: ECF Example
• Early clock flow:
o For attributes related to early clock flow, we need to put all ECF/CTS attributes in a
file and use command read_clock_tree_spec to read the file.
o Innovus has to be 21.1x
• Example:
o read_clock_tree_spec iSpatial_clock_spec.tcl

iSpatial_clock_spec.tcl
create_route_type –name rt_trunk –route_rule CTS_TRUNK -bottom_preferred_layer 9 –top_preferred_layer 11
create_route_type –name rt_leaf –route_rule CTS_LEAF –bottom_preferred_layer 5 –top_preferred_layer 8

set_db cts_route_type_trunk rt_trunk

set_db cts_route_type_leaf rt_leaf

set_db cts_buffer_cells CKBFX2 CKBFX4 CKBFX8 CKBFX12

set_db cts_inverter_cells CKIVX2 CKIVX4 CKIVX8 CKIVX12
set_db cts_clock_gating_cells ICGX1 ICGX2 ICGX4
set_db cts_use_inverters true

set_db cts_target_max_transition_time 0.120

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iSpatial Setup 21.1
Aligned with Innovus
• To set the effort level for spatial optimization flow standard/extreme flows
o opt_spatial_effort standard/extreme
– Extreme effort enables the iSpatial flow
– Standard enables
• early data flowUsed for early floorplan PPA exploration
• Lightweight placement and optimization
• Faster runtime and provide reasonable result

• To set/override Innovus executable path, use attribute

o set_db innovus_executable <invs_path>
– If innovus_executable attribute is not set, the default search order is used:
• Innovus environment variable
• PATH environment variable
• CDS_SYNTH_ROOT environment variable

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iSpatial Setup 21.1, other attributes of interest
• To specify the directory which contains Innovus interface files generated during syn_opt –spatial
o set_db invs_temp_dir <path_to_dir>

• To specify the script to include in Innovus before design load:

o set_db invs_preload_script <path_to_preload_script>

• Enabling ECF in iSpatial:

o set_db opt_spatial_early_clock true/false

• iSpatial merge flow option:

o set_db opt_spatial_merge_flops false/true/mergeOnly/splitOnly

• iSpatial enablingf restructuring:

o set_db opt_spatial_restructuring true/false

• iSpatial saving innovus db after Innovus finished:

o set_db invs_save_db true

• Enabling predict floorplan in the middle of syn_gen:

o set_db predict_floorplan_enable_during_generic true

• Enabling predict floorplan using Innovus in generic stage:

o set_db predict_floorplan_use_innovus true
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PPA
Performance – Power - Area

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 Synthesis Turbo Flow
Up to 5% better PPA and 10% better TAT

Flow architecture in the • Better condition of design going into iSpatial & using PhysRes inside
context of Genus + Innovus – reduced pessimism
Innovus o Frontend engine with architecture reselection
Implementation Flow o Better structuring reduces timing pressure and runtime
o Update architectures later in the flow if needed
High accuracy predictions consuming large runtime not necessary
Synthesis
o

• Runtime intensive optimizations done in iSpatial

iSpatial
• PhysRes backend engine integrated with Innovus
Perform critical region re-synthesis for timing and area in iSpatial/Innovus
CCOpt o

o Low-mid effort optimizations in frontend

RouteOpt • Improved infrastructure
o Constraints, Reporting

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This slide contains forward-looking statements regarding Cadence's business or products. Actual results may differ materially from the information presented here.
Genus – Improved Engines for PPA/TAT
• Compus - Datapath and HDL optimization engine
o Maximal CSA results in better area and power
o New path depth optimizations result in better timing
o Shifter and generic mux optimizations result in better routability

• Congestion Aware Synthesis

o Better structuring for congestion inducing logic
o Power aware congestion optimization

• Early Clock Gating

o Parse high level RTL structures to infer better CG enables
o Improved area and dynamic power

• Multibit, structuring, and mapping improvements

o Better power, path depth (timing), and area tradeoffs

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Compus Advanced Logic Optimization TNS/power-Driven ROI with Innovus GigaPlace
Elaborated Design
Tradeoff Zone

f(normalized slack
(path depth), TNS
sensitivity, power)

Only power Only power

& timing & area

Area

Slack=0
CPU1 CPU2 CPU<n>
Negative Slack Positive Slack

Characterize different Analytically solve for best

Analytical RoI Costing Engine micro-architectures up front global solution

area
RTL and Datapath power
Control DataFlow Transforms delay
Transforms
100s of transforms
Compus guides Genus™ Synthesis to the right architecture for your RTL
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Low Power

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Genus Power Optimization Flow
Features per Flow Step & What to Expect

syn_generic FEATURE EXPECTED COMMENT

• Clockgating
GAIN
[-physical]

Leakage optimization Large, 5- Dependent on #Vt classes and criticality

• Activity-Driven Mapping (ADM) 50% of design; mapper makes initial choice,
syn_map • Power-Aware Incremental Optimization (IOPT) IOPT refines solutions per logic cone
• High-Effort Libcell Support (HEOC)
[-physical] • Multibit Merging (MBCI)
Activity-Driven 1-5% Optimizing internal power on less-critical
Mapping (ADM) dynamic cells; power becomes a factor in the
cost function to pick the best solution
• Power-Aware IOPT
[syn_opt]* • Activity-Driven Restructuring (ADR) Power-Aware IOPT + 1-5% total Needs dedicated call to logical syn_opt;
• (*additional logical IOPT is optional) Activity-Driven Restructures netlist with focus on high-
Restructuring (ADR) activity nets

High-Effort Libcell 5-10% Most helpful with 3+ Vt classes to

Support leakage control usage of highest-leakage class;
syn_opt • iSpatial with Power-Driven Placement and initial mapping will not use these cells,
Optimization only final stages of IOPT using them
[-spatial]

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Optimization is Cost-Driven
• Mapping a generic logic cone has lots of potential solutions
o They differ in their delay/area/power cost
Mapped Logic = f(slack, area, power)

o The “area vs power” trade-off is user-controlled by the attribute design_power_effort

– low will not allow any larger area growth
– high puts more emphasis on power and thus might grow area a bit more

Generic
Logic

Map Map
Cost function selects the best
Solution Solution
solution considering effort/weight
#1 #n

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Activity-Driven Mapping Example
Isolation of high-activity
nets to save power

0 nW

0 nW

Good gain on power for small area penalty

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New power setup simplifies flow
Same as with Innovus in 21.10
No mix of
Power UI so far up to 20.10 attributes from New Power UI in 21.10!
old and new
# optimize for leakage setups please !
set_db leakage_power_effort medium

# enable ADM
set_db [current_design] .max_dynamic_power 0 set_db design_power_effort [none|low|high]
set_db use_signal_activity_for_dynamic_power_opto 1
set_db opt_leakage_to_dynamic_ratio [0.0 – 1.0]
# ratio leakage vs dynamic
set_db lp_power_optimization_weight 0.5

# IOPT for dynamic power

set_db ignore_dynamic_power false
set_db incremental_power_engine joules

# enable power opt in iSpatial

set_db dynamic_power_effort medium

(attributes marked in red are hidden)

Old attributes will trigger a warning Now sharing same controls with Innovus

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Clock Gating

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Early Clock Gating (ECG)
• Clock gating early inside syn_generic
o Access to elaborated circuit before other transforms improved
Early Clock capability to identify strong clock gating conditions
Gating
• Prioritizes feedback paths and ‘sena*’ flop enable for more
elaborate datapath reduction
ungroup, • New algorithms for
opt, ... o Multiple feedback paths & sena
o Deep common enable extraction
syn_generic o Combining otherwise left-over flops with other flops
-physical PBS Opt1 o Improves CG coverage and strengthens enable conditions
(with ‘default’ CG)
• Clean up step
o Deep de-clone of clock gates
syn_map o Simplifies the datapath further
-physical PBS Opt2
• ECG is not enabled by default (to be done before elaboration)
set_db lp_insert_clock_gating true
set_db lp_insert_early_clock_gating true
CG cleanup elaborate
syn_generic

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Advanced Node Synthesis

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Genus – Advanced Node Flow Implications
RTL Stimulus

• RTL stimulus into synthesis/P&R for power optimization

Elaboration
• Early physical in syn_gen and syn_map
syn_gen
-physical
• Incremental Joules replay in synthesis & P&R
syn_map
-physical
• Genus/Innovus iSpatial for predictability & better PPA
iSpatial
• Activity output from Genus/Joules to drive Innovus/Voltus

SAIF/TCF Netlist/DB • Genus mapper Physical Restructuring (PhysRes) in Innovus

o Timing, power & area reduction

place_opt
With PhysRes

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 3nm and Beyond – Genus + Innovus
• Hybrid Row Flow
Different Different o iSpatial Genus & Innovus flow
cell heights row heights
o Smart Adaptive Site Density feature
o GigaPlace cell swapping for wirelength and tech site density
o Density Aware Costing (DAC) balances site utilization
through the flow
o Balancing Hybrid Row Density with Density Aware LEQ
Many valid cell
placements o Improved buffering and layer promotion

high-voltage low-voltage near-threashold

(ULV)
• Timing Signoff
Delay

o Ultra-low Vdd timing effects

o Timing Robustness analysis
o Device Aging in STA

0.4 0.8 1
Vt/Vdd
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DFT

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Current DFT Development / Focus More info in
Modus
presentation

• PPA & physical implementation

o Tighter integration with Genus/Innovus for better PPA
o Full flow PPA improvements for scan, 1500 wrappers scan_in pins

Elastic LFSR

=> Wire length and area reduction XOR Decompressor

Low-Power Gating

Physically aware test points with iSpatial Genus

Compression Macro
o
scan
chain
LBIST

DFT
Macro

MASK

Innovus
XOR Compressor

• Test productivity MISR

XOR

o Consolidation on Unified Compression architecture scan_out pins

o Scan Flexibility (DFT partitions, Launch On Shift, …)

o Hierarchical Test
o RTL based DFT insertion – superior verification, easier adoption

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DFT Flows More info in
Modus / Flow
presentations

• Modus DFT insertion inside Genus synthesis

o No need to exit Genus synthesis flow
o Physically aware scan, compression, and Test Points Insertion
o RTL insertion for MBIST and other test IP

• 3rd party Compression/ATPG support

o Supports both 3rd party netlist or RTL compression
o Option for scan/wrapper insertion in Genus
– Benefits: wirelength reduction, scan flexibility, DFT partitions, power-aware

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Physically Aware Test Points – Modus & iSpatial More info in
Modus
Area & routing congestion solution for test-critical designs presentation

• Repartitioning the test points when the design is optimized in

iSpatial & Innovus
• Native integration with Innovus mitigates the PPA impact via
physically aware optimization of the shared Test Points
• Physical aware Observe test point sharing – Genus 21.10
• Control point sharing – planned for end-2022 Genus
syn_gen -phys

syn_map -phys
Modus
Identify Test points ATPG

Insert Test points

Shared Observe
Scan insertion
Test Points
iSpatial
Physically-Aware
GigaPlace
GigaOpt Test Point
Optimization

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Joules

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Full-Flow Power Leadership More info in
Joules
presentation
Implementation Flow
Genus Power Infrastructure
Compus
Xcelium™ / Palladium®

• Automap RTL stimulus to

Genus™
gate power
Mapping
Joules™

• Replay technology Advanced Power Optimization

• Simulation accuracy
iSpatial • Automatic peak power identification
• Incremental activity
propagation • Full-flow reduction

Innovus™
• Guided/automated Incr GigaOpt™
CCOpt™
reduction NanoRoute™

Signoff
Tempus™, Voltus™
Pegasus™

Up to 10% Lower Power

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New and Improved Features More info in
Joules
presentation

• Integrated Replay : replay_stimulus* (can be run at any stage)

o Automatically map RTL stimulus to gate level design
o Benefit: improved power optimization at the cost of flow runtime

• Integrated Joules optimizations

o Benefit: Dynamic power reduction based on RTL vectors during synthesis
Smart-XOR Data Gating

*Ensure Joules executable is in the path or use joules_executable attribute to specify the Joules binary. Requires a Joules license.
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Licensing Changes

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Genus 21.1 – Licensing Changes
Feature Benefit Notes

RTL Floorplanning Physically aware PPA • No license required for using “predict_floorplan” without
exploration without floorplan automatic macroplacement
information • Innovus GigaPlace-GXL option required for using
“predict_floorplan” with automatic macroplacement

Physical Testpoint Reduced routing congestion & • If dft_physical_refine_test_point_logic is true, Modus

optimization cell area when using Modus DFT Option license used inside of iSpatial
testpoints

Joules integration Advanced power reduction • Requires Joules license in addition to Genus
• New in 21.1: Smart XOR gating, data gating, replay
integration
• Already existing: Stim formats (FSDB, SHM, PHY), Stim
manipulation/toolbox

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Summary

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Genus 21.1x : Predictability and PPA for Challenging Designs
Productivity PPA
Up to 10% TAT gain 5-10% improvement

Syn Turbo Advanced nodes

Tighter alignment Genus-Innovus 3nm and beyond synthesis

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