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Design and Analysis of CMOS Schmitt Trigger

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-7S, May 2019

Design and Analysis of CMOS Schmitt

Trigger
K V K V L Pavan Kumar, V.S.V. Prabhakar, Madala Durga Bhavani, Kowtharapu Geetha,
Maddukuri Venkatesh, K Hari Kishore
 The Schmitt trigger correctly interprets the waveform as a
Abstract: This paper entitles the implementation of a single high-to-low transition, whereas the non-hysteresis
complementary MOS Schmitt trigger using CMOS 130nm in. inverter misinterprets the input waveform. Clearly, this
Complementary MOS Schmitt trigger is analyzed with the difference is important if the result is to be used by a counter.
conventional Schmitt trigger in terms of power, slew rate and
In addition to their ability to reject noise, Schmitt triggers
hysteresis at various technologies and temperatures. The two
operating points Vth+ and Vth- are evaluated with respect to the are valued for their ability to sharpen slowly varying
supply voltages at different technologies and temperature. waveforms in the absence of noise. This is especially true in
the case of CMOS, for which slowly varying wave-forms
I. INTRODUCTION give rise to increased short circuit conduction and the
associated dissipation.
In [1], the Schmitt trigger has an inverter-like voltage
In [4] This paper explores the sub threshold operation of
transfer characteristics, but with two different logic threshold
the ST and provides complete analytical expressions for its
voltages for increasing and for increasing and for decreasing
design. In this the voltage transfer characteristic of the ST is
input signals. With this unique property, the circuit can be analysed and the origin of the hysteresis is explained.
utilized for the detection of low-to-high and high-to low
switching events in noisy environments. In this the W/L ratio
is also varied as in Fig.1.
In [2], Schmitt triggers are specially constructed bistable
circuits that exhibit hysteresis, therefore input high and low
voltages are depend up on the output state of the device. This
property is useful in signal shaping applications. In addition,
Schmitt trigger display exceptional noise rejection capability
because the sum of the noise margins may exceed the supply
voltage.
In a Schmitt trigger, positive feedback and
greater-than-unity loop gain are required, as with any bistable
circuits. The achievement of hysteresis also requires that
there be a switching element that introduces a state
–dependent voltage between the input and ground. The noise
rejection afforded by hysteresis is especially important if a
signal is to be applied to a count-up or count-down circuit.
This can be understood by considering what happen when a
noisy, slowly varying signal is applied to both a conventional
inverter and a Schmitt trigger.

Revised Manuscript Received on May 05, 2019.

Fig.1 W/L ratio of CMOS Schmitt trigger
K V K V L Pavan Kumar, Electronics and Communication
Engineering, Koneru Lakshmaiah Educational Foundation, Guntur district, II. PROPOSED TECHNIQUE
A.P, India
V.S.V. Prabhakar, Electronics and Communication Engineering, As shown in Fig.2. the two-fold transistor inverter is
Koneru Lakshmaiah Educational Foundation, Guntur district, A.P, India utilized because the transistor (N1 and P1) have some higher
Madala Durga Bhavani, Electronics and Communication Engineering,
Koneru Lakshmaiah Educational Foundation, Guntur district, A.P, India
Kowtharapu Geetha, Electronics and Communication Engineering,
Koneru Lakshmaiah Educational Foundation, Guntur district, A.P, India
Maddukuri Venkatesh, Electronics and Communication Engineering,
Koneru Lakshmaiah Educational Foundation, Guntur district, A.P, India
K Hari Kishore, Electronics and Communication Engineering, Koneru
Lakshmaiah Educational Foundation, Guntur district, A.P, India

Published By:
Blue Eyes Intelligence Engineering
Retrieval Number: G10220587S19/19©BEIESP 106 & Sciences Publication
 Design and Analysis of CMOS Schmitt Trigger

edge voltage than N0 and P0 because of impact and because

of which the yield changes to high from low or low from high
when after the ON state of N1 or P0 separately. Assume N0 is off, while both N1 and N2 operate in saturation
Presently after expansion of two additional transistors P2 region.
and N2 the circuit is able to give hysteresis. At the point when
zero information voltage is connected at the info, both N0 and
N1 are in OFF condition while P0 and P1 are in ON condition
and yield is at high rationale level. At the point when the
information scopes to limit voltage of N0 transistor then N0 Solving this we get
will be on, while N1 stays OFF and this time yield will be
high N2 will be on, while N1 stays OFF and as of now yield
As per assumption N0 is indeed turned off:
will be high N2 will be on so N0 endeavor to pull down the
hub somewhere in the range of N0 and N1 while N2 attempt
to destroys up this hub to voltages. At low voltages, the cross
coupled inverter pair quality is of noteworthy stress during
the advancement and read action, to improve the Continues to decrease. Assuming N1 in linear region and
dauntlessness of data read (0 and 1), Schmitt trigger game N2 in saturation
plan is used. In this structure, ST increases or lessens the
trading edge of an inverter depending upon the course
(PMOS and NMOS) of the yield change. This alteration is
cultivated with the help of course of action transistor analysis
procedure with diminished transistor mean action.
Gate to source voltage of N0

We conclude that upper threshold voltage is

approximately equal to 0.85V
Now by considering a negative input sweep, i.e.: assuming
the input voltage from to 0.

N0 and N1 are on, so that the output voltage = 0V. The

PMOS transistors P0 and P1 are off, and P2 is in saturation,
thus,

P0 is at the edge of turning on, P1 is off, and P2 is in

saturation. The output voltage is still un-changed.

P0 is on and in saturation region. P2 is also in saturation, thus,

Fig. 2 Schematic of CMOS ST Now we determine the gate-to-source voltage of P1 as

III. MATHEMATICAL ANALYSIS This indicates that P1 is still turned off at this point.
In [1], we start our analysis assuming that input voltage is If P1 is still off, P0 is in the linear region, and P2 is in the
increasing from 0 to . saturation region:
P0 and P1 are turned on, then

N0 and N1 are turned off. P2 is off; N2 is on and operates in

saturation region. Calculating the threshold voltage of N2
with 2 = -0.6 V,

N1 turns on, N0 is still off.

Published By:
Blue Eyes Intelligence Engineering
Retrieval Number: G10220587S19/19©BEIESP 107 & Sciences Publication
 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-7S, May 2019

At this point the PMOS transistor P1 is already turned on. Table. 3 Power dissipation of CMOS Schmitt trigger with
Consequently, the output voltage is being pulled up to VDD. respect to temperature and technologies
and concludes that the lower logic threshold voltage is POWER (µW)
approximately equal to 0.35V. Technology 130nm 90nm 60nm 32nm 22nm
In theoretical analysis, =0.85V and =0.35V and as 0º C 3.2132 1.7377 0.5944 0.0422 0.0222
per the practical analysis, =0.907V and =0.129 at an

Temperature
10º C 3.1338 1.6883 0.5809 0.0424 0.0216
operating frequency of 500MHz and a supply voltage of
27º C 3.1139 1.5715 0.5464 0.0396 0.0208
1.2V.
The Table1 describes complementary MOS Schmitt trigger 36º C 3.0483 1.5261 0.5321 0.0396 0.0205
operation is performed with W/L ratios of PMOS & NMOS 50º C 3.0934 1.4720 0.5247 0.0386 0.0204
transistors at different voltages with respect to their 60º C 2.8978 1.4148 0.5017 0.0380 0.0202
technologies.
The output waveforms of complementary MOS Schmitt
Table . 1 WL ratios of CMOS Schmitt trigger at different trigger is in fig3 considering a sinusoidal signal as an input
technologies signal with an operating frequency of 500MHz, DC Offset
Technology 130nm 90nm 60nm 32nm 22nm =0V, Supply voltage VDD=1.2V
Supply 1.2V 1V 0.8V 0.6V 0.5V
Voltage
Length (µm) 0.13 0.09 0.06 0.032 0.022
NMOS

Width (µm) 0.18 0.1 0.075 0.045 0.035

Length (µm) 0.13 0.09 0.06 0.032 0.022
PMOS

Width (µm) 0.26 0.18 0.12 0.064 0.5

IV. RESULT AND ANALYSIS

The Table2 describes complementary MOS Schmitt trigger
operation with different operating point’s vth+ & vth- at various
temperatures with respect to their technologies. Fig. 3 Output Waveforms

Table. 2 Vth+ and Vth- values of CMOS Schmitt trigger From the above fig3, it is observed a square wave output is
operated using different technologies. obtained with unequal time periods i.e. T ON != TOFF that
results in an asymmetrical square wave. It is also observed
Range 130nm 90nm 60nm 32nm 22nm that TON period is large compared with TOFF period.
0º C 790 665 540 460 415
10º C 795 670 540 460 420
Vth+ (mV)

27º C 800 665 535 455 425

36º C 800 670 535 455 425
50º C 795 670 535 460 430
60º C 790 665 540 455 430
0º C 315 330 260 130 150
10º C 325 340 255 130 145
Vth- (mV)

27º C 335 335 265 135 150

36º C 345 330 260 140 150
50º C 340 330 265 140 160
60º C 340 325 260 145 150

In [4], it’s demonstrated that the hypothetical least

offer voltage expected to get hysteresis is
Fig. 4 Power (µW) Vs. Frequency (MHz)

2ln (2+√5) kT/q = 75mV A comparison of power with frequency is in Fig4, From
the fig4, it is observed that the power increases with increase
in frequency. The above graph describes power variation
at room temperature theoretically. And done this practically with frequency from 100MHz to 1000MHz. The minimum
at a frequency of 500MHz a hysteresis of 77.8mV is obtained power is observed at frequency of 100MHz and maximum
practically which is approximately equal to the theoretical power is observed at 1000MHz respectively.
value of 75mV. The Table3 describes complementary MOS
Schmitt trigger operation in terms of power at different
temperatures with respect to their technologies.

Published By:
Blue Eyes Intelligence Engineering
Retrieval Number: G10220587S19/19©BEIESP 108 & Sciences Publication
 Design and Analysis of CMOS Schmitt Trigger

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the fig6, it is observed that the hysteresis increases with
increase in frequency. The above graph describes hysteresis
variation with frequency from 100MHz to 1000MHz. The
minimum hysteresis is observed at frequency of 100MHz and
maximum hysteresis is observed at 1000MHz respectively.
In this context, hysteresis at 500MHz is considered for
designing complementary MOS Schmitt trigger.

V. CONCLUSION
The paper concludes that a Complementary MOS Schmitt
trigger is a power efficient device for the use of many
portable applications and is advantageous over conventional
Schmitt trigger in power by 50%. Complementary MOS
Schmitt trigger presents perfect voltage swings for both logic
0 and logic 1 at 500MHz frequency. It also concludes that the
average power dissipation decreases with increase in
temperature and advancements in technology respectively.
Average power dissipation increases and slew rate decreases
with increase in frequency. The hysteresis obtained at
500MHz is approximately equal to theoretical
hysteresis=77.8mV.

REFERENCES
1. CMOS digital Integrated circuits, Analysis and Design, Sung-Mo Kang
Yusuf Leblebici.

Published By:
Blue Eyes Intelligence Engineering
Retrieval Number: G10220587S19/19©BEIESP 109 & Sciences Publication
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