Circuit and System Analysis

EHB 232E

Prof. Dr. Müştak E. Yalçın

Istanbul Technical University

Faculty of Electrical and Electronic Engineering

[email protected]

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 1 / 15
Outline I

1 Laplace Transform in Circuit Analysis-Cont.

Impedance and Admintance concept in s-domain
Mesh currents method in s-domain
Node-voltage method in s-domain

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 2 / 15
Impedance and Admintance concept in s-domain

If no energy is stored in the inductor or capacitor, the relationship between

the terminal voltage and current for each passive element takes the form:

V (s) = Z (s)I (s)

or
I (s) = Y (s)V (s)
Z (s) is impedance and Y (s) is admintance function.
Resistor has an impedance of R⌦, an inductor has an impedance of Ls⌦,
and a capacitor has an impedance of 1/sC ⌦

KCL and KVL in s-domain

The algebraic sum of the currents/voltages at the node/loop is zero in
time domain, the algebraic sum of the transformed currents/voltages is
also zero.

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 3 / 15
Mesh currents method

Write mesh equations

BV (s) = 0
Laplace transform of the equ.

BV (s) = B1 Ve (s) + B2 Vk (s) = 0

where Vk (s) and Ve (s) = [VR (s) VC (s) VL (s)]T voltages of independent
voltage sources and the others, respectively. The terminal equ.s
2 32 3
0nR ⇥nR 0 0 iR
1
Ve (s) = Z(s)Ie (s) + 4 0 s InC ⇥nC 0 5 4 vC (0) 5
0 0 LnL ⇥nL iL (0)

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 4 / 15
Substituting the above equ. into the mesh equ.
2 32 3
0 0 0 iR
B1 ZIe + B1 4 0 1
sI 0 5 4 vC (0) 5 + B2 Vk = 0
0 0 LI iL (0)

Hence the mesh currents is obtained

2 32 3
0 0 0 iR
B1 ZB1 Ic (s) + B1 4 0 s I
T 1
0 5 4 vC (0) 5 + B2 Vk = 0
0 0 LI iL (0)

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 5 / 15
Example

L3 L4
R1

R2
IC1 IC2
C5

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 6 / 15
 1
M1 L3 sIc1 L3 iL3 (0) + ( Cs + R)(Ic1 Ic2 ) + 1s vC (0) VG = 0
1 1
M2 L4 sIc2 L4 iL4 (0) + R2 Ic2 + ( Cs + R)(Ic2 Ic1 ) s vC (0) = 0

In matrix form
2 3
 1
   1 vC (0)
L3 s Cs R1 Ic1 VG s L3 0 4 iL3 (0) 5
1 = + 1
Cs R1 L4 s + R2 Ic2 0 s 0 L4
iL4 (0)

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 7 / 15
Example

R3

I4

I1 L6 V7
R2 C5

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 8 / 15
 R3

I4

I1 L6 V7
R2 C5

2 32 3
R2 R2 0 0 0 Ic1
6
6 R2 R2 + C15 s 1
C5 s 0 0 7 6
7 6 Ic2
7
7
6 1 1
L6 s 7 6 7
6 0 C5 s C5 s + L6 s 0 7 6 Ic3 7
4 0 0 0 R3 0 5 4 Ic4 5
0 0 0 L6 s L6 s Ic5
2 3 2 3
V1 0 0
6 0 7 6 1/s 0 7 
6 7 6 7 vC (0)
=6
6 V4 7+6
7 6 1/s L6 7 7 iL (0)
4 V4 5 4 0 0 5
V7 0 L6

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 9 / 15
 I1 = Ic1
I4 = 2V2
Ic3 Ic4 = 2V1
2 32 3
R2 R2 0 0 0 1 0 Ic1
6 R2 R2 + C15 s 1
0 0 7
6 C5 s 0 0 766 Ic2 7
7
6 7
6 0 1 1
C5 s + L6 s 0 L6 s 0 1 7 6 Ic3 7
6 C5 s 76 7
6 0 0 0 R3 0 0 1 76 Ic4 7
6 76 7
6 0 0 L6 s 0 L6 s 0 0 7 6 Ic5 7
6 76 7
4 1 0 0 0 0 0 0 5 4 V1 5
0 0 1 1 0 2 0 V4
2 3 2 3
0 0 0
6 0 7 6 1/s 0 7
6 7 6 7
6 0 7 6 1/s L6 7 
6 7 6 7 vC (0)
=6 6 0 7+6 0
7 6 0 7
7 iL (0)
6 V7 7 6 0 L6 7
6 7 6 7
4 I1 5 4 0 0 5
0 0 0
Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 10 / 15
Node-voltage Method
Write the fundamental cut-set equations for the nodes which do not
correspond to node of a voltage sources:
AI (s) = 0
A1 Ie (s) + A2 Ik (s) = 0
where Ik (s) currents of current sources and the currents of others
Ie = [IR IC IL ]
2 32 3
0 0 0 VR
Ie = Y(s)Ve + 4 0 C 0 5 4 vC (0) 5
1
0 0 sI iL (0)
Substituting
2 32 3
0 0 0 VR
A1 Y(s)Ve + A1 4 0 C 0 5 4 vC (0) 5 + A2 ik = 0
1
0 0 sI iL (0)
Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 11 / 15
Using Ve = AT1 Vd , we obtain the node voltage
2 32 3
0 0 0 VR
A1 Y(s)A1 Vd + A1 4 0
T
C 0 5 4 vC (0) 5 + A2 ik = 0
1
0 0 sI iL (0)

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 12 / 15
Example

L4

1 2

C3 R2
I 5
R1

  
G1 + C3 s + L13 s C3 s L13 s Vd1 I5
=
C3 s L13 s G2 + C3 s + L13 s Vd2 0
 1

C3 s v3 (0)
+ 1
C3 s i4 (0)

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 13 / 15
Örnek

R3

I4

I1 L6 V7
R2 C5

  
G2 + G3 + C5 s G3 Vd1 I1 I4
=
G3 G3 + L16 s Vd2 I4 I7
 
1/s 0 v5 (0)
+
0 L6 i6 (0)

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 14 / 15
 V7 = Vd1
I4 = 2V2 = 2Vd1

2 32 3 2 3
G2 + 2 + G3 + C5 s G3 0 Vd1 I1
4 G3 2 G3 + L16 s 1 5 4 Vd2 5 = 4 0 5
1 0 0 I7 V7
2 3
1/s 0 
v5 (0)
+4 0 L6 5
i6 (0)
0 0

Prof. Dr. Müştak E. Yalçın (İTÜ) Circuit and System Analysis Spring, 2020 15 / 15