ISSN 2322-0929

Vol.05, Issue.10,
October-2017,
Pages:0954-0959

www.ijvdcs.org
Design and Implementation of Low Power 16-Bit ALU using MGDI Technique
P. SAI KRISHNA1, P. BRUNDAVANI2
1
PG Scholar, Annamacharaya Institute of Technology and Sciences, India, Email: [email protected].
2
Assistant Professor, Annamacharaya Institute of Technology and Sciences, India, Email: [email protected].

Abstract: Rapid development in portable digital applications, demands for increasing speed, compact implementation, and low
power dissipation triggers numerous research efforts. The wish to improve the performance of logic circuits, once based on
traditional CMOS technology, resulted in the development of many logic design techniques during the last two decades.MGDI
(Modified Gate Diffusion Input) is a technique of low power digital combinational design; Compared to other currently used logic
design styles, allows less power consumption and reduced propagation delay with minimum number of transistors.In this paper a
16 – bit Arithmetic Logic Unit using MGDI Technique is presentedand also compared with CMOS logic. The Arithmetic and
Logical functions that are realized in ALU are Addition,Subtraction,Increment, Decrement operations, AND, OR, XOR, and
XNOR. The simulation tool used is Tanner EDA 32 nm Technology.

Keywords: CMOS (Complementary Metal Oxide Semiconductor), ALU (Arithmetic Logical Unit), GDI (Gate Diffusion Input),
MGDI (Modified Gate Diffusion Input).

I. INTRODUCTION much to the modern era.In this paper a 16 - bit ALU is

Very large scale integration (VLSI)technology has developed designed using GDI Technique and its power dissipation and
to the point where millions of transistor can be implemented transistor count is compared with the CMOS logic. The sub
on a single chip. Complementary metal Oxide semiconductor blocks used are multiplexers, adders and gates. The basic
(CMOS) has been the backbone in mixed signal because it logic gates AND, OR, XOR, XNOR and combinational
reduces powerand providing good mix component for analog circuits like half adder, full adder, multiplexer etc are
and digital design. A processor is a main part of any digital designed and compared with the existing logic styles, CMOS
system such that ALU (Arithmetic and Logic Unit) is a and Transmission Gate , in terms of power dissipation and
fundamental building block of the processor circuit which transistor count. The paper progresses as follows: Section 2
performs arithmetic and logical operations. The power provides some background work on CMOS logics in general
consumed by the ALU has a direct impact in the power and Arithmetic logic unit. In the next, a proposedGDI is
dissipated from the processor. Hence, therequired design is to described in Section 3 and the next section, called section 4,
implement the ALU in a fashion where the performance of Describes ALU using Modified GDI Technology and Its
the processor is improved and also with less power Architecture. In Section 5 the simulation results are shown
consumption. Improving the performance of circuits based on and last of all this paper is concluded in section 6.
CMOS logic by the introduction of many logic styles like
Pass Transistor logic, Transmission Gate logic, Double Pass II. CMOS LOGIC TECHNOLOGY
Transistor logic and also many other hybrid logics. One of the most popular MOSFET technologies available
Improving the performance of circuits based on CMOS logic today is the Complementary MOS or CMOS technology.
by the introduction of many logic styles like Pass Transistor CMOS technology is the dominant semiconductor
logic, Transmission Gate logic, Double Pass Transistor logic technology for microprocessors, memories and application
and also many other hybrid logics, It has many advantages specific integrated circuits (ASICs). The main advantage of
over CMOS i.e., high speed, low powerdissipation and lower CMOS over NMOS and BIPOLAR technology is the much
interconnection effects. GDI Technique can overcome certain smaller power dissipation.This allows integrating many more
drawbacks of CMOS LogicA wide range of complex logic CMOS gates on an IC than in NMOS or bipolar technology,
functions in which PTL was used, can be replaced by GDI resulting in much better performance.
Technique and this makes the circuit simple.
A. Components Design With Cmos Logic
Easier design of fast, low power circuits with less number The various components are designed using complementary
of transistors are enabled using GDI Technique.An metal oxide logic (CMOS logic) are Inverter, AND, OR,
Arithmetic Logic Unit with low power dissipation, lesser MUX etc are given below
transistor count and lesser propagation delay can contribute

Copyright @ 2017 IJVDCS. All rights reserved.

 P. SAI KRISHNA, P. BRUNDAVANI
1. CMOS Inverter
The basic CMOS Inverter as shown in the figure 1 below.
When a low voltage (0 V) is applied at the input, the top
transistor (P-type) is conducting (switch closed) while the
bottom transistor behaves like an open circuit. Therefore, the
supply voltage (5 V) appears at the output.

Fig 3. CMOS OR Gate

4. CMOS Mux Design

A multiplexer is used to select the input as output from
many inputs based on the selection input In 2 to 1 MUX we
Fig 1. CMOS Inverter have 2 inputs an one section line which is used to select the
input to output. The cmos design of Multiplexer is given
Conversely, when a high voltage (5 V) is applied at the below
input, the bottom transistor (N-type) is conducting (switch
closed) while the top transistor behaves like an open
circuit.Hence, the output voltage is low (0 V). The output is
the opposite of the input – this gate inverts the input.

2. CMOS AND Logic

Two PMOS gates are connected in parallel and two
NMOS gates are connected in series such that these modules
are connected together and in between these two modules we
can take output as NAND by providing input to the NMOS
and PMOS transistors and it will feed to normal inverter
which can give results as AND Gate. The Basic CMOS AND
gate is shown in figure below

Fig 4. Basic CMOS MUX Design

B. CMOS Based Full Adder

The 1-bit full adder circuit is one of the most important
components of any digital system applications. The power-
delay product is a measurement of the energy expanded per
operational cycle of an arithmetic circuit.

Fig 2. CMOS AND gate

3. CMOS OR Logic:
Two PMOS gates are connected in series and Two NMOS
gates are connected in Parallel such that these modules are
connected together and in between these two modules we can
take output as NOR by providing input to the NMOS and
PMOS transistors and it will feed to normal inverter which
can give results as OR Gate.
Fig 5. CMOS FULL ADDER
International Journal of VLSI System Design and Communication Systems
Volume.05, IssueNo.10, October-2017, Pages: 0954-0959
 Design and Implementation of Low Power 16-Bit ALU using MGDI Technique
C. Arithmatic And Logic Unit (ALU) differences between the two. The three inputs in GDI are
The arithmetic logic unit (ALU) is the brain of the computer, namely
the device that performs the arithmetic operations like 1. G- common inputs to the gate of NMOS and PMOS
addition and subtraction or logical operations like AND and 2. N- input to the source/drain of NMOS
OR. This section constructs an ALU from four hardware 3. P- input to the source/drain of PMOS Bulks of both
building blocks (AND and OR gates, inverters, and NMOS and PMOS are connected to N or P
multiplexors) and illustrates how combinational logic works.
In the next section, we will see how addition can be sped up Basic GDI cell is given below in figure 8
through more clever designs.

1. 1 bit ALU
An arithmetic-logic unit (ALU) is the part of a
ComputerProcessor (CPU) that carries out arithmetic and
logic operations on the operands in Computer instruction
wordsIn some processors, the ALU is divided into two units,
an arithmetic unit (AU) and a logic unit (LU).The logical
operations are easiest, because they map directly onto the
hardware components in Figure below.
Fig 8. Basic GDI Cell

Table 1 shows how a simple change of the input

configuration of the simple GDI cell corresponds to very
different Boolean functions. Most of these functions are
complex (6–12 transistors) in CMOS, as well as in standard
PTL implementations, but very simple (only two transistors
per function) in the GDI design method.

Table .1 Various Logic Functions Of GDI Cell for

Different Input Configurations

Fig 6. Symbol of ALU

The circuits required to design Arithmetic and Logic unit are

A. GDI Based Multiplexer:

Multiplexer will acts as a digital switch. Selection line
plays a major role to select particular input. If the number of
input lines is “2n” and selection lines will be
‟n”selectionlines. With the “n” selection line the particular
“2n” input line will be selected. Figure 9 shows the
Fig 7. Architecture of 1bit ALU implementation of 2x1 multiplexer.

ALU is a core part of computer or digital processor that

executes arithmetic and logical operation, such as
increment,decrement, addition and subtraction as an
arithmetic operationAND, OR, XOR, XNOR as a logical
operation. ALU isbuild by using FA and multiplexer.

III. EXISTING GDI TECHNOLOGY

The GDI cell is similar to a CMOS inverter structure. In a
CMOS inverter the source of the PMOS is connected to VDD
and the source of NMOS is grounded. But in a GDI cell this
might not necessarily occur.There are some important
Fig 9. GDI Multiplexer
International Journal of VLSI System Design and Communication Systems
Volume.05, IssueNo.10, October-2017, Pages: 0954-0959
 P. SAI KRISHNA, P. BRUNDAVANI

B. GDI Based XOR

XOR gate is the main building block of the full adder
and also which gives the sum output of the full adder. The
number of transistors taken to design the XOR gate is four.

Fig 12. Modified GDI cell

A. MGDI Based XOR:

Conventional XOR gate can be fabricated using GDI logic
needs more than 3 transistors. But here is new design of a
XOR gate with 3 transistors as shown in figure 13 below,
Fig 10. GDI based EXOR gate

C. GDI Based Full Adder

FA is basic functional module for designing ALU. 11T
used for design of FA, this modern design of FA is minimize
the power and reduced the delay. FA depicts in Fig. 11,
circuit is operating at power supply (VDD) 0.9V. Inputs A
apply to the gate terminal of PMOS_1 and NMOS_1, drain
terminal of PMOS_2. Inputs B apply to the gate terminal of
PMOS_2 and PMOS_2, drain terminal of NMOS_1. When
source voltage (VS) is greater than threshold voltage (VTH)
transistor is ON and pass the signal from gate terminal to
drain terminal meanspass the gate voltage (VG) to drain
terminal.
Fig 13. XOR with 3T

By using this 3 Transistor XOR we can minimize the no

of transistors of a full adder.

B. MGDI Based FULL ADDER:

In the GDI Technology It requires 11 Transistors to
design a full adder But in the MGDI we can design an XOR
gate with 3 transistors instead of 4 so that we can able to
design a Full Adder with minimum transistors (8) than GDI
based Full adder

Fig 11. GDI Full Adder Using 11 T

IV. PROPOSED MODIFIED GDI TECHNOLOGY

This modified gate diffusion input (Mod-GDI) logic
style allows reducing power consumption, delay and area of
digital circuits. Fig below shows basic Mod-GDI cell. In
contrast with basic GDI cell, Modified GDI cell contains Fig 14. Full adder With 8 Transistors

International Journal of VLSI System Design and Communication Systems

Volume.05, IssueNo.10, October-2017, Pages: 0954-0959
 Design and Implementation of Low Power 16-Bit ALU using MGDI Technique
C. 16 bit ALU using MGDI Technology V. SIMULATION RESULTS
ALU is a core part of computer or digital processor that A. 16 bit ALU using MGDI Technology:
executes arithmetic and logical operation, such as increment,
decrement, addition and subtraction as an arithmetic
operation & AND, OR, XOR, XNOR as a logical operation.
ALU is build by using FA and multiplexer.

Table 2 TRUTH TABLE OF ALU

FA is mainstays of ALU, 16-bit ALU is design using

16-bitripple carry adder (RCA). RCA is responsible for
arithmeticoperation of ALU. Other modules needed for
designing ALUare 2 is to 1 multiplexer and 4 is to 1
multiplexer. Logicaloperation executes by using multiplexer.
Fig. 7 depicts the 1-bit ALU, 1 bit ALU design using one 4 is
to 1 multiplexer and one2 is to 1 multiplexer and FA.

B. DELAY:

C. AREA:

Fig 15. 16-bit ALU Design

International Journal of VLSI System Design and Communication Systems

Volume.05, IssueNo.10, October-2017, Pages: 0954-0959
 P. SAI KRISHNA, P. BRUNDAVANI
D. POWER: Adder using Modified Branch Based Logic Style,” IEEE
European Modelling Symposium, 2013, pp. 691-696.
[7] L. Dhulipalla and A. Deepak, “Design and
implementation Of 4-bit ALU using FINFETS for
nanoscaletechnology,” IEEE InternationalConference on
Nanoscience, Engineering and Technology , November 2011,
pp. 190–195.
[8] A. Srivastava and C. Srinivasan, “ALU Design Using
Reconfigurable CMOS Logic,” IEEE 45th midwest
symposium on circuit and system, vol. 2, August 2002, pp.
663-666.

Author's Profile:
P. Sai Krishna Received B.tech Degree in
ECE from JNTUA. Currently he is pursuing
M.Tech (VLSI Design) degree from
Annamacharaya Institute of technology and
E. COMPARISON RESULTS: sciences, rajampeta. His General Area of
Table 3. Results of different technologies with parameters Interests include Digital design, Testing.
Parameter\Type CMOS GDI MGDI
P. Brundavani, M.Tech,She received her
No. of Transistors 2752 1264 1200
Master of Technology degree from
Power (watts) 10.768 27.121 17.835 JNTUA.Currently working as Assistant
Delay (ns) 2.556 2.559 9.040 Professor in ECE department of
Annamacharaya Institute of Technology and
sciences, affiliated to JNTUA, Rajampeta,
VI. CONCLUSION
A.P. India. She has published in International Journals and
MGDI (modified Gate diffusion input) is a technique
National Conferences. She has attended many workshops and
of low power digital combinational design This technique as
Seminars. Her research areas are Low Power VLSI, Digital
compare to other currently used logic design styles(GDI and
IC Design, Signal processing, and image processing and
CMOS technologies), allows less power consumption and
communications systems.
reduced propagation delay with minimum number of
transistors. In this paper presented with 16 – bit Arithmetic
Logic Unit using modified Gate Diffusion Input (MGDI)
Technique and also number of transistors is reduced than
existing Systems.
VII. REFERENCES
[1] Rajesh Parihar, Nidhi Tiwari, Aditya Mandloi and
Dr.Binod Kumar, “An Implementation of 1-Bit Low Power
Full Adder Based on Multiplexer and Pass Transistor Logic,”
IEEE International Conferenceon Information
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[2] Ravi Tiwari and KhemrajDeshmukh, “Design and
analysis of low power 11-transistor full adder,” IJAREEIE,
vol. 3, issue 6, June 2014,pp. 10301-10307.
[3] PoojaVaishnav and Mr.VishalMoyal, “Performance
Analysis Of 8-Bit ALU For Power In 32 Nm Scale,” IJERT,
vol. 1, issue 8, October 2012 pp. 1-3.
[4] T. Esther Rani, M.A. Rani and R. Rao, “AREA optimized
low power arithmetic and logic unit,” IEEE International
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[5] Gangadhar Reddy Ramireddy “A Novel Power-Aware
and High Performance Full Adder Cell for Ultra low Power
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and ComputingTechnologies, 2014, pp. 1121-1126.
[6] JVR Ravindra, Gangadhar Reddy Ramireddy and
HarikrishnaKamatham, “Design of Ultra Low Power Full

International Journal of VLSI System Design and Communication Systems

Volume.05, IssueNo.10, October-2017, Pages: 0954-0959