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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT CODE : MVJ19EC34
SUBJECT NAME: DIGITAL SYSTEM DESIGN AND VERILOG
LECTURE PRESENTATION MODULE – 2
DESIGN AND ANALYSIS OF COMBINATIONAL LOGIC AND HDL CONCEPTS

FACULTY : Prof. Anitta D, Asst. Prof, Dept. of ECE

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Digital electronics is a field of electronics involving the study of digital signals and the
engineering of devices that use or produce them. This is in contrast to analog
electronics and analog signals.
Digital electronic circuits are usually made from large assemblies of logic gates, often packaged
in integrated circuits. Complex devices may have simple electronic representations of Boolean
logic functions
DIGITAL SYSTEMS DESIGN USING VERILOG integrates coverage of logic design principles,
Verilog as a hardware design language, and FPGA implementation to help electrical and
computer engineering students master the process of designing and testing new hardware
2
configurations. combinational circuit examples.

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MODULE 1
SYLLABUS
Prerequisites: Number systems, Boolean Algebra, Logic Gates, Comparison of Combinational & Sequential
Circuits.
Principles of combinational logic: Introduction, Canonical forms, Minterm & Maxterm Simplification using
Karnaugh maps-3, 4 variables and Quine- McClusky techniques- 3 & 4 variables. [Text1: Chapter 3- 3.2,3.3,3.4,3.5]
Introduction to HDL: Structure of HDL Module, Operators, Data types, Types of Descriptions, simulation and
synthesis, Brief comparison of VHDL and Verilog. [Text 5: Chapter 1]
MODULE 2
Design and Analysis of combinational logic: Full Adder & Subtractors, Parallel Adder and Subtractor, Look ahead
carry Adder, Binary comparators. Decoder, Encoders, Multiplexers & Demultiplexer, Decoders & Multiplexers as
minterm/maxterm Generator. [Text 1: Chapter4- 4.3 to 4.6.2, 4.7]
HDL Concepts: Verilog Models for Full Adder & Subtractors, Parallel Adder and Subtractor, Look ahead carry Adder,
3
Binary comparators.[[Text 5: Chapter 2- 2.2, 2.3] Decoder, Encoders, Multiplexers & Demultiplexer (Data flow &
Structural descriptions) [Text:4 Chapter6: 6.6]
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MODULE 3
Flip-Flops and its Applications: Basic Bi-stable Element, Latches and Flip Flops - SR, JK, Master-slave JK flip-
flops, D, T; Timing considerations in sequential circuits, Characteristic equations, Registers.[ Text 2: Chapter 6:6.1 to
6.3, 6.4.2, 6.6-6.7]
HDL Concepts: Sequential circuit design on Flipflops in Verilog (behavioural description)

MODULE 4
Sequential Circuit Design: Asynchronous Counter, Design of a synchronous mod-n counter using clocked JK, D, T
and SR flip-flops, Melay & Moore Models, Synchronous Sequential circuit Analysis. [ Text 2: Chapter 6-6.8-6.9]
HDL Concepts: Sequential circuit design on Synchronous and Asynchronous Counters in Verilog.

MODULE 5
Synthesis Basics: Introduction, Synthesis information from Entity and Module, Mapping Process and Always in the
Hardware Domain. [Text 5: Chapter 10] 4

Programmable Logic Devices: PLA, PAL, FPGA(Qualitative Approach) .[ Text 3: Chapter 3]

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 MODULE STRUCTURE

• Design and Analysis of combinational logic:

• Full Adder & Subtractor

• Parallel Adder and Subtractor

• Look ahead carry Adder

• Binary comparators

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 MODULE STRUCTURE

• Design and Analysis of combinational logic:

• Decoder,

• Encoders,

• Multiplexers & Demultiplexer,

• Decoders & Multiplexers as minterm/maxterm Generator.

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 MODULE STRUCTURE

• HDL Concepts:

• Verilog Models for Full Adder & Subtractors

• Parallel Adder and Subtractor

• Look ahead carry Adder

• Binary comparators

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 MODULE STRUCTURE

• HDL Concepts:

• Decoder

• Encoders

• Multiplexers & Demultiplexer

(Data flow & Structural descriptions)

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 REFERENCE BOOKS

• John M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2001.

• Donald D. Givone, ―Digital Principles and Design‖, McGraw Hill, 2002.

• Charles H. Roth. Jr. - Digital Systems Design using Verilog, Thomson Learning, Inc, I edition
2015.

• “Fundamentals of Digital Logic with Verilog Design”- Stephen Brown, Zvonko Vranesic, Tata
McGraw Hill, 2002

• “HDL Programming (VHDL and Verilog)”- Nazeih M.Botros- John Weily India Pvt. Ltd. 2008

• Samir Palnitkar ―Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson
9

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 COURSE OUTCOME

• Illustrate simplification of Algebraic equations using K-map & Quine-McCluskey Technique.

• Use the modern engineering tools such as verilog, necessary for engineering practice.

• Analyze & design different applications of Combinational & Sequential Circuits to meet

desired need within realistic constraints.

• Write code & verify the functionality of digital circuit/system using test benches to solve

engineering problems in digital circuits.

• Know the importance of Synthesis & programmable devices used for designing digital circuits.
10

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 BRIDGE MATERIAL

• Boolean Algebra

• Logic Gates

• Combinational circuits.

• Binary Arithmetic

11
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 BINARY ARITHMETIC

Binary is a base-2 number system that uses two states 0 and 1 to represent a number. We can also
call it to be a true state and a false state. A binary number is built the same way as we build the
normal decimal number.

Binary arithmetic is an essential part of various digital systems. You can add, subtract, multiply,
and divide binary numbers using various methods. These operations are much easier than decimal
number arithmetic operations because the binary system has only two digits: 0 and 1.

All arithmetic operations such as addition, subtraction, multiplication, and division are done in
binary representation of numbers. It is necessary to understand the binary number representation to
figure out binary arithmetic in digital computers. 12

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 TYPES OF BINARY ARTHIMETIC

• ADDITION

• SUBTRACTION

• MULTIPLICATION

• DIVISION

13

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 BINARY ADDITION

Binary additions and subtractions are performed as same in decimal additions and subtractions.
Binary additions, will have two outputs: Sum (S) and Carry (C).

There are four rules for binary addition:

INPUT A INPUT B SUM (S) A+B CARRY (C)

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1 14

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 BINARY ADDITION

EXAMPLE:

0 0 1 1

1 0 1 0
+ -------------------------
1 1 0 1
--------------------------

15

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 SELF ASSESSMENT QUESTIONS?

16

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1
 ADD THE FOLLOWING BINARY NUMBERS:

1. (1 0 0 1 ) 2 a n d ( 0 1 0 1 ) 2

2. (101.01)2 and (1101.10)2

3. 10001 + 11101

4. 1011.01 + 11001

5. 11011 + 10.01010

6. 10.111 + 1101.01
17

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 BINARY SUBTRACTION

There are four rules for binary subtraction:

Borrow 1 is required from the next higher order bit to subtract 1 from 0. So, the result became 0.

SUBTRACT BORROW
INPUT A INPUT B
(S) A-B (B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0 18

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 BINARY SUBTRACTION
1’S COMPLEMENT

• The 1’s complement of binary number is obtained by changing each 0 to 1 and each 1 to
0, both the numbers complement each other.

• If one of these number is positive , the other will be negative with same magnitude and vice
versa.

2’S COMPLEMENT

• If 1 is added to 1’s complement of a number then it will obtain the 2’s complement of the number.

19

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 SUBTRACTION USING 1’S COMPLEMENT

 SUBTRACTION OF SMALLER NUMBER FROM A LARGER NUMBER

1. Calculate the 1’s complement of a smaller number.

2. Add the 1’s complement to the larger number.

3. If carry comes in the MSB , remove the carry and add it to the result.

20

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 SUBTRACTION USING 1’S COMPLEMENT

 SUBTRACTION OF LARGER NUMBER FROM A SMALLER NUMBER

1. Calculate 1’s complement of a larger number.

2. Add 1’s complement in smaller number

3. The result will be in 1’s complement form.

4. If no carry calculate 1’s complement of final value and assign –ve sign to the result.

21

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 ADVANTAGES OF USING 1’S COMPLEMENT
SUBTRACTION
1. This can be easily obtained by simply inverting each bit in the number

2. This subtraction can be done with an binary adder. Thus ,it is useful in arithmetic logic
circuits.

22

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 SUBTRACTION USING 1’S COMPLEMENT
M=1 0 1
 EXAMPLE
N= 1 1 0 0 0 1

1’S COMPLEMENT OF N = 0 0 1 1 1 0

SIGNED
BIT MAGNITUDE

M= 0 0 0 0 1 0 1

N= 1 0 0 1 1 1 0

ADD (M+N) = 1 0 1 0 0 1 1

NO CARRY = 1’S COMPLEMENT OF ANSWER = 0 1 0 1 1 0 0

23
PUT – SIGN = -0 1 0 1 1 0 0 =-44

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 SUBTRACTION USING 1’S COMPLEMENT
M = 5 0 4 = (1 1 1 1 1 1 0 0 0 )
 EXAMPLE N= 2 9 0 = (1 0 0 1 0 0 0 1 0 )

1’S COMPLEMENT OF N = 0 1 1 0 1 1 1 0 1

SIGNED
BIT MAGNITUDE

M= 0 1 1 1 1 1 1 0 0 0

N= 1 0 1 1 0 1 1 1 0 1
carry
ADD (M+N) = 1 0 0 1 1 0 1 0 1 0 1

Carry Generated Add Carry To Result 0 0 1 1 0 1 0 1 0 1

+ 1
----------------------------- 24
0 0 1 1 0 1 0 1 1 0
= 504-290= ( 214 )
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 SUBTRACTION USING 2’S COMPLEMENT

 SUBTRACTION OF SMALLER NUMBER FROM A LARGER NUMBER

1. Calculate the 2’s complement of a smaller number.

2. add the 2’s complement to the larger number.

3. If carry comes in the MSB , discard the carry .

25

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 SUBTRACTION USING 2’S COMPLEMENT

SUBTRACTION OF LARGER NUMBER FROM A SMALLER NUMBER

1. Calculate 2’s complement of a larger number.

2. Add 2’s complement in smaller number

3. The result will be in 2’s complement form.

4. If no carry calculate 2’s complement of final value and assign –ve sign to the result.

26

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 SUBTRACTION USING 2’S COMPLEMENT
M=1 0 1
 EXAMPLE
N= 1 1 0 0 0 1

2’S COMPLEMENT OF N = 0 0 1 1 1 0 + 1 = 0 0 1 1 1 1

SIGNED
BIT MAGNITUDE

M= 0 0 0 0 1 0 1

N= 1 0 0 1 1 1 1

ADD (M+N) = 1 0 1 0 1 0 0

NO CARRY = 2’S COMPLEMENT OF ANSWER = 0 1 0 1 0 1 1

+ 1 27
---------------------
PUT – SIGN = -0 1 0 1 1 0 0 =-44 0 1 0 1 1 0 0
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 SUBTRACTION USING 2’S COMPLEMENT
M = 5 0 4 = (1 1 1 1 1 1 0 0 0 )
 EXAMPLE
N= 2 9 0 = (1 0 0 1 0 0 0 1 0 ) = 0 1 1 0 1 1 1 0 1

2’S COMPLEMENT OF N = 0 1 1 0 1 1 1 0 1
+1
-----------------------------
=0 1 1 0 1 1 1 1 0

SIGNED
BIT MAGNITUDE

M= 0 1 1 1 1 1 1 0 0 0

N= 1 0 1 1 0 1 1 1 1 0
carry
ADD (M+N) = 1 0 0 1 1 0 1 0 1 1 0 28

Carry Generated Discard Carry = 0 0 1 1 0 1 0 1 1 0 = 504-290= ( 214 )

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 UNSIGNED AND SIGNED NUMBERS

 UNSIGNED NUMBERS

1. Numbers without any positive and negative sign.

2. Represents only magnitude

29

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 SIGN MAGNITUDE NUMBERS

 In binary number system, both +ve and –ve values are possible.

 In this , we use 0’s and 1’s to represent every number.

The representation of number is known as number.
This kind of representation for signed numbers is called as signed magnitude
representation.

￫
0 +ve number

1 ￫ -ve number.
Eg:- +7=0111

-7=1111

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 DIFFERENT METHODS FOR THE
REPRESENTATION OF BINARY SIGNED NUMBERS

1. Sign magnitude form

2. 1’s complement form

3. 2’s complment form

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 BINARY SUBTRACTION
2’S COMPLEMENT
1’S COMPLEMENT
EXAMPLE: 0 0 1 1
0 0 1 1
0 1 0 1
1 0 1 0 1 -----------------------
0 0 1 1 (3) ---------------------- 1 0 0 0
1 0 0 0 1
------------------
- 1 0 1 0 (10)
------------------------- No carry take 1’s complement 1 0 0 1
No carry take 2’s
1 0 0 1 (-7) of result and put - sign
-------------------------- Complement of result
-0 1 1 1 (-7) and put - sign

0 1 1 0
1 32
-----------------------
0 1 1 1 (-7)
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 SELF ASSESSMENT QUESTIONS?

33

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 SUBTRACT THE FOLLOWING BINARY
NUMBERS
1. (0110)2 from (1010)2

2. (01011)2 from (11011)2

3. 10110.11 − 100.10

4. 1010110 − 101010

5. 100010110 − 1111010

6. 101101 − 100111

34
7. 1110110 − 1010111

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 BINARY MULTIPLICATION
There are four rules for binary multiplication:

Multiplication is always 0, whenever at least one input is 0.

MULTIPLY
INPUT A INPUT B
(AB)
0 0 0
0 1 0
1 0 0
1 1 1

35

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 BINARY MULTIPLICATION
As in decimal system, the multiplication of binary numbers is carried out by multiplying the
multiplicand by one bit of the multiplier at a time and the result of the partial product for each bit is
placed in such a manner that the LSB is under the corresponding multiplier bit. Finally the partial
products are added to get the complete product.

1000 =810
X 0110 =610

0000
+1000
+1000
+0000 36

011 000 0 = 4810

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 SELF ASSESSMENT QUESTIONS?

37

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 MULTIPLY THE FOLLOWING BINARY NUMBERS
1. 10111 by 1101

2. 11011.101 by 101.111

3. (111)2 * (101)2

4. (1010.01)2 * (1.01)2

38

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 BINARY DIVISION

There are four parts in any division: Dividend, Divisor, quotient, and remainder.
The result is always not defined, whenever the divisor is 0.

DIVIDE D
INPUT A INPUT B
(A/B)
NOT
0 0
DEFINED
0 1 0
NOT
1 0
DEFINED
1 1 1 39

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BINARY DIVISION
011 ) 0 1 1 0 0 1 0 (1
011
000 (0
000
000 (0
000
001 (0
000
010
Q=1000=1610

R=10= 210 40

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 SELF ASSESSMENT QUESTIONS?

41

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 DIVIDE THE FOLLOWING BINARY NUMBERS
1. (111101)2 by (100)2

2. (110101.11)2 by (101)2

3. (1010.1)2 by (101.01)2

4. 11001 ÷ 101

5. 11101.01 ÷ 1100

6. 10110.1 ÷ 1101

7. 101.11 ÷ 111

42

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 ADDERS AND SUBTRACTORS

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 ADDERS

• Adders are digital circuits that carry out addition of numbers. Adders are a key component of
Arithmetic Logic unit. Adders can be constructed for most of the numerical representations like
Binary Coded Decimal (BDC), Excess – 3, Gray code, Binary etc. out of these, binary addition is
the most frequently performed task by most common adders. Apart from addition, adders are
also used in certain digital applications like table index calculation, address decoding etc.

44

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 HALF ADDER

Half adder is a combinational circuit that performs simple addition of two binary numbers.
The block diagram of a half adder is shown below.

A SUM
HALF
ADDER
B CARRY

45

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 HALF ADDER TRUTH TABLE

If we assume A and B as the two bits whose addition is to be performed, a truth table for half
adder with A, B as inputs and Sum, Carry as outputs can be tabulated as follows.

TRUTH TABLE

A B SUM (S) CARRY (C)

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
46

SUM = ∑ ( 1,2) CARRY = ∑ ( 3 )

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 HALF ADDER K-MAP
• SUM = ∑ ( 1,2)

• CARRY = ∑ ( 3 )

LSB LSB
B’ B B’ B
MSB b MSB b
a 0 1 a 0 1
a’b’ a’b a’b’ a’b
0 0
A’ 0 1 A’ 0 0
ab’ ab ab’ ab
A 1 1 0 A 1 0 1

SUM = A’B + AB’ CARRY = AB

47

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HALF ADDER LOGIC DIAGRAMS

48

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 VERILOG

• Verilog HDL has a syntax that describes precisely the legal constructs that can be used in
the language.

• It uses about 100 keywords pre-defined, lowercase, identifiers that define the language
constructs.

• Example of keywords: module, endmodule, input, output wire, and, or, not , etc.,

• Any text between two slashes (//) and the end of line is interpreted as a comment.

• Blank spaces are ignored and names are case sensitive.

49

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 DATAFLOW MODELING

• Dataflow modeling uses a number of operators that act on operands to produce desired
results.

• Verilog HDL provides about 30 operator types.

• Dataflow modeling uses continuous assignments and the keyword assign.

• A continuous assignment is a statement that assigns a value to a net.

• The value assigned to the net is specified by an expression that uses operands and
operators.

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 VERILOG - MODULE
• A module is the building block in Verilog.

• It is declared by the keyword module and is always terminated by the keyword endmodule.

• Each statement is terminated with a semicolon, but there is no semi-colon after endmodule.

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 VERILOG – MODULE

HDL Example
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y,C);
or g3(x,e,y);
endmodule
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 HALF ADDER DATAFLOW MODELING

module halfadder( input a, input b, output sum,output carry );

assign sum=a ^ b ;

assign carry=a & b;

endmodule

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 FULL ADDER
Full adder is a digital circuit used to calculate the sum of three binary bits which is the main difference
between this and half adder. Full adders are complex and difficult to implement when compared to half
adders. Two of the three bits are same as before which are A, the augend bit and B, the addend bit. The
additional third bit is carry bit from the previous stage and is called Carry – in generally represented by
CIN. It calculates the sum of three bits along with the carry. The output carry is called Carry – out and is
represented by COUT.

The block diagram of a full adder with A, B and CIN as inputs and S, CoUT as outputs is shown below

A SUM
FULL
B
ADDER
54
CIN CARRY

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 FULL ADDER TRUTH TABLE
If we assume A and B as the two bits whose addition is to be performed, a truth table for full adder
with A, B and Cin as inputs and Sum, Carry as outputs can be tabulated as follows.
TRUTH TABLE
SUM CARRY
A B CIN
(S) (COUT)
0 0 0 0 0 SUM = ∑ ( 1,2,4,7)
0 0 1 1 0 CARRY = ∑ ( 3,5,6,7 )
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
55
1 1 0 0 1
1 1 1 1 1
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 FULL ADDER K-MAP
• SUM = ∑ ( 1,2,4,7)

• CARRY = ∑ ( 3,5,6,7 )

BC BC
00 01 11 10 00 01 11 10
A A
0 0
1
1 3
1
2 0 0 1
1
3 2

1 1 1 1 1 1 1
4 5 7 6 4 5 7 6

SUM = AB’C’ + A’B’C + ABC + A’BC’ CARRY = AC + BC + AB 56

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FULL ADDER LOGIC DIAGRAMS

57

SUM = AB’C’ + A’B’C + ABC + A’BC’ CARRY = AC + BC + AB

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 FULL ADDER USING HALF ADDERS

A full adder can be formed by logically connecting two half adders. The block diagram that shows the
implementation of a full adder using two half adders is shown below.

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FULL ADDER USING HALF ADDERS

SUM = A ⊕ B ⊕ C

CARRY = (A⊕B)CIN + AB

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 FULL ADDER DATAFLOW MODELING
module fulladder(input a,input b,input cin,output sum,output carry );

assign x=a ^ b;

assign sum=x^cin;

assign y=x & cin;

assign z=a & b;

assign carry= y | z;

endmodule
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 SUBTRACTOR

Subtractor is an electronic logic circuit for calculating the difference between two binary

numbers which provides the difference and borrow as output.

The subtractor circuit uses binary numbers (0,1) for the subtraction. The circuit of the half

subtractor can be built with two logic gates namely NAND and EX-OR gates. This circuit gives

two elements such as the difference as well as the borrow

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 HALF SUBTRACTOR

Half Subtractor is used for subtracting one single bit binary number from another single bit
binary number.It has two inputs; Minuend (A) and Subtrahend (B) and two outputs;
Difference(D) and Borrow (Bout).

A DIFFERENCE
HALF
SUBTRACTOR
B BORROW

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 HALF SUBTRACTOR TRUTH TABLE
Half-subtractor is used to subtract the LSB of the subtrahend to the LSB of the minuend when
one binary number is subtracted from another. Subtraction is done according to the rule of binary
subtraction and the operations can be summarized in a truth table as,

TRUTH TABLE
DIFFERENC BORROW
A B
E (D) (B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0 63

DIFFERENCE= ∑ ( 1,2) BORROW = ∑ ( 1 )

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 HALF SUBTRACTOR K-MAP
• DIFFERENCE = ∑ ( 1,2)

• BORROW = ∑ ( 1 )

LSB LSB
B’ B B’ B
MSB b MSB b
a 0 1 a 0 1
a’b’ a’b a’b’ a’b
0 0
A’ 0 1 A’ 0 1
ab’ ab ab’ ab
A 1 1 0 A 1 0 0

DIFFERENCE= A’B + AB’ BORROW = A’B

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HALF SUBTRACTOR LOGIC DIAGRAMS

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 HALF SUBTRACTOR DATAFLOW MODELING

module half_sub( input a,input b,output diff,output borrow);

assign diff=a^b;

assign borrow=(~a)&b;

endmodule

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 FULL SUBTRACTOR

• A logic Circuit Which is used for subtracting three single bit binary numbers is known as Full
Subtractor. It has three inputs; Minuend (A), Subtrahend (B) and following Subtrahend (C) and two
outputs: Difference (D) and Borrow (Bout).

A DIFFERENCE
FULL
B
SUBTRACTOR
BIN BORROW

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 FULL SUBTRACTOR TRUTH TABLE
If we assume A and B as the two bits whose subtraction is to be performed, a truth table for full
subtractor with A, B, Bin as inputs and Difference and Borrow as outputs can be tabulated as follows.
TRUTH TABLE
DIFF BORRO
A B BIN
(D) W (BOUT)
0 0 0 0 0 DIFF= ∑ ( 1,2,4,7)
0 0 1 1 1 BORROW = ∑ ( 1,2,3,7 )
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
68
1 1 0 0 0
1 1 1 1 1
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 FULL SUBTRACTOR K-MAP
• SUM = ∑ ( 1,2,4,7)

• CARRY = ∑ ( 1,2,3,7 )

BC BC
00 01 11 10 00 01 11 10
A A
0 0
1
1 3
1
2 0 0
1
1
1
3
1
2

1 1 1 1 1
4 5 7 6 4 5 7 6

DIFFERENCE = AB’C’ + A’B’C + ABC + A’BC’ BORROW = A’C + A’B + BC 69

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FULL SUBTRACTOR LOGIC DIAGRAMS

70

SUM = AB’C’ + A’B’C + ABC + A’BC’ BORROW = A’C + A’B + BC

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 FULL SUBTRACTOR USING HALF
SUBTRACTOR
A full subtractor can be formed by logically connecting two half subtractors. The block diagram that shows the
implementation of a full subtractor using two half subtractors is shown below.

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FULL SUBTRACTOR USING HALF
SUBTRACTORS

DIFFERENCE = A ⊕ B ⊕ C

BORROW = (A⊕B)’BIN + A’B

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 FULL SUBTRACTOR DATAFLOW MODELING
module full_sub( input a,input b,input c,output diff, output borrow);

assign x= b^c;

assign diff = a ^ x;

assign n1=~c;

assign y=b & n1;

assign n2=~x;

assign z=a & n2;

assign borrow = y | z;
73

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 CASCADING FULL ADDERS

•A single full adder performs the addition of two one bit numbers and an input carry. But
a Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary numbers
that is greater than one bit in length by operating on corresponding pairs of bits in parallel. It
consists of full adders connected in a chain where the output carry from each full adder is
connected to the carry input of the next higher order full adder in the chain.

•A n bit parallel adder requires n full adders to perform the operation. So for the two-bit number,
two adders are needed while for four bit number, four adders are needed and so on.

• Parallel adders normally incorporate carry look ahead logic to ensure that carry propagation
between subsequent stages of addition does not limit addition speed. 74

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CASCADING FULL ADDERS

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 FOUR BIT ADDER

• As shown in the figure, firstly the full adder FA1 adds A1 and B1 along with the carry C1 to
generate the sum S1 (the first bit of the output sum) and the carry C2 which is connected to
the next adder in chain.

• Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2 and B2 to generate
the sum S2(the second bit of the output sum) and the carry C3 which is again further
connected to the next adder in chain and so on.

• The process continues till the last full adder FA4 uses the carry bit C3 to add with its input A4
and B4 to generate the last bit of the output along last carry bit Cout.

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 77

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CASCADING FULL ADDERS

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 CASCADING FULL ADDERS
•An n bit adder can be built by cascading n full adders. Each full adder represents a bit position.
The least significant bit position can be a half adder, because a carry from a least significant
position does not exist. Each carry out from a half adder becomes the carry-in to the next higher
order adder.

•The carry-in input of least significant full adder is grounded. The two binary inputs (X and Y) are
presented to the adder from some external source. The logic designer must know how much
time the logic requires for the addition of two binary numbers. The add time required is
determined by calculating the propagation delays.

•The carries propagate from one full adder to the next higher order full adder. This type of
addition is called ripple carry propagation. 79

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 RIPPLE CARRY PROPAGATION

•Total delay time is the product of the sum of the number of stages in the adder and the carry-in
to carry-out propagation delay time. The carry-in to carry-out propagation delay is used instead
of the input to sum output delay because it is the signal that ripples from one full adder to
another.

•Assume that an adder is realized using an 74ALS86 (EX-OR), 74AS08 ( two input AND) and
74AS802 ( four input OR)

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 RIPPLE CARRY PROPAGATION
Delay time for each IC in TTL book is

Parameter AS08 AS802 ALS86

tpLH 6ns 5ns 8ns

• The propagation time from any data input (X, Y, Cin) to the sum output is

Tpd = 8ns +8ns = 16ns ( 2 EX-OR gate )

• Propagation time from any data input (X, Y, Cin) to the Cout of a full adder using half adder is:

Tpd = 8ns + 6ns +5ns = 19ns ( EX-OR ,AND, OR gate)

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 LOOK AHEAD CARRY ADDER
• A digital computer must contain circuits which can perform arithmetic operations such as
addition, subtraction, multiplication, and division. Among these, addition and subtraction are the
basic operations whereas multiplication and division are the repeated addition and subtraction
respectively.

• To perform these operations ‘Adder circuits’ are implemented using basic logic gates. Adder
circuits are evolved as Half-adder, Full-adder, Ripple-carry Adder, and Carry Look-ahead Adder.

• Among these Carry Look-ahead Adder is the faster adder circuit. It reduces the propagation
delay, which occurs during addition, by using more complex hardware circuitry. It is designed by
transforming the ripple-carry Adder circuit such that the carry logic of the adder is changed into
two-level logic.
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 LOOK AHEAD CARRY ADDER
• In parallel adders, carry output of each full adder is given as a carry input to the next higher-
order state. Hence, these adders it is not possible to produce carry and sum outputs of any state
unless a carry input is available for that state. So, for computation to occur, the circuit has to wait
until the carry bit propagated to all states. This induces carry propagation delay in the circuit.

• In a carry look ahead adder, the carry input at any stage of the adder is independent of the carry
bits generated at the independent stages. Here the output of any stage is dependent only on the
bits which are added in the previous stages and the carry input provided at the beginning stage.
Hence, the circuit at any stage does not have to wait for the generation of carry-bit from the
previous stage and carry bit can be evaluated at any instant of time.

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 TRUTH TABLE FOR LOOK AHEAD CARRY
ADDER
• It can be observed from the equations that carry Ci+1 only depends on the carry C0, not on the
intermediate carry bits.
TRUTH TABLE
A B Ci Ci+1 Condition
0 0 0 0
0 0 1 0 No carry generate
0 1 0 0
0 1 1 1
1 0 0 0 No carry propagate
1 0 1 1
1 1 0 1 84
Carry generate
1 1 1 1
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 TRUTH TABLE FOR LOOK AHEAD CARRY
ADDER
• For deriving the truth table of this adder, two new terms are introduced – Carry generate and
carry propagate. Carry generate Gi =1 whenever there is a carry Ci+1 generated. It depends on
Ai and Bi inputs. Gi is 1 when both Ai and Bi are 1. Hence, Gi is calculated as Gi = Ai. Bi.

• Carry propagated Pi is associated with the propagation of carry from Ci to Ci+1. It is calculated
as Pi = Ai ⊕ Bi. The truth table of this adder can be derived from modifying the truth table of a
full adder.

• AB = ( Cg) C(A+B) = (Cp)

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 EQUATIONS FOR LOOK AHEAD CARRY ADDER
• A carry for jth stage is generated when i/p Xj and Yj produce Coutj =1 independent of any preceding
stage input

Xj-1 , Yj-1………….XoYo

• A carry for jth stage is propagated when Coutj =1 based on receiving a Cinj from Coutj-1

• Carry generated Cg and carry propagated Cp can be formed by

let Cg = X Y Cp = X + Y

Cout = Cg + Cp Cin

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• Consider the full adder circuit shown above with corresponding truth table. We define two
variables as ‘carry generate’ and ‘carry propagate’ then,

• The sum output and carry output can be expressed in terms of carry generate and carry
propagate as

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 88

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 The carry output Boolean function of each
stage in a 4 stage carry look-ahead adder
can be expressed as

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• module carry_lookahead_adder_4_bit
• (
• input [3:0] i_add1,
• input [3:0] i_add2,
• output [4:0] o_result
• );
•
• wire [4:0] w_C;
• wire [3:0] w_G, w_P, w_SUM;
•
• full_adder full_adder_bit_0
• (
• .i_bit1(i_add1[0]),
• .i_bit2(i_add2[0]),
• .i_carry(w_C[0]),
• .o_sum(w_SUM[0]),
• .o_carry()
• ); 90

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• full_adder full_adder_bit_1
• (
• .i_bit1(i_add1[1]),
• .i_bit2(i_add2[1]),
• .i_carry(w_C[1]),
• .o_sum(w_SUM[1]),
• .o_carry()
• );
•
• full_adder full_adder_bit_2
• (
• .i_bit1(i_add1[2]),
• .i_bit2(i_add2[2]),
• .i_carry(w_C[2]),
• .o_sum(w_SUM[2]),
• .o_carry()
• ); 91

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• full_adder full_adder_bit_3
• (
• .i_bit1(i_add1[3]),
• .i_bit2(i_add2[3]),
• .i_carry(w_C[3]),
• .o_sum(w_SUM[3]),
• .o_carry()
• );

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• // Create the Generate (G) Terms: Gi=Ai*Bi
• assign w_G[0] = i_add1[0] & i_add2[0];
• assign w- G[1] = i_add1[1] & i_add2[1];
• assign w_G[2] = i_add1[2] & i_add2[2];
• assign w_G[3] = i_add1[3] & i_add2[3];
•
• // Create the Propagate Terms: Pi=Ai+Bi
• assign w_P[0] = i_add1[0] ^ i_add2[0];
• assign w_P[1] = i_add1[1] ^ i_add2[1];
• assign w_P[2] = i_add1[2] ^ i_add2[2];
• assign w_P[3] = i_add1[3] ^ i_add2[3];
•
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• // Create the Carry Terms:
• assign w_C[0] = 1'b0; // no carry input
• assign w_C[1] = w_G[0] | (w_P[0] & w_C[0]);
• assign w_C[2] = w_G[1] | (w_P[1] & w_C[1]);
• assign w_C[3] = w_G[2] | (w_P[2] & w_C[2]);
• assign w_C[4] = w_G[3] | (w_P[3] & w_C[3]);
•
• assign o_result = {w_ C[4], w_SUM}; // Verilog Concatenation
•
• endmodule // carry_lookahead_adder_4_bit

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 Code Converters – BCD(8421) to/from Excess-3
• The Excess-3 binary code is an example of a self-complementary BCD code. A self-
complementary binary code is a code which is always complimented in itself. By replacing the bit 0
to 1 and 1 to 0 of a number, we find the 1's complement of the number. The sum of the 1's
complement and the binary number of a decimal is equal to the Excess 3 of decimal 9.

• The process of converting BCD to Excess-3 is quite simple from other conversions. The Excess-
3 code can be calculated by adding 3, i.e., 0011 to each four-digit BCD code. Below is the truth
table for the conversion of BCD to Excess-3 code.

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 The sum of the 1'st complement and the binary
number of a decimal is equal to excess 3 of
number 9.

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• To find the corresponding digital circuit, we will use the K-Map technique for each of the
Excess-3 code bits as output with all of the bits of the BCD number as input.

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• Why use Excess-3 code?
• There are the following advantages of excess-3 code which make it required to use:
• These codes are self-complementary.
• These codes use biased representation.
• The excess-3 code has no limitation, so that it considerably simplifies arithmetic
operations.
• The codes 0000 and 1111 can cause a fault in the transmission line. The excess-3 code
doesn't use these codes and gives an advantage for memory organization.

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 100

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 101

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Corresponding minimized boolean expressions for Excess-3 code bits

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4-BIT CARRY LOOK AHEAD ADDER

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 ADVANTAGES OF CARRY LOOK AHEAD ADDER

• CLA Adders generate the carry-in for each full adder simultaneously, by using simplified
equations involving Pi, Gi, and Cin.

• This system reduces the propagation delay. This is because the output carry at any stage is
dependent only on the first Carry signal given at the input.

• It is the fastest adder when compared to other addition mechanisms.

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 DISADVANTAGES OF CARRY LOOK AHEAD
ADDER

• The carry-lookahead adder circuit gets more complicated as the number of variables increase.

• The circuit for a carry-lookahead adder is expensive as it involves more hardware.

• As the number of variables increases, the circuit implements more hardware. Thus, when the
carry-lookahead adder is implemented as an IC, the area is bound to increase.

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 SUBTRACTOR
In general subtraction, we made as A-B. Means A+(-B). We can write it as 2’s Complement of B is added to the
A.

2’s complement means 1’s complement +1. We make add inverter across B and take as carry 1. then it will also
acts as 2’s complement of B.

Then we make add that toA, by using adder circuit.

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 SUBTRACTOR
The number to be subtracted (B) is first passed through inverters to obtain its 2’s complement. The
4-bit adder then adds A and 2’s complement of B to produce the subtraction. S3 S2 S1 S0
represents the result of binary subtraction (A-B) and carry output Cout represents the polarity of the
result. If A > B Cout = 0. if Cout = 1 and the result is in the 2’s complement form.

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 4-BIT ADDER/SUBTRACTOR
K =1 = subtractor K =0 = adder

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Note:
•To perform addition make k = '0'
•To perform 1's complement subtraction
•make k = '1' and connect Cout to Cin.
•To perform 2's complement subtraction
• make k = '1' and Cin = '1‘,cout should be connected

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 Full Adder - EXAMPLE OF DATAFLOW
DESCRIPTION
VHDL1B DESCRIPTION VERILOG DESCRIPTION

entity full_add is module full_ add (A, B, Cin, Cout, Sum);

port (A, B, Cin : in bit; input A, B, Cin;
Sum, Cout : out bit);
output Sum, Cout;
end full_ add;
assign Sum = (A ^ B) ^ Cin;
architecture adder of full add is
assign Cout = (A & B) | (Cin & A) | (Cin & B);
begin
Sum < = A xor B xor Cin;
endmodule

Cout < = (A and B) or (Cin and A) or (Cin and B);

end adder;

SUM = A^B^C
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CARRY = AC + BC + AB

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 STRUCTURAL DESCRIPTION

• Structural description models the system as components or gates.

• This description is identified by the presence of the keyword component in the

architecture (VHDL) or gates construct such as and, or, and not in the module (Verilog).

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 EXAMPLE OF STRUCTURAL DESCRIPTION
VHDL DESCRIPTION

entity full_adder is begin

port(a , b ,c: in bit; Sum , Carry: out bit); signal s0,s1,s2,s3,s4;
end full_adder; X1: xor2 portmap(A , B, s0);
architecture struct_exple of full_adder is X2: xor2 portmap( s0, c, sum);
component xor2 A1: and2 portmap( a,b,s1);
port(I1, I2: in bit; O1 : out bit); A2: and2 portmap( b,c,s2);
end component; A3: and2 portmap( a,c,s3);
component and2 O1: or2 portmap( s1,s2,s4);
port(I1, I2: in bit; O1 : out bit); O2: or2 portmap( s4,s3,carry);
end component; end struct_exple;
Component or2
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Port(I1, I2:in bit; O1: out bit); SUM = A^B^C
end component CARRY = AC + BC + AB
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 EXAMPLE OF STRUCTURAL DESCRIPTION
VERILOG DESCRIPTION
module full_adder1(a,b,cin,S,C);
input a, b,cin;
output Sum,Carry;
wire s0,s1,s2,s3,s4;
Assign s0= (A ^ B),
Sum=( s0 ^ c),
S1= ( a & b),
S2= (b & c),
S3= ( a & c),
S4= (s1 | s2),
Carry= ( s4 | s3);
end module; SUM = A^B^C
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CARRY = AC + BC + AB

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 Full subtractor - EXAMPLE OF DATAFLOW
DESCRIPTION
VHDL DESCRIPTION VERILOG DESCRIPTION

entity full_sub is module full_ sub (A, B, Cin, diff, borr);

port (A, B, Cin : in bit; input A, B, Cin;
diff, borr : out bit);
output diff,, borr;
end full_ sub;
assign diff = (A ^ B) ^ Cin;
architecture subtractor of full sub is
assign borr = (~A & B) | (~A & C) | ( B & C);
begin
Diff < = A xor B xor Cin;
endmodule

Borr < =(not A and B) or ( not A and C) or ( B and

C);
end subtractor;
114
SUM = AB’C’ + A’B’C + ABC + A’BC’ BORROW = A’C + A’B + BC

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 EXAMPLE OF STRUCTURAL DESCRIPTION
VHDL DESCRIPTION SUM = AB’C’ + A’B’C + ABC + A’BC’
BORROW = A’C + A’B + BC

entity full_sub is Component not1

port(a , b ,c: in bit; diff , borrow: out bit); port( x:in bit; y:out bit);
end full_sub; end component;
architecture struct_exple of full_sub is begin
component xor2 signal s0,s1,s2,s3,s4,s5 :bit;
port(I1, I2: in bit; O1 : out bit); Assign
end component; X1: xor2 portmap(A , B, s0);
component and2 X2: xor2 portmap( s0, c, diff);
port(I1, I2: in bit; O1 : out bit); N1: not1 portmap( a,s1);
end component; A1: and2 portmap( s1,b,s2);
115
Component or2 A2: and2 portmap( s1,c,s3);
Port(I1, I2: in bit; O1: out bit); A3: and2 portmap( b,c,s5);
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end component O1: or2 portmap( ss2,s3,s4);
EXAMPLE OF STRUCTURAL DESCRIPTION
VERILOG DESCRIPTION
module full_subtractor1(a,b,cin,Sum,Diff); SUM = AB’C’ + A’B’C + ABC + A’BC’
input a, b,cin; BORROW = A’C + A’B + BC
output Sum,Diff;
wire s0,s1,s2,s3,s4;
Assign
s0=(A ^ B),
Sum=(s0 ^ c),
s1= ~a
s2=( c & s1),
s3=( s1 & b),
s4=( b & c),
s5=( s2 | s3),
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borrow=( s4 | s5);
end module;
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 Carry look ahead adder – VHDL code
• entity carrylookadder is
• Port ( a : in std_logic_vector(3 downto 0);
• b : in std_logic_vector(3 downto 0);
• cin : in std_logic;
• s : out std_logic_vector(3 downto 0);
• cout : out std_logic);
• end carrylookadder;
• architecture Behavioral of carrylookadder is
• signal c:std_logic_vector(4 downto 0);
• signal p,g: std_logic_vector(3 downto 0);

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• begin
• G1: for i in 3 downto 0 generate
• p(i) <= a(i) xor b(i);
• g(i) <= a(i) and b(i);
• s(i) <= p(i) xor c(i);
• end generate;
• -------Carry look ahead array
• c(0) <= cin;
• c(1) <= (cin and p(0)) or g(0);
• c(2) <= (cin and p(0) and p(1)) or (g(0) and p(1)) or g(1);

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• c(3) <= (cin and p(0) and p(1) and p(2)) or (g(0) and p(1) and p(2)) or (g(1) and p(2)) or
g(2);
• c(4) <= (cin and p(0) and p(1) and p(2) and p(3)) or
• (g(0) and p(1) and p(2) and p(3)) or
• (g(1) and p(2) and p(3)) or
• (g(2) and p(3)) or
• g(3);
•

• end Behavioral;

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 BINARY COMPARATOR

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 COMPARATORS
Digital Comparator is a combinational circuit that compares two digital or binary numbers in
order to find out whether one binary number is equal, less than or greater than the other binary
number. We logically design a circuit for which we will have two inputs one for A and other for B
and have three output terminals, one for A > B condition, one for A = B condition and one for A < B
condition.

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 COMPARATORS

COMPARATORS

Identity Magnitude

• Identity Comparators: Comparators that have only one output terminal and produces the output either low
or high are identity comparators.

• Magnitude Comparators: Comparators with three output terminals and checks for three conditions i.e
greater than or less than or equal to is magnitude comparator.
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 COMPARATORS
These comparators can compare 2-bit, 4-bit and 8-bit numbers depending on the application requirement.
These are available in TTL as well as CMOS logic family ICs and some of these ICs include IC 7485 (4-
bit comparator), IC 4585 (4-bit comparator in CMOS family) and IC 74AS885 (8-bitcomparator).

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 BASIC OPERATION TERMS OF COMPARATOR
Consider two binary numbers “A” and “B” as inputs to the digital comparator

LESS THAN:

• If binary number “A” is less than “B” than “less than” output will produce HIGH state “1” also known as true.

• If binary number “A” is greater than or equal to “B” than “less than” output will produce LOW state “0” also
known as false.

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 BASIC OPERATION TERMS OF COMPARATOR
EQUAL TO:

• If and only if number A is equal to number B than “equal to” output will produce logic HIGH state “1”. Otherwise,
the output will be LOW state “0”.

GREATER THAN:

• If number A is greater than B than “greater than” output will produce HIGH state”1”.

• If A is less than or equal to B than “greater than” output will produce LOW state “0”.

• You may also read: Digital Flip-Flops – SR, D, JK and T Flip Flops

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 SINGLE BIT COMPARATOR
This is the basic unit of a multi bit comparator which compares a single binary bit and produces output
according to those bits.

A B A<B A=B A>B

0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

A = B= ∑ ( 0, 3 )

A<B = ∑ ( 1)
126

A>B = ∑ (2)
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 SINGLE BIT COMPARATOR K MAP
A = B= ∑ ( 0, 3 )

A<B = ∑ ( 1)

A>B = ∑ (2)

LSB LSB LSB

B’ B B’ B B’ B
MSB b MSB b MSB b 0 1
a 0 1 a 0 1 a
a’b’ a’b a’b’ a’b a’b’ a’b
0 0 0
A’ 1 O A’ 0 1 A’ 0 0
ab’ ab ab’ ab ab’ ab
A 1 0 1 A 1 0 0 A 1 1 0

(A=B) = A’B’ + AB (A<B) = A’B (A>B) = AB’

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 SINGLE BIT COMPARATOR LOGIC DIAGRAM
(A=B) = A’B’ + AB

(A<B) = A’B

(A>B) = AB’

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 SINGLE BIT COMPARATOR LOGIC DIAGRAM

(A=B) = A’B’ + AB

(A<B) = A’B

(A>B) = AB’

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 2 BIT COMPARATOR
A 2-bit comparator compares two binary numbers, each of two bits and produces their relation such as one number
is equal or greater than or less than the other.

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 INPUTS OUTPUTS
A1 A0 B1 B0 A=B A>B A<B

0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
A = B= ∑ ( 0, 5,10,15)
0 1 0 1 1 0 0
A<B = ∑ ( 4,8,9,12,13,14)
0 1 1 0 0 0 1
0 1 1 1 0 0 1 A>B = ∑ (1,2,3,6,7,11)
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 1 0 0
1 0 1 1 0 0 1
1 1 0 0 0 1 0
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1 1 0 1 0 1 0
1 1 1 0 0 1 0
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 2 BIT COMPARATOR K MAP
A = B= ∑ ( 0, 5,10,15)

A<B = ∑ ( 4,8,9,12,13,14)

B1B0 B1B0
A1A0 00 01 11 10 A1A0 00 01 11 10
00 1 00 3
0 1 3 2 0 1 2

01 1 01 1
4 5 7 6 4 5 7 6

11 1 11 1 1 1
12 13 15 14 12 13 15 14

10 1 10 1 8 1 10
8 9 11 10 9 11

132
(A=B ) = A1’A0’B1’B0’ + A1’AOB1’B0 + A1A0B1B0 + A1A0’B1B0’ A<B= A1B1’ + A0B1’B0’ + A1A0B0’

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 2 BIT COMPARATOR K MAP
A>B = ∑ (1,2,3,6,7,11)

B1B0
A1A0 00 01 11 10
00 1 1 1
0 1 3 2

01 1 1
4 5 7 6

11
12 13 15 14

10 1
8 9 11 10

(A>B ) =A1’A0’B0 + A0’B1B0 + A1’B1

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 2 BIT COMPARATOR LOGIC DIAGRAM
(A=B ) = A1’A0’B1’B0’ + A1’AOB1’B0

+ A1A0B1B0 + A1A0’B1B0’

A<B= A1B1’ + A0B1’B0’ + A1A0B0’

(A>B ) =A1’A0’B0 + A0’B1B0 + A1’B1

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 4 BIT COMPARATOR USING IC 7485
A "comparator" used to compare two binary numbers each of four bits is called a "4-bit magnitude comparator" .
It consists of eight inputs each for two four "bit" numbers and three outputs to generate less than, equal to and
greater than between two binary numbers.

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4 BIT COMPARATOR

INPUTS OUTPUTS
A3B3 A2B2 A1B1 A0B0 A=B A>B A<B

A3>B3 x x x 0 1 0
A3<B3 x x x 0 0 1
A3=B3 A2>B2 x x 0 1 0
A3=B3 A2<B2 x x 0 0 1
A3=B3 A2=B2 A1>B1 x 0 1 0
A3=B3 A2=B2 A1<B1 x 0 0 1
A3=B3 A2=B2 A1=B1 A0>B0 0 1 0
A3=B3 A2=B2 A1=B1 A0<B0 0 0 1
A3=B3 A2=B2 A1=B1 A0=B0 1 0 0
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• In a 4-bit comparator the condition of A>B can be possible in the following four cases:
• If A3 = 1 and B3 = 0
• If A3 = B3 and A2 = 1 and B2 = 0
• If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
• Similarly the condition for A<B can be possible in the following four cases:
• If A3 = 0 and B3 = 1
• If A3 = B3 and A2 = 0 and B2 = 1
• If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

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 BASIC ITERATIVE CIRCUIT MODEL

• The technique of designing a single cell each with a set of inputs and outputs and then cascading
the cells to form larger circuits is called iterative design.

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 BASIC ITERATIVE CIRCUIT MODEL
• Two classes of input and output exist : primary inputs (outputs) enter (exit) the cell from (to) external
data sources (destination) and secondary inputs (outputs) enter (exit)the cell from (to) neighbouring
cells.

• The secondary inputs/outputs communicate information between the cells.

• Eg: Full Adder

1. Primary i/p are data from an external source and primary outputs is the sum.

2. The secondary i/p is the carry-in and the secondary o/p is the carry-out

3. Primary inputs to a comparator cell Cj are provided from external o/p is the carry-out

4. Comparator secondary o/p Soj conveys to cell Cj+1 the results of the comparison up to that cell
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 BASIC ITERATIVE CIRCUIT MODEL
• All of the comparator are identical. The least significant cell has its secondary inputs grounded. A is equal
to B. Each cell compares the external data it receives, checks the result from the previous cell and then
transmits the result to the next cell.

• Code is designed with two secondary i/o siganls from each cell. Let So2 be defined as secondary output 2,
S11 be defined as secondary input 1.

• The secondary inputs and outputs are connected between cells :

I/O FUNCTION

Si/o2 Si/o1

0 0 Aj = Bj

0 1 Aj > Bj 142

1 1 Aj = Bj
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 FOUR BIT ITERATIVE COMPARATOR MODEL
DATA INPUTS

B3 A3 B2 A2 B1 A1 B0 A0

A=B
SO13 SI13 SO12 SI12 SO11 SI11 SO10 SI10
A>B Decode
logic 3 2 1 0
S023 SI23 S022 SI22 S021 SI21 S020 SI20
A<B

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 4 BIT COMPARATOR USING IC 7485
A "comparator" used to compare two binary numbers each of four bits is called a "4-bit magnitude comparator" .
It consists of eight inputs each for two four "bit" numbers and three outputs to generate less than, equal to and
greater than between two binary numbers.

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 5 BIT COMPARATOR USING IC 7485
A "comparator" used to compare two binary numbers each of four bits is called a “5-bit magnitude comparator" .
It consists of eight inputs each for two four "bit" numbers and three outputs to generate less than, equal to and
greater than between two binary numbers and a cascaded 1 bit comparator.

B4 B3 B2 B1 A4 A3 A2 A1 B0 A0

B4 B3 B2 B1 A4 A3 A2 A1

1 BIT

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 8 BIT COMPARATOR USING IC 7485
An 8-bit comparator compares the two 8-bit numbers by cascading of two 4-bit comparators. The circuit
connection of this comparator is shown below in which the lower order comparator A<B, A=B and A>B outputs
are connected to the respective cascade inputs of the higher order comparator.

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 DATAFLOW DESCRIPTION OF A 4-BIT
COMPARATOR.
module magcomp (A,B,ALTB,AGTB,AEQB);

input [3:0] A,B;

output ALTB,AGTB,AEQB;

assign ALTB = (A < B),

AGTB = (A > B),

AEQB = (A == B);

endmodule

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• VHDL Code for 4-bit Binary Comparator – Behavioural Model

• Library ieee;
• use ieee.std_logic_1164.all;
• use ieee.std_logic_arith.all;
• use ieee.std_logic_unsigned.all;
•
• entity VHDL_Binary_Comparator is
• port (
• inp-A,inp-B : in std_logic_vector(3 downto 0);
• greater, equal, smaller : out std_logic
• );
• end VHDL_Binary_Comparator ;
•

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• architecture bhv of VHDL_Binary_Comparator is
• begin
• greater <= '1' when (inp-A > inp-B)
• else '0';
• equal <= '1' when (inp-A = inp-B)
• else '0';
• smaller <= '1' when (inp-A < inp-B)
• else '0';
• end bhv;

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VHDL Structural MODEL

• library ieee;
• use ieee.std_logic_1164.all;
• entity mag_comp_4b is
• port ( a, b : in std_logic_vector(3 downto 0);
• ag, bg, eq : out std_logic);
• end mag_comp_4b;

• architecture structural of mag_comp_4b is

• signal s : std_logic_vector(3 downto 0);
• begin
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• s(0)<= a(0) xnor b(0);
• s(1)<= a(1) xnor b(1);
• s(2)<= a(2) xnor b(2);
• s(3)<= a(3) xnor b(3);
• eq<=s(3) and s(2) and s(1) and s(0);
• ag<=(a(3) and (not b(3))) or (s(3) and a(2) and (not b(2))) or (s(3) and s(2) and a(1)and
(not b(1))) or (s(3) and s(2) and s(1) and a(0) and (not b(0)));
• bg<=(b(3) and (not a(3))) or (s(3) and b(2) and (not a(2)))or (s(3) and s(2) and b(1)and
(not a(1))) or (s(3) and s(2) and s(1) and b(0) and (not a(0)));
• end structural;

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 152

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 MULTIPLEXERS

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 MULTIPLEXER
• Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and
single output line. One of these data inputs will be connected to the output based on the values of
selection lines.

• Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So,
each combination will select only one data input. Multiplexer is also called as Mux.

• It is also called a data selector

• It is used in several digital signal processing applications, design of calculators, mobiles, processors,
and digital image processors.

• It reduces number of wires, circuit complexity, reduces cost

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 BLOCK DIAGRAM OF MULTIPLEXER
• This is the block diagram of a multiplexer with n input signals and m select lines. m select lines
can have 2^m possible combinations.

• Therefore, In a multiplexer,

n = 2^m

• Multiplexers are always of the configuration 2^m:1,

 m is the number of select signal

 Represents the single output.

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FUNCTIONAL DIAGRAM OF MULTIPLEXER

SELECT input code determines which input is transmitted to data out 156

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 MULTIPLEXER CONFIGURATION
• 2:1, 4:1 , 8:1, 16:1 , 32:1, 64:1…… are the possible MUX configuration

CONFIG NO OF I/P SELECT

LINE
2:1 MUX 2 1
4:1 MUX 4 2
8:1 MUX 8 3
16:1 MUX 16 4
32:1 MUX 32 5
64:1 MUX 64 6

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 2:1 MULTIPLEXER

• A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one output Y. Depends
on the select signal, the output is connected to either of the inputs. Since there are two input signals
only two ways are possible to connect the inputs to the outputs, so one select is needed to do these
operations.

• If the select line is low, then the output will be switched to D0 input, whereas if select line is high,
then the output will be switched to D1 input. The figure below shows the block diagram of a 2-to-1
multiplexer which connects two 1-bit inputs to a common destination.

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 2:1 MULTIPLEXER BLOCK DIAGRAM

• 2 DATA INPUT D1 & D0

• 1 SELECT LINE (S)
• 1 DATA OUTPUT (Y) 159

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 OPERATION OF 2:1 MULTIPLEXER
• If select line S0 =0 then output =D0 and if select line S0=1 then output is D1

DATA INPUTS DATA INPUTS

D0 D1 D0
D1

SELECT SIGNAL SELECT SIGNAL

S0 = 0 S0 = 1

Z Z 160
OUTPUT OUTPUT

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2:1 MULTIPLEXER

D0

Z
No of Input [m]= 2
2:1 MUX OUTPUT
no of output [z]= 1
D1
Select line[n] = 2^m = 2^1= 2

SELECT SIGNAL
S0 = 0

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 2:1 MULTIPLEXER TRUTH TABLE

S0 OUTPUT Z
0 D0
1 D1

EXPRESSION:
D0S0’ + D1S1

Case 1:D0 =1,D1=0, S= 0 ,output:1

which is Do

Case 2: D0 =1,D1=0, S= 1 ,output:0

which is D1 162

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 4:1 MULTIPLEXER
• A 4-to-1 multiplexer consists four data input lines as D0 to D3, two select lines as S0 and S1 and a
single output line Y. The select lines S1 and S2 select one of the four input lines to connect the
output line. The particular input combination on select lines selects one of input (D0 through D3) to
the output.

• The figure below shows the block diagram of a 4-to-1 multiplexer in which the multiplexer decodes
the input through select line.

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 4:1 MULTIPLEXER BLOCK DIAGRAM
S0 S1

D0
D0
D1
D1 Z Z
D2
4:1 MUX OUTPUT D2
D3
D3

• 4 DATA INPUT D0, D1, D2,D3

S0 S1
• 2 SELECT LINE S0,S1
• 1 DATA OUTPUT (Z) 164

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 OPERATION OF 4:1 MULTIPLEXER
• If select line S0 =0 then output =D0 and if select line S0=1 then output is D1 and so on.

DATA INPUT DATA INPUT DATA INPUT DATA INPUT

D3 D1 D0 D2 D3 D1 D0 D2 D3 D1 D0 D2 D3 D1 D0 D2

S0=0 S0=0 S0=1 S0=1

S1=0 S1=1 S1=0 S1=1

Z Z Z Z
OUTPUT OUTPUT OUTPUT OUTPUT 165

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 4:1 MULTIPLEXER TRUTH TABLE

S0 S1 OUTPUT Z
0 0 D0
0 1 D1
1 0 D2
1 1 D3

EXPRESSION:
D0S0’S1’ + D1S0’S1 + D2S0S1’ + D3S0S1

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 8:1 MULTIPLEXER
• An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input select lines S2 through
S0 and a single output line Y. Depending on the select lines combinations, multiplexer decodes the
inputs.

• The below figure shows the block diagram of an 8-to-1 multiplexer with enable input that enable or
disable the multiplexer. Since the number data bits given to the MUX are eight then 3 bits (23=8) are
needed to select one of the eight data bits.

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 8:1 MULTIPLEXER BLOCK DIAGRAM
S0 S1 S2

D0

D0 D1
D1
D2
D2
Z
D3 Z D3
8:1 MUX OUTPUT
D4 D4
D5
D5
D6
D6
D7
D7
• 8 DATA INPUT D0, D1, D2,D3,D4,D5,D6,D7
• 3 SELECT LINE S0,S1,S2 169
S0 S1 S2
• 1 DATA OUTPUT (Z)
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 8:1 MULTIPLEXER TRUTH TABLE

S2 S1 S0 OUTPUT Z
0 0 0 D0
0 0 1 D1 EXPRESSION:
0 1 0 D2 D0S0’S1’S2’+D1S0S1’S2’+D2S0’S1S2’+D
0 1 1 D3
3S0S1S2’+D4S0’S1’S2+D5S0S1’S2+D6S
1 0 0 D4
1 0 1 D5
0’S1S2+D7S0S1S2
1 1 0 D6
1 1 1 D7

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 8:1 MULTIPLEXER TRUTH TABLE
EXPRESSION:
D0S0’S1’S2’+D1S0S1’S2’+D2S0’S1S2’+D3S0S1S2’+D4S0’S1’S2+D5S0S1’S2+D6S0’S1S2+D7S0S1
S2

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 MULTIPLEXERS IN IC PACKAGES

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 MULTIPLEXERS IN IC PACKAGES
• The 7400 series has several ICs that contain multiplexers

IC No. Function Output State

74157 Quad 2:1 mux. Output same as input given
74158 Quad 2:1 mux. Output is inverted input
74153 Dual 4:1 mux. Output same as input
74352 Dual 4:1 mux. Output is inverted input
74151 8:1 mux. Output is inverted input
74150 16:1 mux. Output is inverted input

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74153IC:DUAL 4:1 MUX

S0
S1
ENABLE
74153 F1
A0
A1
A2
A3

ENABLE

B0 74153 F0
B1
B2
B3 174

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74157 TTL QUAD 2:1 MULTIPLEXER IC & PIN
CONFIGURATIONS

00

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74153 TTL Dual 4:1 MULTIPLEXER IC & PIN
CONFIGURATIONS

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8:1 MULTIPLEXER IC & PIN CONFIGURATIONS

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 CONFIGURE 16:1 MUX USING 4:1 MUX
x0
x1 d0
x2
4:1 MUX
x3
EN
S1 S2

x4
x5 d1
x6
4:1 MUX d0
x7 d1 f
EN
S1 S2 d2 4:1 MUX O/P
d3
EN S1 1 S2
x8
x9 d2
x10
4:1 MUX
x11 S1 S2
EN

x12
x13 d3
x14
4:1 MUX 178

x15
EN
S1 S2
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CONFIGURE 16:1 MUX USING 74153
S0
S1
EN
A0 74153 F1
A1
A2
A3
EN
B0
B1
B2
B3 F0
S0
S1
EN
A0 74153 F1
A1
A2
A3
EN
B0
B1 179
B2
B3 F0
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DESIGN 8:1 MUX USING 4:1 MUX

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DESIGN 4:1 MUX USING 2:1 MUX

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 DATAFLOW DESCRIPTION OF 2-TO-1-LINE MUX

module mux2x1_df (A,B,select,OUT);

input A,B,select;

output OUT;

assign OUT = select ? A : B;

endmodule

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 Gate Level Modelling
• module m21(Y, D0, D1, S);
• output Y;
• input D0, D1, S;
• wire T1, T2, Sbar;
• and (T1, D1, S),
• and(T2, D0, Sbar);
• not (Sbar, S);
• or (Y, T1, T2);
• endmodule

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 Behavioural
• module m21( D0, D1, S, Y);
• input wire D0, D1, S;
• output reg Y;
• always @(D0 or D1 or S) //Since the output of 2:1 MUX changes once there is a
• change in D0 OR D1 OR S we’ll use always statement.

• begin if(S) // if the S event is true, the output Y will be D1, else the output
• will be D0.
• Y= D1;
• else Y=D0;
• endmodule
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 Structural
• module and_gate(output a, input b, c);
• assign a = b & c;
• endmodule
• module not_gate(output d, input e);
• assign d = ~ e;
• endmodule
• module or_gate(output l, input m, n);
• assign l = m | n;
• endmodule
• module m21(Y, D0, D1, S);
• output Y;
• input D0, D1, S;
185
• wire T1, T2, T3; and_gate u1(T1, D1, S); not_gate u2(T2, S); and_gate u3(T3, D0, T2);
or_gate u4(Y, T1, T3); endmodule
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 186

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 VHDL code for 2:1 mux
• library IEEE;
• use IEEE.STD_LOGIC_1164.ALL;
• entity mux_2to1_top is
• Port ( SEL : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC_VECTOR (3 downto 0));
end mux_2to1_top;
architecture Behavioral of mux_2to1_top is
begin
X <= A when (SEL = '1') else B;
end Behavioral; 187

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 DATAFLOW DESCRIPTION OF 4-TO-1-LINE MUX
module mux4x1_bh (i0,i1,i2,i3,select,y);

input i0,i1,i2,i3;

input [1:0] select;

output y;

reg y;

always @(i0 or i1 or i2 or i3 or select)

case (select)

2'b00: y = i0;

2'b01: y = i1;

2'b10: y = i2;
188
2'b11: y = i3;

endcase
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 STRUCTURAL DESCRIPTION OF 4-TO-1-LINE MUX
//module mux_4_to_1_st_v(S,D,Y);

input [1:0]S;

input [3:0]D;

output Y;

wire [1:0]not_s;

wire [0:3]N;

not g0(not_s[0],S[0]),g1(not_s[1],S[1]);

and g2(N[0],not_s[0],not_s[1],D[0]), g3(N[1],S[0],not_s[1],D[0]), g4(N[2],not_s[0],S[1],D[0]),

g5(N[3],S[0],S[1],D[0]);

or g5(Y,N[0],N[1],N[2],N[3]);
189
endmodule

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SELF ASSESMENT QUESTIONS

1. Design a four bit multiplexer system using two 74153 IC

2. Design 32:1 mux using two 74150 IC
3. Design 32:1 mux using four 8:1 mux and 2 to 4 decoder
4. Realize 16:1 mux using 4:1 mux
5. Realize 64:1 mux using 16:1 mux and 4:1 mux

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 BOOLEAN FUNCTION GENERATOR USING MUX
F(A,B,C,D)= ∑ m ( 1,2,4,5,6,9,11,12,14). Realize using 4:1 mux with AB,CD,AC,AD

WITH AB AS SELECT LINE ( group along the select line)

CD
AB 00 01 11 10
dO C
00 1 1
0 1 3 2 C’D + CD’ D
d1
01 1 1 1 C’+ D’ C’
4 5 7 6
D’
11 d2
1
12 13 15
1 14
D’
D’
d3
10 1 1 D D
8 9 11 10

191

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 BOOLEAN FUNCTION GENERATOR USING MUX
F(A,B,C,D)= ∑ m ( 1,2,4,5,6,9,11,12,14). Realize using 4:1 mux with AB,CD,AC,AD

WITH CD AS SELECT LINE ( group along the select line)

CD
AB 00 01 11 10
00 0 1 3
1 A B
1 2

01 1 1 1 B
4 5 7 6
Y
11 1 1
12 13 15 14

10 8 1 1 10
9 11
dO d1 d2 d3
C D 192

B A’+B’ AB’ A’+B

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 SOLVE
F(A,B,C,D)= ∑ m ( 1,2,4,5,6,9,11,12,14). Realize using 4:1 mux with AB,CD,AC,AD

WITH AD AS SELECT LINE ( group along the select line)

CD
AB 00 01 11 10
00 1 3
1 B
0 1 2

01 1 1 1
4 5 7 6
Y
11 1 1
12 13 15 14

10 8 1 1 10
9 11

A D 193

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 BOOLEAN FUNCTION GENERATOR USING MUX
F(A,B,C,D)= ∑ m ( 1,2,4,5,6,9,11,12,14). Realize using 4:1 mux with AB,CD,AC,AD

WITH AC AS SELECT LINE ( group along the select line)

d0 d1
CD d0= D+B
AB 00 01 11 10 D
d1= D’ B
00 1 3
1
0 1 2
d2= B XOR D
01 1 1 1
4 5 7 6
d3= B XOR D
11 1 1
12 13 15 14

10 8 1 1 10
d2 9 11
d3
A C
194

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 SELF ASSESMENT QUESTIONS

1. Design f(x,y,z) = ∑m ( 0,2,6,7 ) using 8:1 mux , 4:1 mux and 2:1 mux.
2. Design f( A,B,C,D ) = ∑m (1,3,4,5,6,11,15) using 16:1 mux, 8:1 mux
and 4:1 mux.
3. Design f( a,b,c,d) = ∑m (1,2,4,6,7,11,13,15) with ABC, ACD, BCD,
ABD
4. If (a,b,c,d ) = πM ( 0,3,5,8,9,10,12,14) design 8:1 mux with BCD as
select lines and 4:1 mux with Ab as select line

195
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 RECALLING CONCEPTS

196

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MUX IMPLEMENTATION https://www.youtube.com/watch?v=r8S6INFAahg
ABC
D’ 0 2 4 6 8 10 12 14
D 1 3 5 7 9 11 13 15

ACD
B’ 0 1 2 3 8 9 10 11
B 4 5 6 7 12 13 14 15

BCD
A’ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15

ABD
C’ 0 1 4 5 8 9 12 13 197

C 2 3 6 7 10 11 14 15
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 DECODERS

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DECODERS

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 DECODERS

 A decoder is a combinational logic circuit that converts a N-bit binary code into M output
lines such that only one output line is activated for each one of the possible combinations
of inputs.

 In other words, we can say that a decoder identifies or recognizes or detects a particular
code.

 In its general form, a decoder has N input lines to handle N bits and form one to 2N output
lines to indicate the presence of one or more N-bit combinations. Since each of N inputs
can be a 0 or a 1, there are 2N possible input combinations or codes.

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 DECODERS
 For each of these input combinations, only one of the M outputs will be active (HIGH), all other
outputs will remain inactive (LOW). Some decoders are designed to produce active LOW output,
while all other outputs remain HIGH.

 Some decoders do not utilize all of the 2N possible input codes. For example, a BCD to decimal
decoder has a 4-bit input code and 10 output lines that correspond to the 10 BCD code groups
0000 through 1001. Decoders of this type are often designed so that if any of the unused codes
are applied to the input, none of the outputs will be activated.

 A binary decoder is usually implemented as either a stand-alone integrated circuit (IC) or as part
of a more complex IC. Widely used decoders are often available in the form of standardized
ICs.

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 2-TO-4 LINE DECODER

 2-to-4 line decoder has 2 inputs & 4 outputs.

 It uses all AND gates & the outputs are active-HIGH as AND gates give output only when both
inputs are HIGH.
 It is also referred to as 1-of-4 decoder, because only one of the four outputs is activated at one
time.

No. of inputs=N=2

No. of outputs=2N=4

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 TRUTH TABLE
 A & B are the two inputs whereas D0 through D3 are the four outputs.

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 EXPRESSIONS

 The Boolean expressions for the four outputs are:-

D0 = A’B’ , D1 = A’B , D2 = AB’ & D3 = AB.

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 3-TO-8 LINE DECODER
No. of inputs=N=3
 3-to-8 line decoder has 3 inputs & 8 outputs. No. of outputs=2N=8
 It uses all AND gates, and therefore the outputs are active-HIGH. For active-
LOW outputs, NAND

gates are used.

 It is also called a binary-to-octal decoder because it takes a 3-bit binary input
code and activates one of the eight (octal) outputs corresponding to that code.

 It is also referred to as 1-of-8 decoder because only

one of the eight outputs is activated at one time.

 The Boolean expressions for the eight outputs are:-

205
Y0 = X0’ X1’ X2’ , Y1 = X0’ X1’ X2 , Y2 = X0’ X1 X2’ , Y3 = X0’ X1 X2 , Y4 = X0 X1’ X2’ , Y5 = X0 X1’ X2 , Y6 = X0
X1 X2’ ,
& Y7 = X0 X1 X
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 3-TO-8 LINE DECODERS

The decoder is called n-to-m-line decoder, where m≤2n .

the decoder is also used in conjunction with other code converters such as a BCD-to-
seven_segment decoder.

3-to-8 line decoder: For each possible input combination, there are seven outputs that are
equal to 0 and only one that is equal to 1.

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IMPLEMENTATION

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 TRUTH TABLE

 Some decoders have one or more ENABLE inputs that are used to control the operation of the
decoder.For example, in a 3-to-8 line decoder, if a common enabled line is connected to the fourth input
of each gate , a particular output as determined by the X0, X1, X2 input code will go HIGH only when
ENABLE line is held HIGH. When the ENABLE is held LOW, however, all the outputs will be forced to
the LOW state regardless of the levels at the X0, X1 & X2 inputs. Thus, the decoder is enabled only208when
the ENABLE is HIGH.
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3 TO 8 DECODER IC 74x138

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 BCD-TO-DECIMAL DECODER/4-TO-10 LINE
DECODER

 BCD-to-decimal decoders consist of eight inverters and ten four-input NAND gates. The
inverters are connected in pairs to make BCD input data available for decoding by the NAND
gates. Full decoding of valid input logic ensures that all outputs remain off for all invalid input
conditions.

 The BCD-to-decimal decoder is also called a 4-to-10 line decoder or 1-of-10 decoder. It has

4 inputs & 10 outputs. Only one output line is active at a time.

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BCD-TO-DECIMAL DECODER/4-TO-10 LINE DECODER

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PIN DIAGRAM

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 TRUTH TABLE
 IC 7442 is a BCD-to-decimal decoder with active LOW inputs & outputs.

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 BCD-TO-SEVEN SEGMENT DECODER

BCD input Decimal output

LED
00 010 010 01

BCD-to-
7-Segment
Decoder/
Driver

 Electronic decoders are available in IC form.

 This decoder translates from BCD to decimal.
 Decimals are shown on an 7-segment LED display. 214

 This IC also drives the 7-segment LED display.

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 This type of decoder accepts the BCD code & provides outputs to energize seven segment display
devices in order to produce a decimal read out. Sometimes the hex characters A through F may be
produced.

 Each segment is made of a material that emits light when current is passed through it. The most
commonly used materials include LEDs, incandescent filaments & LCDs. The LEDs generally
provide greater illumination levels but require more power than that by LCDs.

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TRUTH TABLE

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 DECODER APPLICATIONS

 Decoders are used whenever an output or group of outputs is to be activated only on the occurrence
of a specific combination of input levels. These input levels are often provided by the outputs of a
counter or register.

 Decoders can be used as timing or sequencing signals to turn devices on or off at specific times,
because when the decoder inputs come from a counter that is being continually pulsed, the decoder
outputs will be activated sequentially.

 Decoders are widely used in memory systems of computers where they respond to the address code
from the central processor to activate the memory storage location specified by the address code.

217

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 DECODER APPLICATIONS

 Decoder is designed to be used in high-performance memory-decoding or data-routing applications

requiring very short propagation delay times.

 In high-performance memory systems, this decoder can be used to minimize the effects of system
decoding.

 When used with high-speed memories using a fast enable circuit, the delay times of these decoders
and the enable time of the memory usually are less than the typical access time of the memory. This
means that the effective system delay introduced by the decoder is negligible.

218

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 DEMULTIPLEXER
 • A decoder withan enable inputis referred toas a decoder/demultiplexer.

• The truthtable ofdemultiplexeris the same with decoder.



D0

Demultiplexer D1 D2
E
D3
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 3-TO-8 DECODER WITH ENABLE
IMPLEMENT THE 4-TO-16 DECODER

220

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 EXAMPLE

• Implement the following multiple output function using 74LS138 and external gates. F1 (A,B,C)=
Σm (1,4,5,7) & F2 (A,B,C)= ∏m(2,3,6,7)

• 74LS138 is an 3*8 decoder. The outputs of this ic have active Low. i.e in SOP form for F1 using
NAND gate and POS function for F2 using AND gate.

221

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 IMPLEMENTATION OF A FULL ADDER WITH
A DECODER
obtain the functions for the combinational circuit in sum of minterms:

S(x, y, z) =∑(1, 2, 4,7)

C(x, y, z) =∑(3, 5, 6,7)

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 ENCODERS

One of the main disadvantages of standard digital encoders is that they can generate the wrong output code
when there is more than one input present at logic level “1”. For example, if we make inputs D1 and D2 HIGH at
logic “1” both at the same time, the resulting output is neither at “01” or at “10” but will be at 223

“11” which is an output binary number that is different to the actual input present.
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 ENCODERS

 Priority encoders output the highest order input first for example, if input lines “D2“, “D3” and “D5” are
applied simultaneously the output code would be for input “D5” (“101”) as this has the
highest order out of the 3 inputs. Once input “D5” had been removed the next highest output code would
224
be for input “D3” (“011”), and so on.

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An encoder is the inverse operation of a decoder. We can derive the Boolean functions by table

z = D 1 + D3 + D5 + D 7
y = D2 + D 3 + D 6 + D 7
x = D4 + D5 + D6 + D7

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ENCODER IMPLEMENTTION

x=D4+D5+D6+D7

y=D2+D3+D6+D7

z=D1+D3+D5+D7

226

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 PRIORITY ENCODER

If two inputs are active simultaneously , the output produces an undefined

combination. We can establish an input priority to ensure that only one input is encoded.

Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated when all
the inputs are 0; the output is the same as when D0 is equal to 1.

The discrepancy tables on Table 4-7 and Table 4-8 can resolve aforesaid condition by providing one
more output to indicate that at least one input is equal to 1.

227

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 PRIORITY ENCODER
V=0=no valid inputs
V=1=valid inputs
X’s in output columns represent don’t-care conditions X’s in the input columns are useful for
representing a truth table in condensed form. Instead of listing all 16 minterms of four variables.

228

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 PRIORITY ENCODER

I3 has the highest priority

I0 has the lowest priority

X: don't-care conditions 229

V: valid output indicator

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 230

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 231

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PRIORITY ENCODER

x  D2  D3
y  D3  D1 D2  232

V  D0  D1  D2  D 3
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IC 74LS 348 8 TO 3 PRIORITY ENCODER

Y0 A
Y1
B
Y2
E0
Y3
74LS 348 c
Y4

Y5 G
Y6
Y7 S
E1

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VERILOG MODULE OF 2:4 DECODER

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VERILOG MODULE OF 3:8 DECODER

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VERILOG MODULE OF 3:8 DECODER

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VERILOG MODULE OF 3:8 ENCODER

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NPTEL VIDEO ON MULTIPLEXER BASED DESIGN
https://www.youtube.com/watch?v=QrZgp0SAUFQ

238

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 EXAMPLES

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 NPTEL AND ANIMATED VIDEOS ON K MAP
Karnaugh Map Minimization Using Maxterms
https://www.youtube.com/watch?v=i_HYxdri69Y

Logic Minimization Using Karnaugh Maps

https://www.youtube.com/watch?v=ygm25sqqepg

https://nptel.ac.in/courses/117/106/117106086/
https://youtu.be/iJ9cFDoXajw
https://youtu.be/6HTN3IDi2Fw
K MAP WITH DON’T CARE 240

https://youtu.be/VY9J3qYbky4
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CONTENT MISMATCH IN CURRICULUM

Variable Entrant Map (VEM) in Digital Logic

https://www.youtube.com/watch?v=nnSk1amiBCk

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 VARIABLE ENTRANT MAP (VEM) IN DIGITAL LOGIC
• Entered variable maps simplify the process further by visually minimizing a K-map. The compression
of the map makes a multi-variable system much easier to visualize and minimize.

• Truth tables provide the best mechanism for completely specifying the behaviour of a given
combinational logic circuit, and K-maps provide the best mechanism for visualizing and minimizing
the input-output relationships of digital logic circuits.

• Input variables across the top left of a truth table and around the periphery of K-maps. This allows
every state of an output signal to be defined as a function of the input patterns of 0's and 1's on a
given row in a truth table, or as the binary coding for a given K-map cell.

242

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 VARIABLE ENTRANT MAP (VEM) IN DIGITAL LOGIC
• Without any loss of information, truth tables and K-maps can be translated into a more compact form by moving input
variables from the top-left of a truth table to the output column, or from outside the K-map to inside the cells of a K-map.

• Although it will not be clear until later modules, the use of entered variables and compressed truth tables and K-maps
often makes a multi-variable system much easier to visualize and minimize.

• The translation mechanics are illustrated in the figures below, where a 16-row truth table is compressed into both 8-row
and 4-row truth tables. In the 8-row truth table, the variable D is no longer used to identify an input column. Instead, it
appears in the output column, where it encodes the relationship between two rows of output logic values and the D
input.

• In the 4-row truth table, variables C and D are no longer used to identify an input column, but rather in the output
column where they encode the relationship between four rows of the output logic values and the C and D inputs.
•
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VARIABLE ENTRANT MAP (VEM) IN DIGITAL LOGIC

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 VARIABLE ENTRANT MAP (VEM) IN DIGITAL LOGIC
• The 4-cell K-map is reproduced to the right, this time showing the implied sub-maps that illustrate the
relationship between C and D for each of the four unique values of the A and B variables.

• For any entered variable K-map, thinking of (or actually sketching) the sub-maps can help identify the
correct encoding for the entered variables.

• Truth table row numbers can be mapped to cells in the sub-maps by reading the K-map index codes,
starting with the super-map code, and appending the sub-map code. For example, the shaded box in
the sub-map is in box number 1110.

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 VARIABLE ENTRANT MAP (VEM) IN DIGITAL LOGIC
• This same map compression is illustrated below, showing the mapping from non-compressed K-
maps directly to compressed K-maps. The colors show how cells in the uncompressed map are
translated to the cells in the compressed map.

• Two cells in the 16-cell map are compressed into a single cell in the 8-cell map, and that four cells in
the 16-cell map are compressed into a single cell in the 4-cell map.

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 QUIZ

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• A decoder converts n inputs to __________ outputs.
a) n
b) n2
c) 2n
d) nn
• Which of the following are building blocks of encoders?
a) NOT gate
b) OR gate
c) AND gate
d) NAND gate
• Which of the following is a decoder IC?
a) 7890
b) 8870
c) 4047
d) 4041

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• Invalid BCD can be made to valid BCD by adding with _______________
a) 0101
b) 0110
c) 0111
d) 1001
• Which of the following represents a number of output lines for a decoder with 4 input
lines?
a) 15
b) 16
c) 17
d) 18

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 VTU QUESTION QUESTIONS

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 Construct an 16:1 MUX using 4:1 and 2:1 multiplexers and hence analyze using truth table
 Using active high output 3:8 line decoder, implement the following functions
f1(A,B,C,D)=Σm(0,1,2,5,7,11,15) f2(A,B,C,D)=Πm(1,3,4,11,13,14)
 Design a carry look ahead 4-bit parallel adder. Show that the time for addition is independent of
the length of operands.
 Write the compressed truth table for a 4 to 2 line priority encoder with a valid output and simplify
the same using K-Map. Design the logic circuit for the same.
 Implement the following multiple output function using one 74138 & external gates. F1(a,b,c) =
Σm(1,4,5,7) & F2(a,b,c) = Π M(2,3,6,7).
 Write the compressed truth table for a 4 to 2 line priority encoder with a valid output where the
highest priority is given to highest bit position and simplify the same using K-map. Design 251
the
logic circuit as well.
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 Implement 4-bit parallel adder/subtractor using 4-full adders blocks. Explain its operation, if Cin =
0 the circuit should act as adder and if Cin = 1 the circuit act as subtractor.
 Implement the function using 8:1 MUX, F(a,b,c,d) = Σm(0,1,3,4,7,10,11,14,15)
 Implement the following Boolean function using a 4:1 Mux with A and B as select lines.
Y=f(A,B,C,D)= ∑m(0,1,2,4,6,9,12,14)
 Design and implement a 4 bit Carry look ahead adder 10M b.Design a 4 to 16 decoder by
cascading 2 to 4 decoders.
 Design an 8:1 Mux Tree using only 2:1 Multiplexers.

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 FDP CONTENT
https://nptel.ac.in/courses/117/106/117106086/
Hardware modeling using verilog
By Prof. Indranil Sengupta | IIT Kharagpur
The course will introduce the participants to the Verilog hardware description language. It
will help them to learn various digital circuit modeling issues using Verilog, writing test
benches, and some case studies.

DRIVE CONTENTS:

https://swayam.gov.in/nd1_noc20_cs63/preview
Digital Systems: From Logic Gates to Processors
https://coursera.org/share/fb5c24026440534142a32fd4068b77df 253

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 ANIMATED VIDEO LINKS
https://www.youtube.com/watch?v=smeUN1Bxj3M

https://www.youtube.com/watch?v=YqGRAD6MUsI

https://www.youtube.com/watch?v=thkTzdnkL5U

https://www.youtube.com/watch?v=pzJnVA5v_34

https://www.youtube.com/watch?v=PBfdiLf1myM

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 VIDEO LINKS
https://www.youtube.com/watch?v=CeD2L6KbtVM

https://www.digimat.in/nptel/courses/video/117105080/L01.html

http://www.nptelvideos.in/2012/12/digital-systems-design.html

https://www.youtube.com/watch?v=RZQTTfU9TNA,

https://www.youtube.com/watch?v=36hCizOk4PA,

https://www.youtube.com/watch?v=397DDnkBm8A

Video link / Additional online information:

https://www.youtube.com/watch?v=nnSk1amiBCk

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 CASE STUDY
https://www.youtube.com/watch?time_continue=472&v=yAzoeFZAOQ&feature=emb_logo

https://www.youtube.com/watch?v=smeUN1Bxj3M&t=19s

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CASE STUDY : BCD TO 7 SEGMENT DISPLAY
ENCODER
Inputs Outputs
Digit A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
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9 1 0 0 1 1 1 1 1 0 1 1

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DISPLAY DECODER

IC 7447

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 Thank You

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