Dual Address RAM Implementation for

Optimized Memory Management

Project 10 - Group 1
Date - 01/03/2025
 List of Contents
1. Introduction 6. Implementation
2. Architecture 7. Advantages
3. Signals 8. Applications
4. Dimension 9. Conclusion
5. Behaviour 10. Future Enhancements
 Introduction
RAM allows the computer to perform many of its everyday tasks, such as loading
applications, browsing the internet, editing a spreadsheet, or experiencing the
latest game.
Random-access memory (RAM) is a form of computer memory that can be
written and read and changed in any order, typically used to store data.
RAM is capable to perform two operations like as Read and Write. Read means
signal transferring out, and Write means signal transferring in.
Traditional RAM systems can only read from or write to memory at one address
during each clock cycle. This can cause delays if multiple data locations need to be
accessed frequently.
In our project we are implementing Dual Address RAM where it has the capability
to access different addresses in parallel manner. Here it can handle these
operations more efficiently compared to Single port ram
It has dual ports for performing simultaneous write and read operations from
distinct addresses.
In DAR, two separate memory addresses can be read from and written to at the
same time. For example, while the processor is reading data from one address
using Address Line A, it can simultaneously write data to another address using
Address Line B.
When writing simultaneously to the same location by both ports, data integrity is
not guaranteed. Separate clock signals must be maintained for port A and port B
to avoid data corruption.
Architecture
Our aim is to enhance system performance and memory efficiency by performing
parallel write, read operations through distinct addresses from dual ports with
reference to their respective clock signals
Key Components in the DAR architecture are as follows
Memory Cells:
The Memory Array is the central storage unit in the RAM, consisting of an
array of memory cells arranged in rows and columns. Each memory cell
stores a bit of data, and groups of cells make up a word of data. The
memory array is where the data is actually stored and retrieved during read
and write operations.
The memory cells are organized into a grid, with the rows representing
addresses, and the columns representing the data bits within each word.
The memory array supports simultaneous access by having independent
read and write ports.
Clock Cycle :
DAR operates on the system clock. It has 2 clock signals at dual ports for
the independent operations occurring within the clock cycle. This dual clock
mechanism can reduce bottlenecks that occur in traditional memory systems.
Dual Access Ports :
It has 2 ports port A and port B. Each port has its own independent set of
address, data, and control lines. This allows two separate devices or systems
to access the memory in parallel from both the ports.
Control Logic :
The control circuitry manages the overall operation of the dual-port RAM
It has 2 control lines at both the ports to control the write and read
operations to be performed
Read control signal controls the data access from the memory
Write control signal controls the data stored into the memory
Address Buses :
DAR has 2 address buses at both the ports.
Address Bus A : This is the address bus used at port A. It carries the memory
address to perform the operations at port A.
Address Bus B : This address bus is used at port B. It carries the memory
address to perform write, read operations at port B.
Data Buses :
DAR has 2 data buses at port A and port B.
Data Bus A : This data bus is used to carry data into the memory at port A
Data Bus B : This data bus is used at port B. It is used to carry data written
into the memory.
This bus is used for the write operations.
Output Bus :
DAR has 2 output signals at dual ports. It transfers the data in the memory,
from the selected address locations to the output signal at both the ports.
 Signals
clka, clkb – Clock signals providing reference timing for synchronized read and
write operations in dual-port memory architecture.
clr – Active-low/high input signal that resets memory contents and forces all
output signals to zero for initialization.
wen_a, wen_b – Write enable signals allowing data storage at respective ports
when asserted during write cycles.
ad_a, ad_b – 11-bit address inputs specifying memory locations for storing or
retrieving data during read and write operations.
din_a, din_b – 8-bit input data signals that are written into specified memory
locations when write enable is active.
ren_a, ren_b – Read enable signals that allow access to stored data from memory
locations when asserted.
q_a, q_b – 8-bit output ports delivering stored data from memory when read
operations are performed successfully.
 Dimensions
Memory Depth: 512 locations, capable of storing 512 individual data entries.
Memory Width: Each location stores 8 bits (1 byte) of data.
Total Storage Capacity:
1. 512 × 1 byte = 512 bytes of total memory.
2. Can hold 512 separate 8-bit values.
Addressing:
1. Requires 9-bit address lines to access all 512 locations (2⁹ = 512).
2. Address range: 000000000 (0) to 111111111 (511).
Read and Write Operations:
1. Write: Stores an 8-bit value at a specified address.
2. Read: Retrieves stored 8-bit data when requested.
 Behaviour
Initially the memory is initialized with some random data to get the visibility of
the data change during the operations.
Design can be made reset which is synchronous as per the requirement. In reset
the output signals at both the ports becomes zero.
The read and write operations in the memory are controlled by the control
signals read enable and write enable.
To perform write at any port, the control signal write enable of that port is made
high. After the write operation is completed the control signal is made low.
To perform read at any port, the control signal read enable of that port is made
high. After the read operation is completed the control signal is made low.
Write and read are performed only when their particular control signals are
high.
When the write is performed again for any address location, then the old data is
overwritten with the new data
Invalid Address :
There might be a chance of any address at the ports is given beyond the range
of the memory. Addresses are tracked by the flags at both the ports.
If the particular flag goes high, that means some invalid address is given.
When the address goes out of range of ram, then the error message is displayed
indicating “Address is invalid, Generate a Valid address”. With this we can
ensure that data loss does not happen.
Simultaneous Write :
When a write operation is performed for the same address at both the ports
with different data, then the data is written into the memory with reference to
their clock signals at each port.
The latest updated data is seen in that memory location.
If write is performed for different address at the ports, the operations are
performed independently within their time slots.
Simultaneous Read :
When the simultaneous read is performed from both the ports for the
same address or the different address, the data is accessed from dual ports
without any interference.
Read and Write :
When a read and write operation occurs on the same port or the different
ports for the same address, the read operation may behave as follows:
Read new data - reads the updated data
Read old data - reads the data which is previously written into the
memory
If read, write operations occur on the same or different ports for the
different address, then they are performed independently as per their
respective clock signals.
Implementation
 Advantages
Higher Throughput:
By allowing multiple memory locations to be accessed simultaneously, DAR
boosts the overall data throughput of the system, making it ideal for
applications like video processing, large-scale simulations.
Reduced Wait Times:
Since read and write operations can occur concurrently, there is less wait time
for the CPU to access data, which leads to faster overall performance.
Improved Parallelism:
In multi-core processors/systems with parallel processing requirements, DAR
helps in managing multiple data streams at once, enhancing the system’s ability
to perform complex tasks in parallel.
Efficient Data Handling:
For applications requiring frequent updates to memory and fast retrieval,
like real-time systems/databases, DAR can handle these operations more
efficiently than single-port RAM.
 Applications
High-Performance Computing (HPC):
DAR is used where high-speed, parallel data access is required to maintain the
performance of complex computations. Systems such as weather forecasting
models or scientific simulations benefit from DAR.
Graphics Processing:
Graphics cards, or GPUs, benefit significantly from dual-address RAM. For
instance, the read/write parallelism can support both reading textures and
writing updated frame buffers simultaneously.
Embedded Systems:
In real-time embedded systems where both data storage and retrieval happen
simultaneously, such as automotive control systems or telecommunications
equipment, DAR can help improve performance.
Network Devices:
Devices like routers or switches that require fast packet processing can also
use DAR for high-speed access to network buffers or memory.
 Conclusion
Optimized RTL Implementation – Efficient design with minimal resource
utilization, reduced power consumption, and improved timing closure for
high performance.
Robust Verification Process – Verified using multiple test scenarios,
covering corner cases and edge conditions to ensure reliability and
functional correctness.
High-Speed Application Suitability – Designed for real-time processing,
handling high-frequency data transactions with minimal latency for
performance-critical applications.
Efficient Parallel Data Access – Enables simultaneous data retrieval,
minimizing access latency and maximizing throughput for time-sensitive,
high-speed operations.
 Future Enhancements
Optimized Multi-Port Architecture :
Developing more advanced multi-port architectures could allow multiple
processors or devices to access DAR memory without conflicts, increasing
overall system performance.
Power-Efficient Memory Cells :
DAR could evolve to incorporate low-power memory technologies such as
memristors, phase-change memory (PCM), or resistive RAM .
These technologies could reduce the power consumption of the memory,
which is crucial for mobile and embedded applications.
Enhanced ECC (Error Correction Codes) :
Future DAR implementations may incorporate more advanced error-
correcting codes to ensure data integrity and reliability in mission-critical
applications.
Thank You