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JoyitaBase Library Design Guide
Standard Cell
ocument number:
D ersion 40
V
Date of Issue: 1 December 2009
Authors: Stephen Kvinta, Keeho Kang, Marlin Frederick
Authorized by: Marlin Frederick
© Copyright ARM Limited 2009. All rights reserved.
Abstract
his document explains how to design quality library cells that have good timing, area, and power
T
characteristics. Methods are shown for estimating wire lengths within cells and determining the logical effort
of single-stage cells. Detailed procedures are given for sizing all cells. A method is explained for analyzing
electromigration effects in any process.
ARM Confidential
Contents
Abstract 1
1 ABOUT THIS DOCUMENT 13
1.1 hange control
C 3
1
1.1.1 C hange history 13
2 INTRODUCTION 15
3 PARASITIC ESTIMATION 15
3.1 Importance of Parasitic Estimation 15
3.2 Wire Capacitance Calculation 15
3.3 Wire Length Estimation 15
3.4 Wire Length Estimation Example 6
1
igure 3-1 Single finger inverter
F 16
Figure 3-2 two fingered inverter (left), three fingered inverter (center), four fingered inverter (right) 17
Table 3-1 Wire length equations for inverters 17
4 DESIGN OF ENGINEERING EXPERIMENTS (DOEE) 18
4.1 Introduction 18
4.2 Running DOEE 18
4.3 Details of DOEE 20
5 TRANSISTOR SIZING PHILOSOPHY 20
5.1 INV Beta Ratio 0
2
Figure 51 INV Beta Ratio Schematic 20
5.2 NAND2 Beta Ratios 1
2
igure 52 NAND2 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
F 21
Figure 53 NAND2 Average Beta Ratio Schematic 22
5.3 NAND3 Beta Ratios 2
2
igure 54 NAND3 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
F 23
Figure 55 NAND3 Average Beta Ratio Schematic 23
5.4 NAND4 Beta Ratios 4
2
igure 56 NAND4 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
F 24
Figure 57 NAND4 Average Beta Ratio Schematic 25
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5.5 NOR2 Beta Ratios 5
2
igure 58 NOR2 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
F 25
Figure 59 NOR2 Average Beta Ratio Schematic 26
5.6 NOR3 Beta Ratios 6
2
igure 510 NOR3 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
F 27
Figure 511 NOR3 Average Beta Ratio Schematic 27
5.7 Beta Ratio: flood-filled (X) 28
5.8 Beta Ratio: maximum (M) 28
5.9 Beta Ratio: average (A) 28
5.10 Beta Ratio: balanced (B) 28
5.11 Beta Ratio: equal edges (E) 28
5.12 Beta Ratio: rising ® 28
5.13 Beta Ratio: falling (F) 28
5.14 Beta Ratio Overview 29
5.15 Drive Strengths 29
6 OGICAL EFFORT
L 9
2
Figure 61 Logical Effort Schematic 30
Figure 62 CUT (Circuit Under Test) Examples 30
7 SINGLE STAGE CELLS 31
7.1 Flood-Filled Sizing 31
7.2 Inverter Cell Sizing 31
7.3 Other Single Stage Cell Sizing 2
3
7.3.1 NAND/NOR 32
7.3.2 AOI 32
7.3.2.1 AOI21 32
Figure 71 AOI21 Schematic 32
7.3.2.2 AOI31 33
Figure 72 AOI31 Schematic 33
7.3.2.3 AOI22 33
Figure 73 AOI22 Schematic 34
7.3.2.4 AOI32 34
Figure 74 AOI32 Schematic 34
7.3.2.5 AOI211 34
Figure 75 AOI211 Schematic 35
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.3.2.6 AOI221
7 3 5
Figure 76 AOI221 Schematic 35
7.3.2.7 AOI222 35
Figure 77 AOI222 Schematic 36
7.3.3 OAI 36
7.3.3.1 OAI211 36
Figure 78 OAI211 Schematic 36
7.3.3.2 OAI21 36
Figure 79 OAI21 Schematic 37
7.3.3.3 OAI221 37
Figure 710 OAI221 Schematic 37
7.3.3.4 OAI22 37
Figure 711 OAI22 Schematic 38
7.3.3.5 OAI222 38
Figure 712 OAI222 Schematic 38
7.3.3.6 OAI31 38
Figure 713 OAI31 Schematic 39
7.3.4 Compound Structures 39
7.3.4.1 AO21A1AI2 39
Figure 714 AO21A1AI2 Schematic 39
7.3.4.2 OA21A1OI2 40
Figure 715 OA21A1OI2 Schematic 40
7.4 Single Stage Cell Sizing Summary 40
8 TWO STAGE CELLS 40
8.1 Two Stage Sizing Strategy 0
4
8.1.1 AND 41
8.1.1.1 AND2 41
Figure 81 AND2 Schematic 41
Figure 82 AND2 Stick Diagram 41
8.1.1.2 AND3 42
8.1.1.3 AND4 42
8.1.2 NAND (Two-Stage) 42
8.1.2.1 NAND2B 42
Figure 83 NAND2B Schematic 42
8.1.2.2 NAND2XB 42
8.1.2.3 NAND3B 43
8.1.2.4 NAND3XXB 43
8.1.2.5 NAND4B 43
8.1.2.6 NAND4XXXB 43
8.1.3 AO 43
8.1.3.1 AO21 43
Figure 84 AO21 Schematic 43
Figure 85 AO21_X1M Example 44
Figure 86 AO21_X1M Example with Single Load Value 44
Figure 87 AO21_X1M Example Partially Sized 45
Figure 88 AO21_X1M Example Completed 45
8.1.3.2 AO1B2 45
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igure 89 AO1B2 Schematic
F 4 5
8.1.3.3 AO21B 46
Figure 810 AO21B Schematic 46
8.1.3.4 AO22 46
Figure 811 AO22 Schematic 46
8.1.3.5 AOI2XB1 46
Figure 812 AOI2XB1 Schematic 47
8.1.3.6 AOI21B 47
Figure 813 AOI21B Schematic 47
8.1.4 OA 47
8.1.4.1 OA211 47
Figure 814 OA211 Schematic 48
8.1.4.2 OA21 48
Figure 815 OA21 Schematic 48
8.1.4.3 OA22 48
Figure 816 OA22 Schematic 49
8.1.4.4 OAI21B 49
Figure 817 OAI21B Schematic 49
8.1.4.5 OAI2XB1 49
Figure 818 OAI2XB1 Schematic 50
8.1.5 OR 50
8.1.5.1 OR2 50
Figure 819 OR2 Schematic 50
8.1.5.2 OR3 50
Figure 820 OR3 Schematic 50
8.1.5.3 OR4 50
Figure 821 OR4 Schematic 51
8.1.5.4 OR6 51
Figure 822 OR6 Schematic 51
8.1.6 NOR (Two-Stage) 51
8.1.6.1 NOR2B 51
Figure 823 NOR2B Schematic 52
8.1.6.2 NOR2XB 52
Figure 824 NOR2XB Schematic 52
8.1.7 BUF 52
8.1.7.1 BUF 52
Figure 825 BUF Schematic 52
8.1.7.2 BUFH 53
Figure 826 BUFH Schematic 53
8.1.7.3 DLY2 53
Figure 827 DLY2 Schematic 53
9 ICG (INTEGRATED CLOCK GATES) 54
9.1 FRICG 4
5
9.1.1 Cell Usage 54
9.1.2 Cell Structure 54
Figure 91 FRICG Schematic 54
9.1.3 Cell Sizing 54
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9.2 PREICG 5
5
9.2.1 Cell Usage 55
9.2.2 Cell Structure 55
Figure 9-2 PREICG Schematic 55
9.2.3 Cell Sizing 55
9.3 POSTICG 6
5
9.3.1 Cell Usage 56
9.3.2 Cell Structure 56
Figure 93 POSTICG Schematic 57
9.3.3 Cell Sizing 57
10 XOR/XNOR 58
10.1 XOR2/XNOR2 8
5
10.1.1 Cell Usage 58
10.1.2 Cell Structure 58
Figure 101 XOR2 Schematic (left) and XNOR2 Schematic (right) 58
10.1.3 Cell Sizing 58
10.2 XOR3/XNOR3 9
5
10.2.1 Cell Usage 59
10.2.2 Cell Structure 59
Figure 102 XOR3 Schematic 59
Figure 103 XNOR3 Schematic 60
10.2.3 Cell Sizing 60
11 MUX 61
11.1 NAND Based Muxes 1
6
11.1.1 MX2 61
Figure 111 MX2 Schematic 61
11.2 Transmission Gate Based Muxes 2
6
11.2.1 MXT2 62
Figure 112 MXT2 Schematic 62
11.2.2 MXIT2 63
Figure 113 MXIT2 Schematic 63
11.2.3 MXT4 63
Figure 114 MXT4 Schematic 64
11.2.4 MXIT4 65
Figure 115 MXIT4 Schematic 65
12 ADDERS 66
12.1 ADDH 6
6
Figure 12-1 ADDH Schematic 66
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12.2 ADDF 6
6
Figure 12-2 ADDF Schematic 67
Figure 12-3 ADDF Schematic – GROUP 1 67
Figure 12-4 ADDF Schematic – GROUP 2 68
Figure 12-5 ADDF Schematic – GROUP 3 68
Figure 12-6 ADDF Schematic – GROUP 4 69
Figure 12-7 ADDF Schematic – GROUP 5 69
13 LATCHES 70
13.1 Basic Latch Types 70
13.2 Latch Sizing Philosophy 70
13.3 Latch Cells 0
7
13.3.1 Phi1 Latches 70
13.3.1.1 LATQ 70
Figure 13-1 LATQ Schematic 70
13.3.1.2 LATQN 71
Figure 13-2 LATQN Schematic 71
13.3.1.3 LATRQ 71
Figure 13-3 LATRQ Schematic 72
13.3.1.4 LATRPQN 72
Figure 13-4 LATRPQN Schematic 73
13.3.1.5 LATSPQ 73
Figure 13-5 LATSPQ Schematic 73
13.3.1.6 LATSQN 74
Figure 13-6 LATSQN Schematic 74
13.3.2 Phi2 Latches 74
13.3.2.1 LATNQ 74
Figure 13-7 LATNQ Schematic 75
13.3.2.2 LATNQN 75
Figure 13-8 LATNQN Schematic 75
13.3.2.3 LATNRQ 75
Figure 13-9 LATNRQ Schematic 76
13.3.2.4 LATNRPQN 76
Figure 13-10 LATNRPQN Schematic 76
13.3.2.5 LATNSPQ 76
Figure 13-11 LATNSPQ Schematic 77
13.3.2.6 LATNSQN 77
Figure 13-12 LATNSQN Schematic 77
14 FLOPS 78
14.1 Basic Flop Types 78
14.2 Flop Sizing Philosophy 78
14.3 Flop Cells 78
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14.3.1 Phi2/Phi1 Scan Flops 8
7
14.3.1.1 SDFFQ 78
Figure 14-1 SDFFQ Schematic 79
Figure 14-2 SDFFQ Schematic with Important Gates Noted in the Dashed Line Boxes 79
14.3.1.2 SDFFQN 80
Figure 14-3 SDFFQN Schematic 80
Figure 14-4 SDFFQN Schematic with Important Gates Noted in the Dashed Line Boxes 81
14.3.1.3 SDFFRPQ 82
Figure 14-5 SDFFRPQ Schematic 82
14.3.1.4 SDFFRPQN 82
Figure 14-6 SDFFRPQN Schematic 83
14.3.1.5 SDFFSQ 83
Figure 14-7 SDFFSQ Schematic 84
14.3.1.6 SDFFSQN 84
Figure 14-8 SDFFSQN Schematic 85
14.3.1.7 SDFFSRPQ 85
Figure 14-9 SDFFSRPQ Schematic 85
14.3.1.8 SDFFYQ 85
Figure 14-10 SDFFYQ Schematic 86
14.3.1.9 A2SDFFQ 86
Figure 14-11 A2SDFFQ Schematic 87
14.3.1.10 A2SDFFQN 87
Figure 14-12 A2SDFFQN Schematic 87
14.3.1.11 ESDFFQ 87
Figure 14-13 ESDFFQ Schematic 88
14.3.1.12 ESDFFQN 88
Figure 14-14 ESDFFQN Schematic 89
14.3.1.13 M2SDFFQ 89
Figure 14-15 M2SDFFQ Schematic 90
14.3.1.14 M2SDFFQN 90
Figure 14-16 M2SDFFQN Schematic 91
14.3.2 Phi1/Phi2 Scan Flops 91
14.3.2.1 SDFFNQ 91
Figure 14-17 SDFFNQ Schematic 92
14.3.2.2 SDFFNRPQ 92
Figure 14-18 SDFFNRPQ Schematic 92
14.3.2.3 SDFFNSQ 93
Figure 14-19 SDFFNSQ Schematic 93
14.3.2.4 SDFFNSRPQ 93
Figure 14-20 SDFFNSRPQ Schematic 94
14.3.3 Phi2/Phi1 Non-Scan Flops 94
14.3.3.1 DFFQ 94
Figure 14-21 DFFQ Schematic 95
14.3.3.2 DFFQN 95
Figure 14-22 DFFQN Schematic 95
14.3.3.3 DFFRPQ 95
Figure 14-23 DFFRPQ Schematic 96
14.3.3.4 DFFRPQN 96
Figure 14-24 DFFRPQN Schematic 96
14.3.3.5 DFFSQ 97
Figure 14-25 DFFSQ Schematic 97
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4.3.3.6 DFFSQN
1 9 7
Figure 14-26 DFFSQN Schematic 98
14.3.3.7 DFFSRPQ 98
Figure 14-27 DFFSRPQ Schematic 98
14.3.3.8 DFFYQ 99
Figure 14-28 DFFYQ Schematic 99
14.3.3.9 A2DFFQ 99
Figure 14-29 A2DFFQ Schematic 100
14.3.3.10 A2DFFQN 100
Figure 14-30 A2DFFQN Schematic 100
14.3.3.11 EDFFQ 101
Figure 14-31 EDFFQ Schematic 101
14.3.3.12 EDFFQN 101
Figure 14-32 EDFFQN Schematic 102
14.3.3.13 M2SDFFQ 102
Figure 14-33 M2DFFQ Schematic 103
14.3.3.14 M2DFFQN 103
Figure 14-34 M2DFFQN Schematic 104
14.3.4 Phi1/Phi2 Non-Scan Flops 104
14.3.4.1 DFFNQ 104
Figure 14-35 DFFNQ Schematic 105
14.3.4.2 DFFNRPQ 105
Figure 14-36 DFFNRPQ Schematic 105
14.3.4.3 DFFNSQ 106
Figure 14-37 DFFNSQ Schematic 106
14.3.4.4 DFFNSRPQ 106
Figure 14-38 DFFNSRPQ Schematic 107
15 BUFZ 107
15.1 Cell Usage 107
15.2 Cell Structure 07
1
Figure 15-1 BUFZ Schematic 107
15.3 Cell Sizing 107
16 DLY4 108
16.1 Cell Usage 108
16.2 Cell Structure 08
1
Figure 16-1 DLY4 Schematic 108
16.3 Cell Sizing 108
17 VOLTAGE REFERENCE CELLS 109
17.1 TIEHI 09
1
17.1.1 Cell Usage 109
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17.1.2 Cell Structure 09
1
Figure 17-1 TIEHI Schematic 109
17.1.3 Cell Sizing 109
17.2 TIELO 09
1
17.2.1 Cell Usage 109
17.2.2 Cell Structure 109
Figure 17-2 TIELO Schematic 110
17.2.3 Cell Sizing 110
18 REGISTER FILES 110
18.1 RF1R1WS 10
1
18.1.1 Cell Usage 110
18.1.2 Cell Structure 110
Figure 18-1 RF1R1WS Schematic 111
18.1.3 Cell Sizing 111
18.2 RF2R1WS 11
1
18.2.1 Cell Usage 111
18.2.2 Cell Structure 111
Figure 18-2 RF2R1WS Schematic 112
18.2.3 Cell Sizing 112
18.3 RF1R2WS 13
1
18.3.1 Cell Usage 113
18.3.2 Cell Structure 113
Figure 18-3 RF1R2WS Schematic 113
18.3.3 Cell Sizing 113
18.4 RF2R2WS 14
1
18.4.1 Cell Usage 114
18.4.2 Cell Structure 114
Figure 18-4 RF2R2WS Schematic 114
18.4.3 Cell Sizing 115
19 LAYOUT FINISHING CELLS 115
19.1 ANTENNA Cells 15
1
19.1.1 Cell Usage 115
19.1.2 Cell Structure 116
Figure 19-1 ANTENNA Schematic 116
19.1.3 Cell Sizing 116
19.2 FILLCAP Cells 16
1
19.2.1 Cell Usage 116
19.2.2 Cell Structure 116
Figure 19-2 FILLCAP Schematic 117
19.2.3 Cell Sizing 117
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20 TK CELLS
A 17
1
Table 20-1 ATK Cell Types 117
20.1 Full Adders 17
1
20.1.1 ADDFCIN 117
20.1.1.1 Cell Usage 117
20.1.1.2 Cell Structure 117
Figure 20-1 ADDFCIN Schematic 118
20.1.1.3 Cell Sizing 118
20.1.2 ADDFH 118
20.1.2.1 Cell Usage 118
20.1.2.2 Cell Structure 119
Figure 20-2 ADDFH Schematic 119
20.1.2.3 Cell Sizing 119
20.2 Booth Encoders 19
1
20.2.1 BENC 119
20.2.1.1 Cell Usage 119
20.2.1.2 Cell Structure 119
Figure 20-3 BENC Schematic 120
Figure 20-4 BENC High Drive Strength Schematic 121
20.2.1.3 Cell Sizing 121
20.3 Booth Muxes 21
1
20.3.1 BMXIT 121
20.3.1.1 Cell Usage 121
20.3.1.2 Cell Structure 121
Figure 20-5 BMXIT Schematic 122
20.3.1.3 Cell Sizing 122
20.3.2 BMXT 123
20.3.2.1 Cell Usage 123
20.3.2.2 Cell Structure 123
Figure 20-6 BMXT Schematic 123
20.3.2.3 Cell Sizing 123
20.4 Carry Generators 24
1
20.4.1 CGENCIN 124
20.4.1.1 Cell Usage 124
20.4.1.2 Cell Structure 124
Figure 20-7 CGENCIN Schematic 125
20.4.1.3 Cell Sizing 125
20.4.2 CGENCON 126
20.4.2.1 Cell Usage 126
20.4.2.2 Cell Structure 126
Figure 20-8 CGENCON Schematic 126
20.4.2.3 Cell Sizing 126
20.4.3 CGENI 127
20.4.3.1 Cell Usage 127
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0.4.3.2 Cell Structure
2 1 27
Figure 20-9 CGENI Schematic 127
20.4.3.3 Cell Sizing 127
20.4.4 CGEN 127
20.4.4.1 Cell Usage 127
20.4.4.2 Cell Structure 127
Figure 20-10 CGEN Schematic 127
20.4.4.3 Cell Sizing 128
20.5 Compressors 28
1
20.5.1 CMPR42 128
20.5.1.1 Cell Usage 128
20.5.1.2 Cell Structure 128
Figure 20-11 CMPR42 Schematic 129
20.5.1.3 Cell Sizing 129
21 LVS GUIDELINES 130
21.1 General Recommendations 30
1
21.1.1 Layout N-Well and Substrate Layers 130
21.1.2 Schematic 1-Ohm Resistors 130
21.1.3 CDL Netlist *.CONNECT Statements 130
21.1.4 Transistor Folding 130
21.2 Known Limitations 30
1
21.2.1 Foundry-provided LVS Deck Issues 130
21.2.2 EDA tool issues 131
21.3 Cell-Specific Guidelines 31
1
21.3.1 Layout Finishing Cells 131
21.3.1.1 ENDCAPTIE 131
21.3.1.2 FILL 131
21.3.1.3 FILLTIE 131
21.3.1.4 FILLTIESB 131
22 ELECTROMIGRATION 132
22.1 Definition 132
22.2 Causes 132
22.3 Failure Rate 132
22.4 Prevention 132
22.5 Pre-Analysis 132
22.6 Analysis 32
1
22.6.1 Schematic 133
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igure 21-1 EM Analysis Schematic for Inverters
F 1 33
Figure 21-2 EM Analysis Schematic for Nand2 Cells 133
22.6.2 Load Simulation 134
22.6.3 Current Simulation 134
22.6.3.1 Average Current 134
22.6.3.2 Peak Current 135
22.6.3.3 RMS Current 135
22.7 Sample Library Analysis 35
1
22.7.1 Understanding the Design Rules 135
22.7.2 Applying the Design Rules 136
22.7.2.1 Average Current 136
Table 21-1 TSMC 65G Minimum Metal Widths 136
22.7.2.2 Peak Current 136
22.7.2.3 RMS Current 137
22.8 Final Comments 138
23 CONCLUSION 138
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1 ABOUT THIS DOCUMENT
1.1 Change control
1.1.1 Change history
Issue Date By Change
A01 15 December 2005 Stephen Kvinta First draft
A02 11 January 2006 Stephen Kvinta dded sections on wire parasitics, beta ratios, and single
A
stage cell sizing
A03 12 January 2006 Stephen Kvinta Added sections on aoi cell sizing
A04 19 January 2006 Stephen Kvinta dded section on logical effort and began two stage cell
A
sizing section
A05 20 January 2006 Stephen Kvinta dded section on oai cell sizing and continued two stage
A
cell sizing section
A06 23 January 2006 Stephen Kvinta inished two stage cell sizing section, made corrections
F
to preicg section, and added mux sizing section
A07 26 January 2006 Stephen Kvinta dded rising and falling beta ratios, added XOR3/XNOR3
A
sizing section, and clarified flood-filled beta ratio section
A08 27 January 2006 Stephen Kvinta Added posticg sizing section
A09 6 February 2006 Stephen Kvinta dded electromigration section and rewrote beta ratio
A
section
A10 10 February 2006 Stephen Kvinta dded adder sizing section and clarified beta ratio
A
section based on feedback from BLR
A11 13 February 2006 Stephen Kvinta Began latch sizing section
A12 13 February 2006 Stephen Kvinta Finished latch sizing section
A13 2 March 2006 Stephen Kvinta egan flop sizing section and changed ‘ovrd’ to ‘ovrd_’ in
B
posticg and clarified aoi and oai single stage sizing
sections
A14 3 March 2006 Stephen Kvinta General cleanup of document
A15 30 October 2006 Stephen Kvinta Added doee section
A16 14 November 2006 Stephen Kvinta In process of changing cell and pin names to current
naming convention
A17 16 November 2006 Stephen Kvinta Finished changing cell and pin names
A18 17 November 2006 Stephen Kvinta inished flop sizing section and added BUFZ and DLY4
F
sections
A19 27 November 2006 Stephen Kvinta hanged cell and pin names back to 65nm convention,
C
added Compound Structures section, fixed AO1B2 and
AO21B sizing sections, and added Voltage Reference
section
A20 28 November 2006 Stephen Kvinta Adding Register File Section
A21 29 November 2006 Stephen Kvinta inished Register File Section and changed document
F
title
A22 29 November 2006 Stephen Kvinta Added Layout Finishing Cell Section
A23 30 November 2006 Stephen Kvinta Adding ATK Cell Section
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A24 1 December 2006 Stephen Kvinta Finished ATK Cell Section (CMPR42 is incomplete)
A25 6 December 2006 Stephen Kvinta Added OAI31 Cell
A26 12 December 2006 Stephen Kvinta Updated DOEE Section and SDFFQ Section
A27 3 January 2007 Stephen Kvinta ade corrections throughout the document and finished
M
CMPR42 section
A28 25 January 2007 Stephen Kvinta Changed compound cell names
A29 26 February 2007 Stephen Kvinta Updated ATK Cell Section
A30 7 March 2007 Stephen Kvinta Made corrections to ADDFCIN section
A31 8 March 2007 Stephen Kvinta Made corrections to CGENCIN section
A32 25 July 2007 Stephen Kvinta hanged ADDFCIN, ADDFH, CGENCIN, and CGENCON
C
topologies and removed the FILLCAPTIE section
A33 19 February 2008 Stephen Kvinta Made corrections to SDFFYQ section
A34 2 December 2008 Keeho Kang Added LVS Guidelines section
A35 23 February 2009 Stephen Kvinta Added EM comment about M1 finger width
A36 17 March 2009 Stephen Kvinta Made corrections to compound cell sizing
A37 25 March 2009 Stephen Kvinta Updated CMPR42 section
A38 30 March 2009 Stephen Kvinta Made corrections to OAI31 section
A39 18 August 2009 Stephen Kvinta Fixed typo in EM section
A40 1 December 2009 Stephen Kvinta Added more comments to EM section for clarity
2 INTRODUCTION
esigning library cells is a complex task that requires a good understanding of electrical and layout issues. The
D
key is to find a good balance of power, performance, and area. It is essential to include good estimates of wire
parasitics when drawing schematics, so a procedure is shown for how to estimate wire lengths. Multiple beta
ratios have been proven to improve performance. In order to size multi-stage cells, it is necessary to know the
logical effort values for the single-stage cells.
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ingle-stage cells are the simplest cells to design. Multi-stage cells require a good understanding of wire
S
parasitics, beta ratios, and the concepts of Logical Effort.
3 PARASITIC ESTIMATION
his section describes how to estimate wire parasitics. First, there is a quick discussion of why parasitic
T
estimation is necessary. Then, there is a discussion of how to accurately measure the lengths of wires.
3.1 Importance of Parasitic Estimation
here are two main factors that influence the delay of a cell: the gate delay and the wire delay. As processes
T
become smaller, the gate delay becomes smaller. However, the wire delay remains fairly constant. Thus, the
wire delay becomes a larger part of the total delay as processes become smaller. Therefore, it is essential to
have an accurate estimate of wire parasitics.
3.2 Wire Capacitance Calculation
he wire capacitance is calculated by multiplying the length of the wire by the capacitance per unit of wire. The
T
capacitance per unit of wire depends on the process and the metal layer. A technology file needs to be created
for each process that contains these values. The wire length needs to be calculated by the circuit designer and
entered into the schematic. The schematic netlister multiplies the wire length from the schematic and the
capacitance per unit of wire from the technology file and sets this value as the wire capacitance.
3.3 Wire Length Estimation
In order to estimate the lengths of the wires in the cells, some basic DRC and cell image information is needed.
● The length of the “middle dead space” between the p-diffusion and the n-diffusion
● The length of metal1 overlap over p-diffusion and n-diffusion
● The distance between two poly stripes
● The maximum single finger p-channel and n-channel transistor sizes
or a sample library, the “middle dead space” length is 320 nm, the metal1 overlap distance (overlap) is 400 nm
F
for both p-diffusion and n-diffusion, the distance between two poly stripes (poly space) is 260 nm, the maximum
single finger p-channel transistor size is 700 nm, and the maximum single finger n-channel transistor size is 580
nm.
fter these values have been calculated, either actual layout or stick diagrams need to be drawn for each cell.
A
Based on the layout or stick diagrams, equations need to be written to calculate the length of each wire. Once
the wire lengths have been calculated, these values need to be added to the cell schematics using “wire_c”
instances from the armPrimitives library.
3.4 Wire Length Estimation Example
ere is an example of how to estimate the wire lengths for an inverter. Figure 3-1 shows the stick diagram for a
H
single finger inverter. This figure is not drawn to scale. Diffusion is brown, poly is red and metal1 is green.
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Figure 3-1 Single finger inverter
here are two wire lengths to calculate for inverters: “A” and “Y”. The “A” length is equal to the poly length plus a
T
small horizontal metal1 length above the contact. The “Y” length is equal to the metal1 vertical length.
In equation form,
= dead space between diffusions + small horizontal metal1 length
A
Y = dead space between diffusions + (2 * metal1 overlap)
For the sample library, these equations become
= 320 nm + 100 nm = 420 nm
A
Y = 320 nm + (2 * 400 nm) = 1120 nm
where 100 nm is an estimated value for the small horizontal metal1 length.
he previous equations work for single finger inverters, but there needs to be a more general equation that works
T
for any number of fingers. Figure 3-2 shows stick diagrams for inverters with two, three, and four fingers.
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Figure 3-2 two fingered inverter (left), three fingered inverter (center), four fingered inverter (right)
Here are the wire length equations for these cells.
# of fingers A Y
1 iddle dead space + small
m middle dead space + (2 * overlap)
horizontal width
2 (2 * middle dead space) + small iddle dead space + (2 * overlap)
m
horizontal width + poly space + (2 * poly space)
3 (3 * middle dead space) + small iddle dead space + (4 * overlap)
m
horizontal width + (2 * poly space) + (4 * poly space)
4 (4 * middle dead space) + small iddle dead space + (4 * overlap)
m
horizontal width + (3 * poly space) + (6 * poly space)
Table 3-1 Wire length equations for inverters
ow there is a way to generalize these equations into a single “A” equation and a single “Y” equation that can be
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used no matter how many fingers there are.
= (# of fingers * middle dead space) + small horizontal width + ((# of fingers – 1) * poly space)
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Y = middle dead space + (2 * (ceiling (# of fingers / 2)) * overlap) + (2 * (# of fingers – 1) * poly space)
he “ceiling” function is the same as rounding up. For example, ceiling (1/2) = 1, ceiling (2/2) = 1, ceiling (3/2) =
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2, and ceiling (4/2) = 2.
ollowing this example, stick diagrams can be drawn for all cells and the wire lengths can be determined. More
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complex cells will have more wires that need to be estimated than just the input and output. Multi-stage cells
such as ANDs and ORs have internal nodes that need to be estimated as well.
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4 DESIGN OF ENGINEERING EXPERIMENTS (DOEE)
4.1 Introduction
he doee simulations determine the sizes of all single-stage and most two-stage cells. The inputs required are
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some basic physical dimensions and HSPICE models. The output, which is a Microsoft Excel spreadsheet,
contains the following information.
● eta Ratios for all single-stage cells
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● Logical Effort values for all single-stage cells
● Wire parasitic estimates for all single-stage cells
● The optimal well boundary location
● Transistor sizes for all single-stage and most two-stage cells
There is work underway to automatically have schematics drawn based on the results of the doee simulations.
4.2 Running DOEE
Here are the steps for running doee.
1) Login to a Linux machine. SPICE runs much faster on Linux than Solaris.
2) Load the hspice module. Type “module load avanti/star_hspice/2006.09” or load a newer version.
3) Unzip and untar the doee.tar.gz file in /projects/pipd/common/45nm/sc_adv9/dev/doee.
4) Ensure that you have the necessary plug-ins necessary for MS Excel. In Excel, go to Tools -> Add-Ins and
check all boxes except for “Euro Currency Tools”.
5) Run the 'update_spice_model' script in the doee directory. This script adds the spice model names to all of
the spice input files.
The syntax is scripts/update_spice_model -n nfet_model -p pfet_model -x
he –n option sets the n-channel transistor spice model name based on the nfet_model variable.
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The –p option sets the p-channel transistor spice model name based on the pfet_model variable.
The –x option puts an ‘X’ in front of the transistor lines in the netlist. This option is optional.
6) Update the 'base.inc' file in the config directory.
Change the .lib line to point to the spice models, change the vdd, and temp. Also, change the values in the
" Process dependant parameters" section. "w_total" is the maximum single fingerp ch + nch transistorsize.
"w_min" is the minimum transistor size. "w_step" is used for sweeping the widths and should stay at 0.01u.
"n_ext" is the sum of contact-poly spacing, contact width, and diffusion overlap of contact. "a_ext" is
minimum poly-poly spacing. "s_ext" is the sum of contact-poly spacing, contact
width, and contact-poly spacing.
7) Run the 'run_hspice' script in the meas_inv directory. Wait for the simulation to finish.
Type ‘scripts/run_hspice’ in the meas_inv directory.
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8) Run the 'meas_beta' script in the meas_inv directory. The inverter 'm' and 'b' beta ratios will be displayed.
Type ‘scripts/meas_beta –i’ in the meas_inv directory.
9) Add the inverter 'm' and 'b' beta ratio values to the Excel spreadsheet in the spreadsheet directory.
0) Add the inverter 'm' and 'b' device sizes to the 'inv_values.inc' file in the config directory. These sizes are
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calculated based on the beta ratios and the maximum transistor sizes.
11) Run the 'run_hspice' script in the meas_le_m and meas_le_b directories. Wait for the simulations to finish.
ype ‘scripts/run_hspice’ in the meas_le_m directory.
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Type ‘scripts/run_hspice’ in the meas_le_b directory.
12) Run the 'meas_beta' script in the meas_le_m directory. The logical effort values for 'm' beta ratio cells will
be displayed.
Type ‘scripts/meas_beta –lm’ in the meas_le_m directory.
13) Run the 'meas_beta' script in the meas_le_b directory. The logical effort values for 'b' beta ratio cells will be
displayed.
Type ‘scripts/meas_beta –lb’ in the meas_le_b directory.
14) Add the logical effort values to the spreadsheet.
15) Add the logical effort values to the 'le_m_values.inc' and 'le_b_values.inc' files in the config directory.
16) Run the 'run_hspice' script in the meas_m and meas_b directories. Wait for the simulations to finish.
ype ‘scripts/run_hspice’ in the meas_m directory.
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Type ‘scripts/run_hspice’ in the meas_b directory.
17) Run the 'meas_beta' script in the meas_m directory. The 'm' beta ratios will be displayed.
Type ‘scripts/meas_beta –m’ in the meas_m directory.
18) Run the 'meas_beta' script in the meas_b directory. The 'b' beta ratios will be displayed.
Type ‘scripts/meas_beta –b’ in the meas_b directory.
19) Add the beta ratio values to the spreadsheet.
20) Add the maximum device sizes to the spreadsheet in cells K4, K5, and K6.
21) Go to the 'WBA' page of the spreadsheet and find the PFET size that is 2/3 of way down between the upper
YES and lower YES. Enter this PFET size in cell K7 of the 'MV' page.
22) Add the PFET and NFET sizes from cells K7 and K8 of the spreadsheet to the 'max_values.inc' file in the
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config directory.
23) Run the 'run_hspice' script in the meas_a directory. Wait for the simulation to finish.
Type ‘scripts/run_hspice’ in the meas_a directory.
24) Run the 'meas_beta' script in the meas_a directory. The 'a' beta ratios will be displayed.
Type ‘scripts/meas_beta –a’ in the meas_a directory.
25) Add the beta ratio values to the spreadsheet.
4.3 Details of DOEE
he doee simulations are shown in detail in the next two sections. The beta ratio simulations are shown in the
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“TRANSISTOR SIZING PHILOSOPHY” section. The logical effort simulations are shown in the “LOGICAL
EFFORT” section.
5 TRANSISTOR SIZING PHILOSOPHY
even unique beta ratios are defined in this section. Multiple pre-defined beta ratios have been shown to provide
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additional performance in several circumstances. These beta ratios should not be confused with the natural beta
ratio of the process. The natural beta ratio is the device ratio that results in equal rising and falling drive strength.
The final section defines the drive strength strategy.
5.1 INV Beta Ratio
he primary beta ratio will be determined by finding the smallest delay through an even number of inverters, each
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having a stage effort of four. Refer to the “Logical Effort” book by Sutherland, Sproull, and Harris for a
description of stage effort (f), electrical effort (h), and logical effort (g). Since the logical effort of an inverter is one
by definition, the electrical effort or more commonly gain of each inverter has been set to four. The doee
simulations find this minimum delay beta ratio by using a schematic as shown in Figure 5-1. The “mult = 4”
blocks are used to generate a fanout of four. These blocks are drawn using the “imult” symbol in the
armPrimitives library. Each inverter is set to the same fixed total device width. Then this total width is swept
from a ratio where the PFET dominates to NFET dominating. The ratio that results in the minimum of the
maximum propagation delay is the inverter beta ratio for the library. Typical processes have primary beta ratios
of 1.2 to 1.7. The timing is measured for the middle four inverters (net ‘m04’ to net ‘m12’). The first two inverters
are there to generate a realistic input driver and the last two inverters represent a realistic load.
Figure 51 INV Beta Ratio Schematic
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he inverter beta ratio that is found from this simulation is the flood-filled ratio (X), the maximum ratio (M), and the
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average ratio (A) for inverters. The ‘X’ is sometimes left off of the cell name. These beta ratio types are explained
in detail later in this section.
he inverter balanced beta ratio (B) is found using the schematic in Figure 5-1. However, the timing is measured
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for only one inverter (net ‘m04’ to net ‘m06’). Each inverter is set to the same fixed total device width. Then this
total width is swept from a ratio where the PFET dominates to NFET dominating. The ratio that results in the
minimum of the maximum propagation delay from net ‘m04’ to ‘m06’ is the inverter balanced beta ratio for the
library.
imilarly, the inverter equal edge beta ratio (E) is found using the schematic in Figure 5-1. The edge rates are
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measured at the output of only one inverter (net ‘m06’). Each inverter is set to the same fixed total device width.
Then this total width is swept from a ratio where the PFET dominates to NFET dominating. The ratio that results
in an equal rising and falling edge rate for net ‘m06’ is the inverter equal edge beta ratio for the library.
5.2 NAND2 Beta Ratios
he flood-filled beta ratio (X) for NAND2 is the same as the inverter flood-filled ratio. The NAND2 flood-filled
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sizes are the same as the inverter flood-filled sizes. For example, NAND2_X2X has the same transistor sizes as
INV_X2X.
he maximum (M) and average (A) beta ratios for NAND2 are not the same as the flood-filled ratio (X). These
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beta ratios are determined using the doee simulations. The NAND2 maximum beta ratio schematic is shown in
Figure 5-2 and the NAND2 average beta ratio schematic is shown in Figure 5-3.
Figure 52 NAND2 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
o find the maximum beta ratio, the inverters are sized using the inverter beta ratio (‘M’ or ‘X’) found in Section
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5.1. ‘wp_inv’ and ‘wn_inv’ are single fingers. The NAND2 total transistor size is the same as the inverter total
transistor size. In other words, the sum of ‘wp_inv’ and ‘wn_inv’ is equal to the sum of ‘wp’ and ‘wn’. ‘wp’ or
‘wn’ is swept to find the minimum of the maximum delay from ‘m04’ to ‘m12’. The value of ‘fo_single’ is equal to
four divided by the logical effort of NAND2 (gNAND2). Section 6 shows how to calculate logical effort values.
he NAND2 balanced beta ratio (B) is found using the schematic in Figure 5-2. However, the timing is measured
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for only the NAND2 (net ‘m04’ to net ‘m06’). ‘wp’ or ‘wn’ is swept to find the minimum of the maximum delay
from ‘m04’ to ‘m06’. The ratio that results is the NAND2 balanced beta ratio for the library.
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imilarly, the NAND2 equal edge beta ratio (E) is found using the schematic in Figure 5-2. The edge rates are
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measured at the output of only the NAND2 (net ‘m06’). ‘wp’ or ‘wn’ is swept to find equal rising and falling edges
for net ‘m06’. The ratio that results is the NAND2 equal edge beta ratio for the library.
Figure 53 NAND2 Average Beta Ratio Schematic
o find the average beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. ‘wn_nand2’ is the maximum single finger n-channel transistor size. ‘wp_nand2’ is
swept to find the minimum of the maximum delay from ‘a04’ to ‘a16’.
5.3 NAND3 Beta Ratios
he flood-filled beta ratio (X) for NAND3 is the same as the inverter flood-filled ratio. The NAND3 flood-filled
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sizes are the same as the inverter flood-filled sizes. For example, NAND3_X2X has the same transistor sizes as
INV_X2X.
he maximum (M) and average (A) beta ratios for NAND3 are not the same as the flood-filled ratio (X). These
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beta ratios are determined by doee simulations. The NAND3 maximum beta ratio schematic is shown in Figure
5-4 and the NAND3 average beta ratio schematic is shown in Figure 5-5.
Figure 54 NAND3 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
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o find the maximum beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. The NAND3 total transistor size is the same as the inverter total transistor size. In
other words, the sum of ‘wp_inv’ and ‘wn_inv’ is equal to the sum of ‘wp’ and ‘wn’. ‘wp’ or ‘wn’ is swept to find
the minimum of the maximum delay from ‘m04’ to ‘m12’. The value of ‘fo_single’ is equal to four divided by the
logical effort of NAND3 (gNAND3). Section 6 showshow to calculate logical effort values.
he NAND3 balanced beta ratio (B) is found using the schematic in Figure 5-4. However, the timing is measured
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for only the NAND3 (net ‘m04’ to net ‘m06’). ‘wp’ or ‘wn’ is swept to find the minimum of the maximum delay
from ‘m04’ to ‘m06’. The ratio that results is the NAND3 balanced beta ratio for the library.
imilarly, the NAND3 equal edge beta ratio (E) is found using the schematic in Figure 5-4. The edge rates are
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measured at the output of only the NAND3 (net ‘m06’). ‘wp’ or ‘wn’ is swept to find equal rising and falling edges
for net ‘m06’. The ratio that results is the NAND3 equal edge beta ratio for the library.
Figure 55 NAND3 Average Beta Ratio Schematic
o find the average beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. ‘wn_nand3’ is the maximum single finger n-channel transistor size. ‘wp_nand3’ is
swept to find the minimum of the maximum delay from ‘a04’ to ‘a16’.
5.4 NAND4 Beta Ratios
he flood-filled beta ratio (X) for NAND4 is the same as the inverter flood-filled ratio. The NAND4 flood-filled
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sizes are the same as the inverter flood-filled sizes. For example, NAND4_X2X has the same transistor sizes as
INV_X2X.
he maximum (M) and average (A) beta ratios for NAND4 are not the same as the flood-filled ratio (X). These
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beta ratios are determined by doee simulations. The NAND4 maximum beta ratio schematic is shown in Figure
5-6 and the NAND4 average beta ratio schematic is shown in Figure 5-7.
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Figure 56 NAND4 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
o find the maximum beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. The NAND4 total transistor size is the same as the inverter total transistor size. In
other words, the sum of ‘wp_inv’ and ‘wn_inv’ is equal to the sum of ‘wp’ and ‘wn’. ‘wp’ or ‘wn’ is swept to find
the minimum of the maximum delay from ‘m04’ to ‘m12’. The value of ‘fo_single’ is equal to four divided by the
logical effort of NAND4 (gNAND4). Section 6 showshow to calculate logical effort values.
he NAND4 balanced beta ratio (B) is found using the schematic in Figure 5-6. However, the timing is measured
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for only the NAND4 (net ‘m04’ to net ‘m06’). ‘wp’ or ‘wn’ is swept to find the minimum of the maximum delay
from ‘m04’ to ‘m06’. The ratio that results is the NAND4 balanced beta ratio for the library.
imilarly, the NAND4 equal edge beta ratio (E) is found using the schematic in Figure 5-6. The edge rates are
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measured at the output of only the NAND4 (net ‘m06’). ‘wp’ or ‘wn’ is swept to find equal rising and falling edges
for net ‘m06’. The ratio that results is the NAND4 equal edge beta ratio for the library.
Figure 57 NAND4 Average Beta Ratio Schematic
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o find the average beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. ‘wn_nand4’ is the maximum single finger n-channel transistor size. ‘wp_nand4’ is
swept to find the minimum of the maximum delay from ‘a04’ to ‘a16’.
5.5 NOR2 Beta Ratios
he flood-filled beta ratio (X) for NOR2 is the same as the inverter flood-filled ratio. The NOR2 flood-filled sizes
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are the same as the inverter flood-filled sizes. For example, NOR2_X2X has the same transistor sizes as
INV_X2X.
he maximum (M) and average (A) beta ratios for NOR2 are not the same as the flood-filled ratio (X). These beta
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ratios are determined by doee simulations. The NOR2 maximum beta ratio schematic is shown in Figure 5-8 and
the NOR2 average beta ratio schematic is shown in Figure 5-9.
Figure 58 NOR2 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
o find the maximum beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. The NOR2 total transistor size is the same as the inverter total transistor size. In
other words, the sum of ‘wp_inv’ and ‘wn_inv’ is equal to the sum of ‘wp’ and ‘wn’. ‘wp’ or ‘wn’ is swept to find
the minimum of the maximum delay from ‘m04’ to ‘m12’. The value of ‘fo_single’ is equal to four divided by the
logical effort of NOR2 (gNOR2). Section 6 shows howto calculate logical effort values.
he NOR2 balanced beta ratio (B) is found using the schematic in Figure 5-8. However, the timing is measured
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for only the NOR2 (net ‘m04’ to net ‘m06’). ‘wp’ or ‘wn’ is swept to find the minimum of the maximum delay from
‘m04’ to ‘m06’. The ratio that results is the NOR2 balanced beta ratio for the library.
imilarly, the NOR2 equal edge beta ratio (E) is found using the schematic in Figure 5-8. The edge rates are
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measured at the output of only the NOR2 (net ‘m06’). ‘wp’ or ‘wn’ is swept to find equal rising and falling edges
for net ‘m06’. The ratio that results is the NOR2 equal edge beta ratio for the library.
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Figure 59 NOR2 Average Beta Ratio Schematic
o find the average beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. ‘wn_nor2’ is the maximum single finger n-channel transistor size. ‘wp_nor2’ is swept
to find the minimum of the maximum delay from ‘a04’ to ‘a16’.
5.6 NOR3 Beta Ratios
he flood-filled beta ratio (X) for NOR3 is the same as the inverter flood-filled ratio. The NOR3 flood-filled sizes
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are the same as the inverter flood-filled sizes. For example, NOR3_X2X has the same transistor sizes as
INV_X2X.
he maximum (M) and average (A) beta ratios for NOR3 are not the same as the flood-filled ratio (X). These beta
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ratios are determined by doee simulations. The NOR3 maximum beta ratio schematic is shown in Figure 5-10
and the NOR3 average beta ratio schematic is shown in Figure 5-11.
Figure 510 NOR3 Maximum, Balanced, and Equal Edge Beta Ratio Schematic
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o find the maximum beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. The NOR3 total transistor size is the same as the inverter total transistor size. In
other words, the sum of ‘wp_inv’ and ‘wn_inv’ is equal to the sum of ‘wp’ and ‘wn’. ‘wp’ or ‘wn’ is swept to find
the minimum of the maximum delay from ‘m04’ to ‘m12’. The value of ‘fo_single’ is equal to four divided by the
logical effort of NOR3 (gNOR3). Section 6 shows howto calculate logical effort values.
he NOR3 balanced beta ratio (B) is found using the schematic in Figure 5-10. However, the timing is measured
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for only the NOR3 (net ‘m04’ to net ‘m06’). ‘wp’ or ‘wn’ is swept to find the minimum of the maximum delay from
‘m04’ to ‘m06’. The ratio that results is the NOR3 balanced beta ratio for the library.
imilarly, the NOR3 equal edge beta ratio (E) is found using the schematic in Figure 5-10. The edge rates are
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measured at the output of only the NOR3 (net ‘m06’). ‘wp’ or ‘wn’ is swept to find equal rising and falling edges
for net ‘m06’. The ratio that results is the NOR3 equal edge beta ratio for the library.
Figure 511 NOR3 Average Beta Ratio Schematic
o find the average beta ratio, the inverters are sized using the beta ratio found in Section 5.1. ‘wp_inv’ and
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‘wn_inv’ are single fingers. ‘wn_nor3’ is the maximum single finger n-channel transistor size. ‘wp_nor3’ is swept
to find the minimum of the maximum delay from ‘a04’ to ‘a16’.
5.7 Beta Ratio: flood-filled (X)
he flood-filled beta ratio is determined by the layout. For single-stage flood-filled cells, the beta ratio is the
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maximum p-channel finger size divided by the maximum n-channel finger size. For multi-stage flood-filled cells,
the output stage is flood-filled and the other stages are sized such that the delay through the entire cell results in
an ‘M’ beta ratio.
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5.8 Beta Ratio: maximum (M)
he maximum beta ratio, referred to as ‘M’ in the naming convention, results in a minimization of the maximum
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edge delay. Mathematically, this beta ratio refers to the minimum of maximum(risePD,fallPD). ‘risePD’ refers to
the propagation delay rising and ‘fallPD’ refers to the propagation delay falling.
5.9 Beta Ratio: average (A)
he average beta ratio, referred to as ‘A’ in the naming convention, results in a minimization of the average edge
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delay. Mathematically, this beta ratio refers to the minimum of average(risePD,fallPD). ‘risePD’ refers to the
propagation delay rising and ‘fallPD’ refers to the propagation delay falling.
The average beta ratio can give better performance when even numbers of the gate of interest are in a cycle, and
will usually give lower power for single stage cells than the flood-filled ratio. This beta ratio is offered only for the
most common cell topologies. It should be noted that cells with stacked p-channel transistors could have poor
transition times when using this ratio, making wire parasitic more of an issue.
Note that the A beta ratio simulation schematics employ a combination of “off path” loading made up of inverters
and “on path” loading which consists of copies of the cell under test. This configuration better accounts for the
mix of “average” beta ratio configurations in typical designs and fixed parasitic loading. Tuning the A beta ratio
using a regular fanout-of-4 schematic (like those used for M and B beta ratios) leads to sizing that is undesirably
close to flood-filled, especially if effects such as Ids scaling with width are present in the technology.
5.10 Beta Ratio: balanced (B)
he balanced beta ratio, referred to as ‘B’ in the naming convention, results in a balanced rise and fall delay.
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Cells with this beta ratio are primarily used in the clock tree. The beta ratio value for these cells is much larger
than it is for the other drive strengths because the p-channel transistors are upsized to get balanced delay.
5.11 Beta Ratio: equal edges (E)
The equal edges beta ratio, referred to as ‘E’ in the naming convention, results in equal output edge rates.
5.12 Beta Ratio: rising (R)
ells with the ‘R’ beta ratio favor the output rising edge. These are single stage cells where the beta ratio is
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larger than the ‘M’ or ‘X’ beta ratios.
5.13 Beta Ratio: falling (F)
ells with the ‘F’ beta ratio favor the output falling edge. These are single stage cells where the beta ratio is
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smaller than the ‘M’ or ‘X’ beta ratios.
5.14 Beta Ratio Overview
A few observations should be made regarding the beta ratios.
● For inverters the primary, average, and maximum beta ratios are all the same.
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he power implied by using the maximum beta ratio is usually higher than the power implied by using the
average beta ratio, but in most cases the delay is smaller for the maximum beta ratio.
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he delay impact of varying the beta ratio tends to be soft, while the power impact is typically more
pronounced. This means that if a design wanted to reduce the power consumption at the price of lower
performance the maximum beta ratios can be removed in favor of an all average beta ratio library.
5.15 Drive Strengths
he drive strengths for all cells are based on the number of fingers on the output stage. The X1 drive strength
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has an output stage that has one p-transistor finger and one n-transistor finger. The output stage devices are
sized as large as possible while having only finger and maintaining the correct beta ratio. The X2 drive strength
has an output stage that has two p-transistor fingers and two n-transistor fingers. The output stage devices are
sized as large as possible while having two fingers and maintaining the correct beta ratio.
here are some beta ratios where the output stage is not sized as large as possible while having the
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corresponding numbers of fingers. For example, the X1P5 drive strength has an output stage that has two
p-transistor fingers and two n-transistor fingers, although the fingers are not full size.
6 LOGICAL EFFORT
It is important to be clear when talking about Logical Effort. Logical Effort (in capitals) refers to the technique for
sizing transistors based on the book by Sutherland, Sproull, and Harris. “Logical Effort” (in capitals and quotes)
refers to the book itself. Finally, logical effort (in lowercase) is the ability of a logic gate to produce an output
current, regardless of the transistor sizes.
his section explains how to determine the logical effort of the basic single-stage cells. This information is
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required before sizing any multi-stage cells. This section is not a substitute for learning the concepts explained
in the “Logical Effort” book by Sutherland, Sproull, and Harris. The logical effort of a cell is noted as “g” in the
“Logical Effort” book.
he logical effort for an inverter is 1, by definition. The logical effort for other basic single-stage cells is greater
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than 1. The smaller the logical effort, the better the cell is at producing output current.
For all standard cell libraries, a specific method of determining logical effort is used.
)
1 raw a schematic like Figure 6-1 below.
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2) Replace the “cut” block (circuit under test) with the cell of interest. See Figure 6-2 for examples.
3) Run a simulation to determine at what point the edge rate of “outinv” matches the edge rate of “outcut”.
4) Use the following equation to determine the logical effort of the circuit under test.
LE = “cut” transistor size / inverter transistor size
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Figure 61 Logical Effort Schematic
Figure 62 CUT (Circuit Under Test) Examples
t first glance it is not obvious what the purpose is of the circuit in Figure 6-1. The two “mult = 4” blocks are
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used to generate a fanout of four from the first two inverters. These blocks are drawn using the “imult” symbol in
the armPrimitives library. The voltage source in the bottom part of the figure is a voltage controlled voltage
source (E in SPICE). The voltage is controlled by the voltage of the wire “tap” in the top part of the figure. This
voltage source insures that the signal going into the “cut” block is the same as the one going into the third
inverter in the top part of the figure.
he three inverters are all sized the same using the beta ratio found in the Beta Ratio section of the document.
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The “load” capacitance is set to a value that gives approximately a fanout of four for the inverter chain.
If the circuit under test is a nand gate, size the p-channel transistors the same as the p-channel transistors of the
inverters. Sweep the n-channel transistor size of the nand gate until the falling edge rate of “outcut” matches the
falling edge rate of “outinv”.
If the circuit under test is a nor gate, size the n-channel transistors the same as the n-channel transistors of the
inverters. Sweep the p-channel transistor size of the nor gate until the rising edge rate of “outcut” matches the
rising edge rate of “outinv”.
setheequationforcalculatinglogicaleffort(LE=“cut”transistorsize/invertertransistorsize)tofindthelogical
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effort value for each single-stage cell. For example, assumetheinvertersaresized1500nm/1000nm. The
notation is p-channel transistor size / n-channel transistor size. The total transistor size is 2500 nm for the
inverters. TheNAND2n-channelsizesaredeterminedtobe1500nm. TheNAND2p-channelsizeissetto1500
nmtomatchtheinvertersize. Thetotaltransistorsizeis3000nmfortheNAND2. ThelogicaleffortforNAND2
would be 1.2 for this example (3000 nm / 2500 nm).
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It isnotobvioushowtodeterminethelogicaleffortforaoiandoaigatessincetheyareasymmetricstructures.
Forallstandardcelllibraries,weusethelogicaleffortsfornandandnorgatestocalculatethelogicaleffortsfor
theaoiandoaigates. Forexample,AOI21hasatwohighp-channeltransistorstacksimilartoaNOR2andaone
highandtwohighn-channeltransistorstackssimilartoaninverterandNAND2,respectively. SeeFigure7-1for
anAOI21schematic. WemultipliedthelogicaleffortofNOR2andthelogicaleffortofNAND2togetthelogical
effortforthetwohighstacks;wemultipliedthelogicaleffortofNOR2andthelogicaleffortofaninvertertoget
the logical effort for the twohighp-channelstackandtheonehighn-channelstack. Thenwetookthesetwo
products and averaged them to come up with the logical effort for the AOI21 cell.
7 SINGLE STAGE CELLS
his section describes how to design all of the single stage cells. It is assumed that the beta ratios have already
T
been found for each of the single stage cells using the methods described in the section titled “Transistor Sizing
Philosophy”. It is also assumed that the maximum single finger transistor sizes are known.
7.1 Flood-Filled Sizing
o size single-stage cells based on the flood-filled beta ratio, “X”, set the p-channel transistors to the maximum
T
p-channel finger size and set the n-channel transistors to the n-channel finger size. The number of fingers is
determined by the drive strength. The following subsections apply to the other beta ratios: “A”, “B”, “E”, and “M”.
7.2 Inverter Cell Sizing
he Base library contains inverters with two beta ratios: “M” and “B”. The “M” beta ratio inverters are the
T
general-use inverters while the “B” beta ratio inverters are used primarily for clock drivers.
or the single stage combinatorial cells, it is generally easiest to start with the “X1” drive strength and scale the
F
transistors for the other drive strengths. To size the INV_X1M cell, set the p-channel transistor to the maximum
single finger size. Then divide the p-channel transistor size by the inverter “M” beta ratio to get the n-channel
transistor size. Follow the same procedure to size the INV_X1B cell, except use the inverter “B” beta ratio to get
the n-channel transistor size. To size the INV_X1X flood-filled cell, set the p-channel transistor to the maximum
p-channel finger size and set the n-channel transistor to the maximum n-channel finger size.
he idea behind setting the p-channel transistor size to the maximum single finger size is to maximize the device
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size while maintaining the proper beta ratio. This concept is sometimes referred to as the “max-tuned” approach
because either the p-channel or n-channel transistor size is set to the maximum finger size. In order to get the
maximum device size for the inverters, the p-channel transistor is set to the maximum finger size. The critical
point is the ratio of single-finger maximum p-channel size to single-finger maximum n-channel size. If the beta
ratio is above this critical point, then set the p-channel size to the maximum single finger size and divide by the
beta ratio to get the n-channel size. If the beta ratio is below this critical point, then set the n-channel size to the
maximum single finger size and multiply by the beta ratio to get the p-channel size.
nce the “X1” drive strength inverters have been sized, it is simple to figure out the sizes for the remaining drive
O
strengths. Multiply the device sizes of the “X1” drive strength inverter by the drive strength to size. For example,
the INV_X2M cell has transistors that are double the size of the INV_X1M cell. The INV_X2P5B cell has
transistors that are 2.5 times larger than the size of the INV_X1B cell.
It is important to include wire length estimates for all cells so that timing simulations based on the schematics are
not optimistic.
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7.3 Other Single Stage Cell Sizing
he other single stage cells are sized using the procedure described in the previous subsection. These cells will
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be in some combination of “A”, “B”, “E”, “F”, “M”, “R”, and “X” beta ratios. For some AOI and OAI cells the
transistor sizes will vary within the cell due to the circuit topology.
7.3.1 NAND/NOR
AND cells (NAND2, NAND3, and NAND4) and NOR cells (NOR2 and NOR3) are sized using the procedure
N
described in the previous subsection. If the cells are flood-filled (“X”), the sizes are exactly the same as the
inverter sizes. For the other beta ratios, start with the “X1” drive strength cell. If the beta ratio is larger than the
critical ratio (the flood-filled ratio), set the p-channel transistor sizes to the maximum size single finger p-channel
size. Set the n-channel transistor sizes to the p-channel size divided by the beta ratio. If the beta ratio is smaller
than the critical ratio, set the n-channel transistor sizes to the maximum size single finger n-channel size. Set the
p-channel transistor sizes to the n-channel size multiplied by the beta ratio.
7.3.2 AOI
OI cells are more complicated to design because some of the cells have n-channel transistors that are not all
A
sized the same. The exception to this is the flood-filled ratio “X” because the sizes are the same as the inverter
sizes.
.3.2.1AOI21
7
Figure 7-1 is the schematic of an AOI21 cell.
Figure 71 AOI21 Schematic
or this cell, “Y” is pulled-up through either “A0 & B0” or “A1 & B0” (two high p-channel transistors). Size all of
F
the p-channel transistors the same as the p-channel transistors in NOR2. “Y” is pulled-down through either “B0”
or “A0 & A1” (a single n-channel transistor or two high n-channel transistors). Size “B0” the same as the
n-channel transistors in NOR2 and size “A0” and “A1” by multiplying the “B0” n-channel transistor size by the
inverter M beta ratio divided by the NAND2 M beta ratio. If the n-channel transistor size for the X1M cell is larger
than the maximum n-channel finger size, all of the transistors need to be downsized so that the n-channel
transistor size equals the maximum n-channel finger size. See Section 7.3.2.2 for an example of this downsizing.
ere is an example of how to size an AOI21_X1M cell. For this example, assume that the NOR2_X1M transistor
H
sizes are 0.7u/0.285u (beta ratio 2.456), the NAND2_X1M transistor sizes are 0.48u/0.58u (beta ratio 0.828), and
the INV_X1M transistor sizes are 0.7u/0.53u (beta ratio 1.32). Also assume that the maximum p-channel finger
size is 0.7u and the maximum n-channel finger size is 0.58u. All of the p-channel transistors in AOI21_X1M will
be 0.7u because that is the NOR2_X1M p-channel transistor size. The “B0” n-channel transistor in AOI21_X1M
will be 0.285u because that is the NOR2_X1M n-channel transistor size. The “A0” and “A1” n-channel transistors
in AOI21_X1M will be 0.455u, which is the “B0” n-channel transistor size times the inverter M beta ratio divided
by the NAND2 M beta ratio (0.285u * 1.32 / 0.828).
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.3.2.2AOI31
7
Figure 7-2 is the schematic of an AOI31 cell.
Figure 72 AOI31 Schematic
or this cell, “Y” is pulled-up through either “A0 & B0” or “A1 & B0” or “A2 & B0” (two high p-channel transistors).
F
Size all of the p-channel transistors the same as the p-channel transistors in NOR2. “Y” is pulled-down through
either “B0” or “A0 & A1 & A2” (a single n-channel transistor or three high n-channel transistors). Size “B0” the
same as the n-channel transistors in NOR2 and size “A0”, “A1”, and “A2” by multiplying the “B0” n-channel
transistor size by the inverter M beta ratio divided by the NAND3 M beta ratio. If the n-channel transistor size for
the AOI31_X1M cell is larger than the maximum n-channel finger size, all of the transistors in AOI31_X1M need to
be downsized so that the n-channel transistor size equals the maximum n-channel finger size.
ere is an example of how to size an AOI31_X1M cell. For this example, assume that the NOR2_X1M transistor
H
sizes are 0.7u/0.285u (beta ratio 2.456), the NAND3_X1M transistor sizes are 0.36u/0.58u (beta ratio 0.62), and
the INV_X1M transistor sizes are 0.7u/0.53u (beta ratio 1.32). Also assume that the maximum p-channel finger
size is 0.7u and the maximum n-channel finger size is 0.58u. All of the p-channel transistors in AOI31_X1M will
be 0.7u because that is the NOR2_X1M p-channel transistor size. The “B0” n-channel transistor size in
AOI31_X1M will be 0.285u because that is the NOR2_X1M n-channel transistor size. The “A0”, “A1”, and “A2”
n-channel transistors in AOI31_X1M will be 0.605u, which is the “B0” n-channel transistor size times the inverter
M beta ratio divided by the nand3 M beta ratio (0.285u * 1.32 / 0.62). However, notice that these transistor sizes
are larger than the maximum n-channel finger size. All of the transistors must be scaled down by 0.605/0.58 (the
oversized transistor size divided by the maximum finger size).
.3.2.3AOI22
7
Figure 7-3 is the schematic of an AOI22 cell.
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Figure 73 AOI22 Schematic
or this cell, “Y” is pulled-up through either “A0 & B0” or “A1 & B0” or “A0 & B1” or “A1 & B1” (two high
F
p-channel transistors). Size all of the p-channel transistors the same as the p-channel transistors in NOR2. “Y”
is pulled-down through either “A0 & A1” or “B0 & B1” (two high n-channel transistors). Size all of the n-channel
transistors the same as “A0” and “A1” in AOI21. If the n-channel transistor size for the AOI22_X1M cell is larger
than the maximum n-channel finger size, all of the transistors need to be downsized so that the n-channel
transistor size equals the maximum n-channel finger size. See Section 7.3.2.2 for an example of this downsizing.
.3.2.4AOI32
7
Figure 7-4 is the schematic of an AOI32 cell.
Figure 74 AOI32 Schematic
or this cell, “Y” is pulled-up through either “A0 & B0” or “A0 & B1” or “A1 & B0” or “A1 & B1” or “A2 & B0” or “A2
F
& B1” (two high p-channel transistors). Size all of the p-channel transistors the same as the p-channel transistors
in NOR2. “Y” is pulled-down through either “B0 & B1” or “A0 & A1 & A2” (two high n-channel transistors or three
high n-channel transistors). Size “B0” and “B1” the same as “A0” and “A1” in AOI21 and size “A0”, “A1”, and
“A2” the same as “A0”, “A1”, and “A2” as AOI31. If the n-channel transistor size for the AOI32_X1M cell is larger
than the maximum n-channel finger size, all of the transistors need to be downsized so that the n-channel
transistor size equals the maximum n-channel finger size. See Section 7.3.2.2 for an example of this downsizing.
.3.2.5AOI211
7
Figure 7-5 is the schematic of an AOI211 cell.
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Figure 75 AOI211 Schematic
or this cell, “Y” is pulled-up through either “A0 & B0 & C0” or “A1 & B0 & C0” (three high p-channel transistors).
F
Size all of the p-channel transistors the same as the p-channel transistors in NOR3. “Y” is pulled-down through
either “C0” or “B0” or “A0 & A1” (a single n-channel transistor or two high n-channel transistors). Size “C0” and
“B0” the same as the n-channel transistors in NOR2 and size “A0” and “A1” the same as “A0” and “A1” in AOI21.
If the n-channel transistor size for the AOI211_X1M cell is larger than the maximum n-channel finger size, all of
the transistors need to be downsized so that the n-channel transistor size equals the maximum n-channel finger
size. See Section 7.3.2.2 for an example of this downsizing.
.3.2.6AOI221
7
Figure 7-6 is the schematic of an AOI221 cell.
Figure 76 AOI221 Schematic
or this cell, “Y” is pulled-up through either “A0 & B0 & C0” or “A0 & B1 & C0” or “A1 & B0 & C0” or “A1 & B1 &
F
C0” (three high p-channel transistors). Size all of the p-channel transistors the same as the p-channel transistors
in NOR3. “Y” is pulled-down through either “C0” or “B0 & B1” or “A0 & A1” (a single n-channel transistor or two
high n-channel transistors). Size “C0” the same as the n-channel transistor in NOR2 and size “B0”, “B1”, “A0”,
and “A1” the same as “A0” and “A1” in AOI21. If the n-channel transistor size for the AOI221_X1M cell is larger
than the maximum n-channel finger size, all of the transistors need to be downsized so that the n-channel
transistor size equals the maximum n-channel finger size. See Section 7.3.2.2 for an example of this downsizing.
.3.2.7AOI222
7
Figure 7-7 is the schematic of an AOI222 cell.
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Figure 77 AOI222 Schematic
or this cell, “Y” is pulled-up through either “A0 & B0 & C0” or “A0 & B0 & C1” or “A0 & B1 & C0” or “A0 & B1 &
F
C1” or “A1 & B0 & C0” or “A1 & B0 & C1” or “A1 & B1 & C0” or “A1 & B1 & C1” (three high p-channel transistors).
Size all of the p-channel transistors the same as the p-channel transistors in NOR3. “Y” is pulled-down through
either “A0 & A1” or “B0 & B1” or “C0 & C1” (two high n-channel transistors). Size all of the n-channel transistors
the same as “A0” and “A1” in AOI21. If the n-channel transistor size for the AOI222_X1M cell is larger than the
maximum n-channel finger size, all of the transistors need to be downsized so that the n-channel transistor size
equals the maximum n-channel finger size. See Section 7.3.2.2 for an example of this downsizing.
7.3.3 OAI
or the OAI cells, follow the procedure for sizing AOI cells. The n-channel transistor sizes will be the same within
F
a cell. The p-channel transistor sizes will vary within a cell depending on the size of the transistor stack.
.3.3.1OAI211
7
Figure 7-8 is the schematic of an OAI211 cell.
Figure 78 OAI211 Schematic
or this cell, “Y” is pulled-up through either “C0” or “B0” or “A0 & A1” (a single p-channel transistor or two high
F
p-channel transistors). Size “A0” and “A1” like the p-channel transistors in NOR2. Size “C0” and “B0” by
multiplying the “A0” or “A1” p-channel transistor size by the inverter M beta ratio divided by the NOR2 M beta
ratio. “Y” is pulled-down through either “A0 & B0 & C0” or “A1 & B0 & C0” (three high n-channel transistors).
Size all of the n-channel transistors the same as the n-channel transistors “A0”, “A1”, and “A2” in AOI31.
.3.3.2OAI21
7
Figure 7-9 is the schematic of an OAI21 cell.
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Figure 79 OAI21 Schematic
or this cell, “Y” is pulled-up through either “B0” or “A0 & A1” (a single p-channel transistor or two high
F
p-channel transistors). Size “B0” the same as the p-channel transistors “C0” and “B0” in OAI211. Size “A0” and
“A1” like the p-channel transistors in NOR2. “Y” is pulled-down through either “A0 & B0” or “A1 & B0” (two high
n-channel transistors). Size all of the n-channel transistors the same as the n-channel transistors in AOI22.
.3.3.3OAI221
7
Figure 7-10 is the schematic of an OAI221 cell.
Figure 710 OAI221 Schematic
or this cell, “Y” is pulled-up through either “C0” or “B0 & B1” or “A0 & A1” (a single p-channel transistor or two
F
high p-channel transistors). Size “C0” the same as the p-channel transistors “C0” and “B0” in OAI211. Size the
other p-channel transistors like the p-channel transistors in NOR2. “Y” is pulled-down through either “A0 & B0 &
C0” or “A1 & B0 & C0” or “A0 & B1 & C0” or “A1 & B1 & C0” (three high n-channel transistors). Size all of the
n-channel transistors the same as the n-channel transistors “A0”, “A1”, and “A2” in AOI31.
.3.3.4OAI22
7
Figure 7-11 is the schematic of an OAI22 cell.
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Figure 711 OAI22 Schematic
or this cell, “Y” is pulled-up through either “A0 & A1” or “B0 & B1” (two high p-channel transistors). Size all of
F
the p-channel transistors like the p-channel transistors in NOR2. “Y” is pulled-down through either “A0 & B0” or
“A0 & B1” or “A1 & B0” or “A1 & B1” (two high n-channel transistors). Size all of the n-channel transistors the
same as the n-channel transistors in AOI22.
.3.3.5OAI222
7
Figure 7-12 is the schematic of an OAI222 cell.
Figure 712 OAI222 Schematic
or this cell, “Y” is pulled-up through either “A0 & A1” or “B0 & B1” or “C0 & C1” (two high p-channel transistors).
F
Size all of the p-channel transistors like the p-channel transistors in NOR2. “Y” is pulled-down through either “A0
& B0 & C0” or “A0 & B0 & C1” or “A0 & B1 & C0” or “A0 & B1 & C1” or “A1 & B0 & C0” or “A1 & B0 & C1” or “A1
& B1 & C0” or “A1 & B1 & C1” (three high n-channel transistors). Size all of the n-channel transistors the same as
the n-channel transistors “A0”, “A1”, and “A2” in AOI31.
.3.3.6OAI31
7
Figure 7-13 is the schematic of an OAI31 cell.
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Figure 713 OAI31 Schematic
or this cell, “Y” is pulled-up through either “B0” or “A0 & A1 & A2” (a single p-channel transistor or two high
F
p-channel transistors). Size “A0”, “A1”, and “A2” like the p-channel transistors in AOI222. “Y” is pulled-down
through either “A0 & B0”, “A1 & B0”, “A2 & B0” (two high n-channel transistors). Size all of the n-channel
transistors the same as the n-channel transistors in AOI222. Size the p-channel transistor “B0” using the beta
ratio of NAND2.
7.3.4 Compound Structures
he Base library contains two compound cell topologies: AO21A1AI2 and OA21A1OI2. These compound cells
T
are single-stage cells, but they are more complex than AOI or OAI structures.
.3.4.1AO21A1AI2
7
Figure 7-14 is the schematic of an AO21A1AI2 cell.
Figure 714 AO21A1AI2 Schematic
or this cell, “Y” is pulled-up through either “C0” or “A0 & B0” or “A1 & B0” (a single p-channel transistor or two
F
high p-channel transistors). Size “C0” the same as the p-channel transistors “C0” and “B0” in OAI211. Size the
other p-channel transistors like the p-channel transistors in NOR2. “Y” is pulled-down through either “B0 & C0”
or “A0 & A1 & C0” (two high n-channel transistors or three high n-channel transistors). Size all of the n-channel
transistors the same as the n-channel transistors “A0”, “A1”, and “A2” in AOI31.
.3.4.2OA21A1OI2
7
Figure 7-15 is the schematic of an OA21A1OI2 cell.
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Figure 715 OA21A1OI2 Schematic
or this cell, “Y” is pulled-up through either “B0 & C0” or “A0 & A1 & C0” (two high p-channel transistors or three
F
high p-channel transistors). Size all of the p-channel transistors the same as the p-channel transistors in NOR3.
“Y” is pulled-down through either “C0” or “A0 & B0” or “A1 & B0” (a single p-channel transistor or two high
n-channel transistors). Size “A0”, “A1”, and “B0” the same as the n-channel transistors in AOI22. Size “C0” the
same as the n-channel transistors in NOR2.
7.4 Single Stage Cell Sizing Summary
The following is a brief summary of how to size single stage cells.
) D
1 etermine which beta ratios and drive strengths will be included for each cell in the library.
2) Determine the value of each beta ratio for each cell type.
3) Determine if each beta ratio is larger or smaller than the critical ratio (maximum size single finger
p-channel divided by maximum size single finger n-channel).
4) Determine the “X1” drive strength size - If the beta ratio is larger than the critical ratio, set the p-channel
size to the maximum size single finger p-channel size. Set the n-channel size to the p-channel size
divided by the beta ratio. If the beta ratio is smaller than the critical ratio, set the n-channel size to the
maximum size single finger n-channel size. Set the p-channel size to the n-channel size multiplied by the
beta ratio.
5) Determine the other drive strength sizes – Multiply the “X1” drive strength sizes by the drive strength
value.
6) Determine the wire lengths and add them to the schematic.
8 TWO STAGE CELLS
his section describes how to design all of the two stage cells. These cells are more difficult to size than the
T
single stage cells because the size of the input stage requires good knowledge of logical effort and wire
parasitics.
8.1 Two Stage Sizing Strategy
Here is a procedure for sizing two stage cells.
1) Draw the un-sized cell schematic and stick diagram.
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2) S ize the output stage as though it were a single stage cell. For example, the output stage of the
NAND2B_X4M cell is sized the same as the NAND2_X4M cell. However, the output stage of the
AO1B2_X4M cell is sized the same as the NAND2_X4A cell.
3) Using the stick diagram, determine the wire lengths and add the wire lengths to the schematic.
4) Determine the total transistor size of the first stage using a stage effort of four. To simplify this
calculation, it is best to convert the wire length to an equivalent gate width. Add this equivalent gate
width to the width of the output stage to determine Cout.
5) Run doee simulations to determine the proper beta ratio for the input stage.
6) Size the input stage based on the results of step 5.
8.1.1 AND
or all AND gates, the size of the inverter is determined by the drive strength and beta ratio type. The wire
F
lengths are found using stick diagrams. The NAND gate size is determined using Logical Effort and simulation.
.1.1.1AND2
8
Figure 8-1 is the schematic of an AND2 cell. The capacitances shown in the figure represent the wire
capacitance for “ny” and “Y”. The capacitances for “A” and “B” need to be calculated and added to the
schematic, but are not shown in the figure for better readability.
Figure 81 AND2 Schematic
Figure 8-2 is the stick diagram of a single fingered AND2 cell.
Figure 82 AND2 Stick Diagram
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he output stage of an AND2 cell is an inverter. Size the inverter just like a single-stage inverter. For example, an
T
AND2_X1X cell has an inverter with the same sizes as INV_X1X. Now that the inverter has been sized, use the
stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the NAND2 gate. The total transistor size of the NAND2 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of NAND2 are known. At this point, doee
simulations are needed to determine the beta ratio for the NAND2 depending on the beta ratio type for the cell.
.1.1.2AND3
8
AND3 cells are sized like AND2 cells except that the input stage is a NAND3 instead of a NAND2.
.1.1.3AND4
8
AND4 cells are sized like AND2 cells except that the input stage is a NAND4 instead of a NAND2.
8.1.2 NAND (Two-Stage)
he Base library contains NAND cells that have one or more inverted inputs. These cells are primarily area
T
savers because two cells (INV and NAND) are contained in one.
.1.2.1NAND2B
8
Figure 8-3 is the schematic of a NAND2B cell. The capacitances shown in the figure represent the wire
capacitance for “a” and “Y”. The capacitances for “AN” and “B” need to be calculated and added to the
schematic, but are not shown in the figure for better readability.
Figure 83 NAND2B Schematic
he output stage of a NAND2B cell is a NAND2. Size the NAND2 just like a single-stage NAND2. For example, a
T
NAND2B_X1X cell has a NAND2 with the same sizes as NAND2_X1X. Now that the NAND2 has been sized, use
the stick diagram to determine the lengths of the input wires, the “a” wire, and the output wire.
he next step is to size the inverter. The total transistor size of the inverter can be found using Logical Effort,
T
since the NAND2 size, the “a” wire length, and the logical effort of INV are known. The logical effort of an inverter
is always 1. At this point, doee simulations are needed to determine the beta ratio for the inverter depending on
the beta ratio type for the cell.
.1.2.2NAND2XB
8
The NAND2XB cell is similar to the NAND2B cell except that the “B” input is inverted instead of “A”. Use the
same procedure as NAND2B to size this cell.
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.1.2.3NAND3B
8
The NAND3B cell is similar to the NAND2B cell except that the input stage is a NAND3. Use the same procedure
as NAND2B to size this cell.
.1.2.4NAND3XXB
8
The NAND3XXB cell is similar to the NAND3B cell except that the “C” input is inverted instead of “A”. Use the
same procedure as NAND3B to size this cell.
.1.2.5NAND4B
8
The NAND4B cell is similar to the NAND2B cell except that the input stage is a NAND4. Use the same procedure
as NAND2B to size this cell.
.1.2.6NAND4XXXB
8
The NAND4XXXB cell is similar to the NAND4B cell except that the “D” input is inverted instead of “A”. Use the
same procedure as NAND4B to size this cell.
8.1.3 AO
.1.3.1AO21
8
The AO21 cell is an AOI21 driving an inverter as shown in Figure 8-4.
Figure 84 AO21 Schematic
he output stage of an AO21 cell is an inverter. Size the inverter just like a single-stage inverter. For example, an
T
AO21_X1X cell has an inverter with the same sizes as INV_X1X. Now that the inverter has been sized, use the
stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the AOI21 gate. The total transistor size of the AOI21 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of AOI21 are known. At this point, doee
simulations are needed to determine the sizes for the AOI21 depending on the beta ratio type for the cell.
he following is an example of how to size an AO21_X1M cell. Assume that an INV_X1M cell is 0.7 µm / 0.5 µm.
T
For this example, the logical effort of an AOI21 cell is two, the length of wire “ny” is 2 µm, the length of wire “Y” is
1.5 µm, and the length of the input wires is 0.5 µm. Figure 8-5 shows the AO21_X1M cell for this example. The
capacitance of the input and output wires is not shown in the figures for readability, except for the final
schematic, Figure 8-8.
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Figure 85 AO21_X1M Example
t this point, it is best to convert the length of wire “ny” into an equivalent gate length. In other words, we need
A
to find what amount of gate length has the same capacitance as 2 µm of Metal 1 wire. This value needs to be
calculated for each process. For this example, we will use a value which is 5 nm of Metal 1 wire is equivalent to 1
nm of gate length. So the 2 µm wire becomes 0.4 µm of gate. Figure 8-6 shows the output inverter and “ny”
wire converted into a single capacitance value of 1.6 µm of transistor length (0.7 µm + 0.5 µm + 0.4 µm).
Figure 86 AO21_X1M Example with Single Load Value
ow we can determine the device size of the AOI21 using a stage effort of four. Using Logical Effort, Cin = g *
N
Cout / f. From this example, the logical effort (g) is two, Cout is 1.6 µm, and the stage effort (f) is four. So Cin = 2
* 1.6 µm / 4 = 0.8 µm.
e can apply the sizing technique from the AOI21 Section to this cell. All of the p-channel transistors have the
W
same size. Also the n-channel transistors “A0” and “A1” have the same size, while “B0” is smaller. The size of
any of the p-channel transistors plus either n-channel transistor “A0” or “A1” equals 0.8 µm (Cin) for this example.
We would need to run a simulation to determine how to best divide up the 0.8 µm of transistor width. We want to
minimize the maximum delay since we are sizing an AO21_X1M cell. We would need to be sure to keep “B0” at
ground during the simulation because we are not interested in the timing through the n-channel transistor “B0” at
this point. We will assume that the result is that the p-channel transistors are 0.5 µm and the n-channel
transistors “A0” and “A1” are 0.3 µm. Figure 8-7 shows the example schematic at this point.
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Figure 87 AO21_X1M Example Partially Sized
he only transistor left to size is the n-channel “B0” transistor. We would need to run a similar simulation as
T
before to determine this transistor size. In this simulation, we would set “A0” to VDD and “A1” to VSS, or vice
versa, so that “ny” does not get pulled down through “A0” and “A1”. We need to sweep the size of this “B0”
transistor until the timing is the same as the timing we found in the previous simulation. This way we are
minimizing the maximum delay. For this example, we will assume that the simulation shows that when n-channel
“B0” transistor size is 0.18 µm the delay is minimized. Figure 8-8 shows the completed schematic including the
input and output capacitances which were not shown previously.
Figure 88 AO21_X1M Example Completed
.1.3.2AO1B2
8
The AO1B2 cell is a NAND2 driving a NAND2 as shown in Figure 8-9.
Figure 89 AO1B2 Schematic
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he output stage of an AO1B2 cell is a NAND2. Size the output stage NAND2 just like a single-stage NAND2
T
with an ‘A’ beta ratio. For example, an AO1B2_X6M cell has an output stage NAND2 with the same sizes as
NAND2_X6A. Now that the output stage NAND2 has been sized, use the stick diagram to determine the lengths
of the input wires, the “b0b1” wire, and the output wire.
he next step is to size the input stage NAND2. The total transistor size of the input stage NAND2 can be found
T
using Logical Effort, since the output stage NAND2 size, the “b0b1” wire length, and the logical effort of NAND2
are known. Use the NAND2 ‘A’ beta ratio to size the input stage NAND2.
.1.3.3AO21B
8
The AO21B cell is a NAND2 driving a NAND2 as shown in Figure 8-10.
Figure 810 AO21B Schematic
Size the AO21B cell using the same procedure as the AO1B2 cell.
.1.3.4AO22
8
The AO22 cell is an AOI22 driving an inverter as shown in Figure 8-11.
Figure 811 AO22 Schematic
he output stage of an AO22 cell is an inverter. Size the inverter just like a single-stage inverter. For example, an
T
AO22_X1M cell has an inverter with the same sizes as INV_X1M. Now that the inverter has been sized, use the
stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the AOI22 gate. The total transistor size of the AOI22 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of AOI22 are known. At this point, doee
simulations are needed to determine the sizes for the AOI22 depending on the beta ratio type for the cell.
.1.3.5AOI2XB1
8
The AOI2XB1 cell is an inverter driving an AOI21 as shown in Figure 8-12.
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Figure 812 AOI2XB1 Schematic
he output stage of an AOI2XB1 cell is an AOI21. Size the AOI21 just like a single-stage AOI21. For example, an
T
AOI2XB1_X1M cell has an AOI21 with the same sizes as AOI21_X1M. Now that the AOI21 has been sized, use
the stick diagram to determine the lengths of the input wires, the “a1” wire, and the output wire.
he next step is to size the inverter. The total transistor size of the inverter can be found using Logical Effort,
T
since the AOI21 size, the “a1” wire length, and the logical effort of an inverter are known. At this point, doee
simulations are needed to determine the beta ratio for the inverter depending on the beta ratio type for the cell.
8.1.3.6AOI21B
The AOI21B cell is an inverter driving an AOI21 as shown in Figure 8-13.
Figure 813 AOI21B Schematic
Size the AOI21B cell using the same procedure as the AOI2XB1 cell.
8.1.4 OA
.1.4.1OA211
8
The OA211 cell is an OAI211 cell driving an inverter as shown in Figure 8-14.
Figure 814 OA211 Schematic
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he output stage of an OA211 cell is an inverter. Size the inverter just like a single-stage inverter. For example,
T
an OA211_X1M cell has an inverter with the same sizes as INV_X1M. Now that the inverter has been sized, use
the stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the OAI211 gate. The total transistor size of the OAI211 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of an OAI211 are known. At this point,
doee simulations are needed to determine the beta ratio for the OAI211 depending on the beta ratio type for the
cell. Like the AO21 cell, the “A0” and “A1” p-channel transistor sizes are found with one simulation and the “B0”
and “C0” p-channel transistor sizes are found with another simulation.
.1.4.2OA21
8
The OA21 cell is an OAI21 cell driving an inverter as shown in Figure 8-15.
Figure 815 OA21 Schematic
he output stage of an OA21 cell is an inverter. Size the inverter just like a single-stage inverter. For example, an
T
OA21_X1M cell has an inverter with the same sizes as INV_X1M. Now that the inverter has been sized, use the
stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the OAI21 gate. The total transistor size of the OAI21 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of an OAI21 are known. At this point,
doee simulations are needed to determine the beta ratio for the OAI21 depending on the beta ratio type for the
cell. Like the OA211 cell, the “A0” and “A1 p-channel transistor sizes are found with one simulation and the “B0”
p-channel transistor size is found with another simulation.
.1.4.3OA22
8
The OA22 cell is an OAI22 cell driving an inverter as shown in Figure 8-16.
Figure 816 OA22 Schematic
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he output stage of an OA22 cell is an inverter. Size the inverter just like a single-stage inverter. For example, an
T
OA22_X1M cell has an inverter with the same sizes as INV_X1M. Now that the inverter has been sized, use the
stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the OAI22 gate. The total transistor size of the OAI22 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of an OAI22 are known. At this point,
simulations are needed to determine the beta ratio for the OAI22 depending on the beta ratio type for the cell.
.1.4.4OAI21B
8
The OAI21B is an inverter driving an OAI21B cell as shown in Figure 8-17.
Figure 817 OAI21B Schematic
he output stage of an OAI21B cell is an OAI21 gate. Size the OAI21 gate just like a single-stage OAI21 gate.
T
For example, an OAI21B_X4M cell has an OAI21 gate with the same sizes as OAI21_X4M. Now that the OAI21
gate has been sized, use the stick diagram to determine the lengths of the input wires, the “b0” wire, and the
output wire.
he next step is to size the inverter. The total transistor size of the inverter can be found using Logical Effort,
T
since the OAI21 size, the “b0” wire length, and the logical effort of an inverter are known. At this point, doee
simulations are needed to determine the beta ratio for the inverter depending on the beta ratio type for the cell.
.1.4.5OAI2XB1
8
The OAI2XB1 cell is an inverter driving an OAI21 cell as shown in Figure 8-18.
Figure 818 OAI2XB1 Schematic
Size the OAI2XB1 cell using the same procedure as the OAI21B cell.
8.1.5 OR
The OR2 and OR3 cells have NOR – INV structures. The OR4 and OR6 cells have NOR – NAND structures.
.1.5.1OR2
8
The OR2 cell is a NOR2 cell driving an inverter as shown in Figure 8-19.
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Figure 819 OR2 Schematic
he output stage of an OR2 cell is an inverter. Size the inverter just like a single-stage inverter. For example, an
T
OR2_X1M cell has an inverter with the same sizes as INV_X1M. Now that the inverter has been sized, use the
stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the NOR2 gate. The total transistor size of the NOR2 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of NOR2 are known. At this point, doee
simulations are needed to determine the beta ratio for the NOR2 depending on the beta ratio type for the cell.
.1.5.2OR3
8
The OR3 cell is a NOR3 cell driving an inverter as shown in Figure 8-20.
Figure 820 OR3 Schematic
he output stage of an OR3 cell is an inverter. Size the inverter just like a single-stage inverter. For example, an
T
OR3_X1X cell has an inverter with the same sizes as INV_X1X. Now that the inverter has been sized, use the
stick diagram to determine the lengths of the input wires, the “ny” wire, and the output wire.
he next step is to size the NOR3 gate. The total transistor size of the NOR3 gate can be found using Logical
T
Effort, since the inverter size, the “ny” wire length, and the logical effort of NOR3 are known. At this point, doee
simulations are needed to determine the beta ratio for the NOR3 depending on the beta ratio type for the cell.
.1.5.3OR4
8
The OR4 cell is a NOR2 cell driving a NAND2 cell as shown in Figure 8-21.
Figure 821 OR4 Schematic
he output stage of an OR4 cell is a NAND2. Size the NAND2 just like a single-stage NAND2. For example, an
T
OR4_X4M cell has a NAND2 with the same sizes as NAND2_X4M. Now that the NAND2 gate has been sized,
use the stick diagram to determine the lengths of the input wires, the “ab” wire, the “cd” wire, and the output
wire.
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he next step is to size the NOR2 gates. The total transistor size of the top NOR2 gate can be found using
T
Logical Effort, since the inverter size, the “ab” wire length, and the logical effort of NOR2 are known. The total
transistor size of the bottom NOR2 gate can be found using Logical Effort, since the inverter size, the “cd” wire
length, and the logical effort of NOR2 are known. At this point, doee simulations are needed to determine the
beta ratio for the NOR2 gates depending on the beta ratio type for the cell.
.1.5.4OR6
8
The OR6 cell is a NOR3 cell driving a NAND2 cell as shown in Figure 8-22.
Figure 822 OR6 Schematic
he output stage of an OR6 cell is a NAND2. Size the NAND2 just like a single-stage NAND2. For example, an
T
OR6_X2M cell has a NAND2 with the same sizes as NAND2_X2M. Now that the NAND2 gate has been sized,
use the stick diagram to determine the lengths of the input wires, the “abc” wire, the “def” wire, and the output
wire.
he next step is to size the NOR3 gates. The total transistor size of the top NOR3 gate can be found using
T
Logical Effort, since the inverter size, the “abc” wire length, and the logical effort of NOR3 are known. The total
transistor size of the bottom NOR3 gate can be found using Logical Effort, since the inverter size, the “def” wire
length, and the logical effort of NOR3 are known. At this point, doee simulations are needed to determine the
beta ratio for the NOR3 gates depending on the beta ratio type for the cell.
8.1.6 NOR (Two-Stage)
.1.6.1NOR2B
8
The NOR2B cell is an inverter driving a NOR2 cell as shown in Figure 8-23.
Figure 823 NOR2B Schematic
he output stage of a NOR2B cell is a NOR2. Size the NOR2 just like a single-stage NOR2. For example, a
T
NOR2B_X1M cell has a NOR2 with the same sizes as NOR2_X1M. Now that the NOR2 has been sized, use the
stick diagram to determine the lengths of the input wires, the “a” wire, and the output wire.
he next step is to size the inverter. The total transistor size of the inverter can be found using Logical Effort,
T
since the NOR2 size, the “a” wire length, and the logical effort of inverter are known. The logical effort of an
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inverter is always 1. At this point, doee simulations are needed to determine the beta ratio for the inverter
depending on the beta ratio type for the cell.
.1.6.2NOR2XB
8
The NOR2XB cell is an inverter driving a NOR2 cell as shown in Figure 8-24.
Figure 824 NOR2XB Schematic
he NOR2XB cell is similar to the NOR2B cell except that the “B” input is inverted instead of “A”. Use the same
T
procedure as NOR2B to size this cell.
8.1.7 BUF
his section covers ‘BUF’, ‘BUFH’, and ‘DLY2’ cells. The ‘BUFZ’ and ‘DLY4’ cells are covered in a later section.
T
The number after the ‘DLY’ refers to the number of stages of inverters or tri-state inverters in the cell.
.1.7.1BUF
8
The BUF cell is an inverter driving another inverter as shown in Figure 8-25.
Figure 825 BUF Schematic
he output stage of a BUF cell is an inverter. Size the output inverter just like a single-stage inverter. For
T
example, a BUF_X1M cell has an output inverter with the same sizes as INV_X1M. Now that the output inverter
has been sized, use the stick diagram to determine the lengths of the input wires, the “ny” wire, and the output
wire.
he next step is to size the input inverter. The total transistor size of the first inverter can be found using Logical
T
Effort, since the output inverter size, the “ny” wire length, and the logical effort of inverter are known. Use a
stage effort of four to calculate the total transistor size of the first inverter. The logical effort of an inverter is
always 1. At this point, doee simulations are needed to determine the beta ratio for the first inverter depending
on the beta ratio type for the cell.
.1.7.2BUFH
8
The BUFH cell is an inverter driving another inverter as shown in Figure 8-26.
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Figure 826 BUFH Schematic
The BUFH cell is similar to the BUF cell except that the input inverter is sized using a stage effort of two.
.1.7.3DLY2
8
The DLY2 cell is a tri-state inverter driving an inverter with transistors used as capacitors as shown in Figure
8-27. The transistors used as capacitors are used to add extra delay to the cell.
Figure 827 DLY2 Schematic
he output stage of a DLY2 cell is an inverter. Size the output inverter just like a single-stage inverter. For
T
example, a DLY2_X1M cell has an output inverter with the same sizes as INV_X1M. Now that the output inverter
has been sized, use the stick diagram to determine the lengths of the input wires, the “ny” wire, and the output
wire.
he next step is to size the tri-state inverter. The total transistor size of the tri-state inverter can be found using
T
Logical Effort, since the output inverter size, the “ny” wire length, and the logical effort of a tri-state inverter are
known. Ignore the transistors used as capacitors when sizing the tri-state inverter. At this point, doee
simulations are needed to determine the beta ratio for the first inverter depending on the beta ratio type for the
cell, with the two transistors used as capacitors set to zero width. Once the tri-state inverter has been sized, set
the p-channel transistor used as a capacitor to the size of the p-channel transistors of the tri-state inverter. Run
simulations to determine the size of the n-channel transistor used as a capacitor so that the timing of the cell
matches the beta ratio type.
he layout area of this cell should match the layout area of the equivalent buffer. For instance, a DLY2_0P5X cell
T
should have the same area as a BUF_X0P5X cell.
9 ICG (INTEGRATED CLOCK GATES)
here are three basic types of ICG cells in the Base library: FRICG, PREICG, and POSTICG. The timing from CK
T
to ECK should be equal for all three types for the same drive strength.
9.1 FRICG
his section describes how to design FRICG cells. These cells should be sized before the other integrated clock
T
gate cells.
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9.1.1 Cell Usage
FRICG cells are free running cells, which means that these cells do not stop the clock from toggling.
9.1.2 Cell Structure
Figure 9-1 below shows the schematic of an FRICG cell.
Figure 91 FRICG Schematic
9.1.3 Cell Sizing
There are a few things to keep in mind when sizing this cell.
● S
ince this cell is designed using a ‘B’ beta ratio, the rise and fall delay of ‘CK’ to ‘ECK’ needs to be
balanced.
● S
ince this cell has clock signals, it is important to keep the clock transistors as small as possible while
maintaining performance.
● S
ince the ‘hi’ input to the p-channel transistor of the NAND2 gate of the FRICG is always at a logic 1
voltage level, this transistor should be made as small as possible while meeting the leakage guidelines.
hen sizing any multi-stage cell, it is best to start with the output device. In this case, the output inverter is
W
sized the same as the ‘B’ beta ratio inverter of the same drive strength. For instance, the FRICG_X11B cell has
an output inverter that is sized the same as the INV_X11B cell.
ince power and timing are the important factors for this cell, the remaining transistors need to be sized such
S
that the power – delay product is minimized. Using a stage effort of five results in a small power – delay product.
fter the output inverter has been sized, the NAND2 device needs to be sized. The NAND2 cell should have the
A
same beta ratio as the ‘B’ beta ratio NAND2 cells. The only exception is the p-channel transistor that is driven by
net ‘hi’. This transistor is kept small as mentioned in the “things to keep in mind” above. As a general rule, this
transistor is sized one tenth as large as the other p-channel transistor of the NAND2 gate. When applying the
stage effort to come up with the NAND2 transistor sizes, remember to include the wire capacitance of net ‘neck’.
fter the NAND2 devices have been sized, the three remaining transistors need to be sized. The n-channel
A
transistor is sized as the minimum non-dog boned transistor size. The p-channel transistor on the right is sized
by multiplying the n-channel transistor size by the inverter ‘M’ beta ratio. The p-channel transistor on the left
varies depending on the beta ratio. For the largest drive strength FRICG cell (FRICG_X16B), this transistor is
sized the same as the p-channel transistor in INV_X1M (the largest single-finger p-channel transistor). Divide the
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-channel NAND2 gate size by the size of this transistor. Use this ratio when sizing this transistor of other FRICG
n
cells.
9.2 PREICG
This section describes how to design PREICG cells.
9.2.1 Cell Usage
REICG cells, like POSTICG cells, are used to conserve clock power. These cells stop the clock from toggling in
P
the flops that they drive. Since clocks toggle twice a cycle, it is important to conserve clock power whenever
possible.
9.2.2 Cell Structure
Figure 9-2 below shows the schematic of a PREICG cell.
Figure 9-2 PREICG Schematic
9.2.3 Cell Sizing
There are a few things to keep in mind when sizing this cell.
● S
ince this cell is designed using a ‘B’ beta ratio, the rise and fall delay of ‘CK’ to ‘ECK’ needs to be
balanced. However, the ‘E’ to ‘m’ path is sized using the ‘M’ beta ratio.
● S
ince this cell has clock signals, it is important to keep the clock transistors as small as possible while
maintaining performance.
● S
ince the ‘m’ input to the p-channel transistor of the NAND2 gate of the PREICG is used only as a
keeper and not to drive the output, this transistor should be made as small as possible while meeting the
leakage guidelines.
● Since the tri-state inverter is used only as a keeper, this device should be kept to minimum size.
he NAND2 and output inverter are sized using the same sizes as the FRICG cell. This sizing method ensures
T
that all of the different ICG topologies have the same ‘CK’ to ‘ECK’ timing.
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he inverter that drives the net ‘m’ needs to be sized using the same stage effort as the NAND2 – output inverter
T
stage. Use the ‘M’ beta ratio as a starting point for the beta ratio. The beta ratio will need to be adjusted later,
so that the ‘E’ to ‘m’ path has an ‘M’ beta ratio. The tri-state inverter is sized using minimum devices.
henever there is a gate driving a transmission gate, consider the gate and transmission gate as one device for
W
figuring out the logical effort. In the PREICG, there is a NOR2 driving a transmission gate. Use the procedure
described in the section on Logical Effort to calculate the logical effort for the NOR2 – transmission gate pair.
The transmission gate and the n-channel transistors of the NOR2 gate are all sized the same. The p-channel
transistors of the NOR2 gate are tapered. The transistor closest to the output is sized about half the size of the
other p-channel transistor. Use a stage effort of five to size the NOR2 gate and transmission gate. The beta ratio
of the NOR2 gate and the inverter that drives net ‘m’ will be determined later, after timing simulations are run to
determine the sizes that result in an ‘m’ beta ratio for the ‘E’ to ‘m’ path. Last, the inverter that drives ‘nclk’ is
sized using the same stage effort.
nce all of the devices have been sized and reasonable estimates have been made for the wire capacitances of
O
each net, the cell needs to be simulated to find the ‘E’ to ‘m’ timing (sized for ‘M’ beta ratio).
9.3 POSTICG
This section describes how to design POSTICG cells.
9.3.1 Cell Usage
OSTICG cells, like PREICG cells, are used to conserve clock power. These cells stop the clock from toggling in
P
the flops that they drive. Since clocks toggle twice a cycle, it is important to conserve clock power whenever
possible.
9.3.2 Cell Structure
Figure 9-3 below shows the schematic of a POSTICG cell.
Figure 93 POSTICG Schematic
9.3.3 Cell Sizing
There are a few things to keep in mind when sizing this cell.
● S
ince this cell is designed using a ‘B’ beta ratio, the rise and fall delay of ‘CK’ to ‘ECK’ needs to be
balanced. However, the ‘E’ to ‘m’ path is sized using the ‘M’ beta ratio.
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● S
ince this cell has clock signals, it is important to keep the clock transistors as small as possible while
maintaining performance.
● S
ince the ‘m’ input to the p-channel transistor of the NAND2 gate of the POSTICG is used only as a
keeper and not to drive the output, this transistor should be made as small as possible while meeting the
leakage guidelines.
● Since the tri-state inverter is used only as a keeper, this device should be kept to minimum size.
he NAND2 and output inverter are sized using the same sizes as the FRICG cell. This sizing method ensures
T
that all of the different ICG topologies have the same ‘CK’ to ‘ECK’ timing.
he NAND2 gate that drives the net ‘m’ needs to be sized using the same stage effort as the NAND2 – output
T
inverter stage. Use the ‘M’ beta ratio as a starting point for the beta ratio. The beta ratio will need to be adjusted
later, so that the ‘E’ to ‘m’ path has an ‘M’ beta ratio. The tri-state inverter is sized using minimum devices.
henever there is a gate driving a transmission gate, consider the gate and transmission gate as one device for
W
figuring out the logical effort. In the POSTICG cell, there is an inverter driving a transmission gate. Use the
procedure described in the section on Logical Effort to calculate the logical effort for the inverter – transmission
gate pair. The transmission gate and the n-channel transistors of the inverter are all sized the same. Use a stage
effort of five to size the inverter and transmission gate. The beta ratio of the input inverter and the NAND2 gate
that drives net ‘m’ will be determined later, after timing simulations are run to determine the sizes that result in an
‘M’ beta ratio for the ‘E’ to ‘m’ path. Last, the inverter that drives ‘nclk’ is sized using the same stage effort.
nce all of the devices have been sized and reasonable estimates have been made for the wire capacitances of
O
each net, the cell needs to be simulated to find the ‘E’ to ‘m’ timing (sized for ‘M’ beta ratio).
10 XOR/XNOR
10.1 XOR2/XNOR2
his section describes how to design XOR2 and XNOR2 cells. XOR2 and XNOR2 are grouped together because
T
they are sized the same; only the wiring is different.
10.1.1Cell Usage
XOR2 and XNOR2 are combinatorial cells used throughout a design.
10.1.2Cell Structure
igure 10-1 shows the schematic of an XOR2 and an XNOR2 cell. The only difference between the two is the
F
wiring of the transmission gates.
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Figure 101 XOR2 Schematic (left) and XNOR2 Schematic (right)
10.1.3Cell Sizing
There are a few things to keep in mind when sizing this cell.
● S
ince this cell is designed using an ‘M’ or ‘X’ beta ratio, the delay needs to be the minimum of the
maximum of the rise and fall delays.
● S
ince this cell has an inverter – transmission gate structure, the sizes of the transmission gates and the
n-channel transistors of the inverters driving ‘nb’ and ‘bb’ should be the same.
● S
ince this cell has a fork (‘nb’ drives a transmission gate and an inverter – transmission gate), size the
inverters driving ‘nb’ and ‘bb’ the same.
● S
ince the maximum two finger transmission gate size is typically less than double the single finger
transmission gate size, this cell needs to be layed out before final sizing is done to figure out the
maximum allowable transmission gate sizes.
or this cell, the best place to start sizing is the inverters driving ‘nb’ and ‘bb’. The p-channel transistors are
F
sized to the maximum allowable finger size. For instance, the p-channel transistors for these inverters in the
XOR2_X1M cell are sized the same as the p-channel transistor in the INV_X1M cell. The n-channel transistors for
these inverters and the transmission gates are sized the same. The size that gives the minimum of the maximum
of the rise and fall delays should be used. The transmission gates should have the same number of fingers as
the drive strength. For instance, the XOR2_X1M cell should have transmission gates with one finger and the
XOR2_X3M cell should have transmission gates with three fingers.
he inverter that drives ‘na’ is sized using a stage effort of two. The beta ratio of this inverter should be
T
determined by simulation.
10.2 XOR3/XNOR3
his section describes how to design XOR3 and XNOR3 cells. XOR3 and XNOR3 are grouped together because
T
they are sized the same; only the wiring is different.
10.2.1Cell Usage
XOR3 and XNOR3 are combinatorial cells used throughout a design.
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10.2.2Cell Structure
igure 10-2 shows the schematic of an XOR3 and Figure 10-3 shows the schematic of an XNOR3 cell. The only
F
difference between the two is the wiring of the transmission gates.
Figure 102 XOR3 Schematic
Figure 103 XNOR3 Schematic
10.2.3Cell Sizing
There are a few things to keep in mind when sizing this cell.
● S
ince this cell is designed using an ‘M’ or ‘X’ beta ratio, the delay needs to be the minimum of the
maximum of the rise and fall delays.
● S
ince this cell has many stages, size the output stage first then work back toward the input stage and
finally size the ‘A’ and ‘B’ inverters.
● S
ince this cell has an inverter – transmission gate structure, the sizes of the transmission gates and the
n-channel transistors of the inverters driving ‘nc’ and ‘bc’ should be the same.
● S
ince this cell has a fork (‘nc’ drives a transmission gate and an inverter – transmission gate), size the
inverters driving ‘nc’ and ‘bc’ the same.
● S
ince the maximum two finger transmission gate size is typically less than double the single finger
transmission gate size, this cell needs to be layed out before final sizing is done to figure out the
maximum allowable transmission gate sizes.
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● N
ot all of the inputs will have the same input to output delay. The ‘A’ to ‘Y’ path will be the fastest path,
while the ‘C’ to ‘Y’ path will be the slowest path. The ‘A’ to ‘Y’ path should not be slowed down to more
closely match the timing for the other inputs.
● It is nearly impossible to get the best timing for this cell on the first pass. It is essential to iteratively tune
and simulate this cell to find the proper transistor sizes.
he output stage of an XOR3/XNOR3 cell is an inverter. Size the output inverter just like a single-stage inverter.
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For example, an XOR3_X1M cell has an output inverter with the same sizes as INV_X1M. Now that the output
inverter has been sized, use the stick diagram to determine the lengths of the “ny” wire and the output wire.
he next step is to size the inverter – transmission gate pair driving ‘ny’. Use a stage effort of four to determine
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the total transistor size of the inverter – transmission gate pair. Use the ‘M’ beta ratio to size this inverter (the one
driving ‘nbnc’). The beta ratio of the inverter might need to be changed after the cell has been fully sized and
simulations have been run. Size the p-channel and n-channel transistors of the two transmission gates that drive
‘ny’ using the n-channel transistor size of the inverter that drives ‘nbnc’. The sizes of these two transmission
gates might need to be changed after the cell has been fully sized and simulations have been run.
he input stage has the same topology as an XOR2/XNOR2 cell. The inverters driving ‘nc’ and ‘bc’ will have the
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same sizes. As a starting point, size these inverters the same as the inverter driving ‘nbnc’. Also, the
transmission gates driving ‘bnc’ will have the same sizes as the n-channel transistors of the inverters driving ‘nc’
and ‘bc’. These sizes will need to be changed after the cell has been fully sized and simulations have been run.
he ‘A’ and ‘B’ inverters are the last transistors to size. These inverters are sized using a stage effort of two. The
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beta ratio of these inverters should be determined by simulation.
ow that the entire cell has been sized, run simulations to find the ‘A’ to ‘Y’ timing, the ‘B’ to ‘Y’ timing, and the
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‘C’ to ‘Y’ timing. The ‘A’ to ‘Y’ timing will be the fastest and the ‘C’ to ‘Y’ timing will be the slowest. Continue
tuning and simulating this cell until the timing from each input to the output is the minimum of the maximum
delay.
11 MUX
his section describes how to design the muxes. There are two basic types of muxes: NAND based and
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transmission gate based. The transmission gate muxes have a ‘T’ in the cell name.
11.1 NAND Based Muxes
11.1.1MX2
The MX2 cell is a NAND2 driving another NAND2 with a select inverter as shown in Figure 11-1.
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Figure 111 MX2 Schematic
he output stage of an MX2 cell is a NAND2. Size the output stage NAND2 just like a single-stage NAND2. For
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example, an MX2_X1B cell has an output stage NAND2 with the same sizes as NAND2_X1B. Now that the
output stage NAND2 gate has been sized, use the stick diagram to determine the lengths of the input wires, the
“ans0” and “bs0” wires, and the output wire.
he next step is to size the input stage NAND2 gates. The total transistor size of the top NAND2 gate can be
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found using Logical Effort, since the output stage NAND2 size, the “ans0” wire length, and the logical effort of
NAND2 are known. The total transistor size of the bottom NAND2 gate can be found using Logical Effort, since
the output stage NAND2 size, the “bs0” wire length, and the logical effort of NAND2 are known. At this point,
simulations are needed to determine the beta ratio for the NAND2 gates depending on the beta ratio type for the
cell.
inally, the select inverter needs to be sized. Use the stick diagram to determine the length of the “ns0” wire.
F
The total transistor size of the select inverter can be found using Logical Effort, since the top input stage NAND2
size, the “ns0” wire length, and the logical effort of inverter are known. The logical effort of an inverter is one by
definition. Use a stage effort of two when calculating the size of the select inverter. At this point, simulations are
needed to determine the beta ratio for the select inverter depending on the beta ratio type for the cell.
11.2 Transmission Gate Based Muxes
11.2.1MXT2
he MXT2 cell is an inverter – transmission gate pair driving another inverter with a select inverter as shown in
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Figure 11-2.
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Figure 112 MXT2 Schematic
he output stage of an MXT2 cell is an inverter. Size the output stage inverter just like a single-stage inverter.
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For example, an MXT2_X1X cell has an output stage inverter with the same sizes as INV_X1X. Now that the
output stage inverter has been sized, use the stick diagram to determine the lengths of the input wires, the “na”
and “nb” wires, the “ny” wire, and the output wire.
he next step is to size the input stage inverter – transmission gate pair. The total transistor size of the inverter –
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transmission gate pairs can be found using Logical Effort, since the output stage inverter size, the “ny” wire
length, and the logical effort of an inverter – transmission gate pair are known. Size the n-channel transistors of
the input inverters and the transistors of the transmission gates the same. At this point, simulations are needed
to determine the p-channel transistor size for the input inverters depending on the beta ratio type for the cell.
inally, the select inverter needs to be sized. Use the stick diagram to determine the length of the “ns0” wire.
F
The total transistor size of the select inverter can be found using Logical Effort, since the transmission gate sizes,
the “ns0” wire length, and the logical effort of inverter are known. The logical effort of an inverter is one by
definition. Use a stage effort of two, when calculating the size of the select inverter. At this point, simulations are
needed to determine the beta ratio for the select inverter depending on the beta ratio type for the cell.
11.2.2MXIT2
he MXIT2 cell is an inverter – transmission gate pair with a select inverter as shown in Figure 11-3. This cell is
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similar to the MXT2 cell, except it does not have an output inverter.
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Figure 113 MXIT2 Schematic
he output stage of an MXIT2 cell is an inverter – transmission gate pair. For the ‘X1’ cell, draw the largest
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single-fingered transmission gate with the p-channel and n-channel transistors having equal size. Then set the
‘A’ and ‘B’ inverters’ p-channel size to the largest single-fingered size. Set the ‘A’ and ‘B’ inverters’ n-channel
size to the transmission gates’ transistor size.
ow that the inverter – transmission gate pair has been sized, use the stick diagram to determine the lengths of
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the input wires, the “na” and “nb” wires, and the output wire.
inally, the select inverter needs to be sized. Use the stick diagram to determine the length of the “ns0” wire.
F
The total transistor size of the select inverter can be found using Logical Effort, since the transmission gate sizes,
the “ns0” wire length, and the logical effort of inverter are known. The logical effort of an inverter is one by
definition. Use a stage effort of two, when calculating the size of the select inverter. At this point, simulations are
needed to determine the beta ratio for the select inverter depending on the beta ratio type for the cell.
11.2.3MXT4
he MXT4 cell is an inverter – transmission gate – transmission gate triplet driving another inverter with a select
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inverter as shown in Figure 11-4.
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Figure 114 MXT4 Schematic
he output stage of an MXT4 cell is an inverter. Size the output stage inverter just like a single-stage inverter.
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For example, an MXT4_X1X cell has an output stage inverter with the same sizes as INV_X1X. Now that the
output stage inverter has been sized, use the stick diagram to determine the lengths of the input wires, the
internal wires, the “ny” wire, and the output wire.
he next step is to size the input stage inverter – transmission gate – transmission gate triplet. The total
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transistor size of the inverter – transmission gate – transmission gate triplets can be found using Logical Effort,
since the output stage inverter size, the “ny” wire length, and the logical effort of an inverter – transmission gate –
transmission gate triplet are known. Size the n-channel transistors of the input inverters and the transistors of the
transmission gates the same. At this point, simulations are needed to determine the p-channel transistor size for
the input inverters depending on the beta ratio type for the cell.
inally, the select inverters need to be sized. Use the stick diagram to determine the length of the “ns0” and
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“ns1” wires. The total transistor size of the select inverters can be found using Logical Effort, since the
transmission gate sizes, the “ns0” and “ns1” wire lengths, and the logical effort of inverter are known. The logical
effort of an inverter is one by definition. Use a stage effort of two, when calculating the size of the select
inverters. At this point, simulations are needed to determine the beta ratio for the select inverters depending on
the beta ratio type for the cell.
11.2.4MXIT4
he MXIT4 cell is an inverter – transmission gate driving another inverter – transmission gate driving an inverter
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with a select inverter as shown in Figure 11-5. This cell is similar to the MXT4 cell, except it has an extra pair of
inverters.
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Figure 115 MXIT4 Schematic
he output stage of an MXIT4 cell is an inverter. Size the output stage inverter just like a single-stage inverter.
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For example, an MXIT4_X1X cell has an output stage inverter with the same sizes as INV_X1X. Now that the
output stage inverter has been sized, use the stick diagram to determine the lengths of the input wires, the
internal wires, the “ny” wire, and the output wire.
he next step is to size the middle stage inverter – transmission gate pair. The total transistor size of the inverter
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– transmission gate pairs can be found using Logical Effort, since the output stage inverter size, the “ny” wire
length, and the logical effort of an inverter – transmission gate pair are known. Size the n-channel transistors of
the inverters and the transistors of the transmission gates the same. Size the p-channel transistors of the
inverters using the inverter ‘M’ beta ratio.
ow size the input stage inverter – transmission gate pair. The transmission gates should have the same sizes as
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the middle stage transmission gates. Size the n-channel transistors of the inverters and the transistors of the
transmission gates the same. Simulations are needed to determine the size of the p-channel transistors of the
input inverters.
Finally, the select inverters need to be sized. Use the stick diagram to determine the length of the “ns0” and
“ns1” wires. The total transistor size of the select inverters can be found using Logical Effort, since the
transmission gate sizes, the “ns0” and “ns1” wire lengths, and the logical effort of inverter are known. The logical
effort of an inverter is one by definition. Use a stage effort of two, when calculating the size of the select
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inverters. At this point, simulations are needed to determine the beta ratio for the select inverters depending on
the beta ratio type for the cell.
12 ADDERS
12.1 ADDH
he ADDH cell has two inputs and two outputs as shown in Figure 12-1. This cell should be sized to minimize
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the maximum delay. The propagation delay will be larger to the ‘S’ output than ‘CO’ because of the extra stage
of delay.
Figure 12-1 ADDH Schematic
he output stage of an ADDH cell is an inverter. Size the inverter just like a single-stage inverter. For example,
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an ADDH_X1M cell has output inverters with the same sizes as INV_X1M. Now that the inverters have been
sized, use the stick diagram to determine the lengths of the input wires, the “ns” wire, the “nco” wire, and the
output wires.
he next step is to size the OAI21 gate. The total transistor size of the OAI21 can be found using Logical Effort,
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since the output inverter size, the “ns” wire length, and the logical effort of OAI21 are known. The beta ratio of
the OAI21 will be determined later by simulation, so for now set the OAI21 gate to the beta ratio used in the
single-stage OAI21 cells.
he last gate to size is the NAND2 gate. The total transistor size of the NAND2 can be found using Logical Effort,
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since the output inverter size, the OAI21 total transistor size, the “nco” wire length, and the logical effort of
NAND2 are known. Sweep the beta ratio of the NAND2 gate to find the minimum of the maximum propagation
delay for ‘CO’. Then with the NAND2 gate size fixed, sweep the beta ratio of the OAI21 gate to find the minimum
of the maximum propagation delay for ‘S’. By sizing the ADDH cell this way, both ‘S’ and ‘CO’ will be sized to
have the minimum of the maximum delay.
12.2 ADDF
he ADDF cell has three inputs and two outputs as shown in Figure 12-2. There are many ways to design full
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adders. This version is area efficient compared to the others. This design is known as non-canonical static
because the p-channel stacks are not complements of the n-channel stacks. This cell should be sized to
minimize the maximum delay. The propagation delay will be larger to the ‘S’ output than ‘CO’ because of the
extra stages of delay.
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Figure 12-2 ADDF Schematic
he output stage of an ADDF cell is an inverter as shown in “GROUP 1” of Figure 12-3. Size the inverter just like
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a single-stage inverter. For example, an ADDF_X1M cell has output inverters with the same sizes as INV_X1M.
Now that the inverters have been sized, use the stick diagram to determine the lengths of the input wires, the
“ns” wire, the “nco” wire, and the output wires.
Figure 12-3 ADDF Schematic – GROUP 1
he next step is to size the transistors noted as ‘GROUP 2’ in Figure 12-4. The total transistor size of this group
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can be found using Logical Effort, since the output inverter size, the “ns” wire length, and the logical effort of
AOI21 are known. The logical effort of AOI21 can be used since that cell and this group have a two high
p-channel stack and a two high n-channel stack. The beta ratio of this group will be determined later by
simulation, so for now set the beta ratio of this group to one.
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Figure 12-4 ADDF Schematic – GROUP 2
he next step is to size the transistors noted as ‘GROUP 3’ in Figure 12-5. The only time that the transistors in
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GROUP 3 will affect the logic state of output ‘S’ is if ‘A’, ‘B’, and ‘CI’ are all either logic zero or logic one. If this
condition is true, then ‘S’ is only a function of ‘A’, ‘B’, and ‘CI’. Since ‘S’ is not a function of ‘nco’ in this case, the
transistors in GROUP 3 can have the same total transistor size as the transistors in GROUP 2 even though
GROUP 3 has three high transistor stacks. So, as a starting point, size the transistors in GROUP 3 with the same
sizes as the ones in GROUP 2. These values might need to change after simulations have been run.
Figure 12-5 ADDF Schematic – GROUP 3
he next step is to size the transistors noted as ‘GROUP 4’ in Figure 12-6. The total transistor size of this group
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can be found using Logical Effort, since the output ‘CO’ inverter size, the ‘GROUP 2’ total transistor size, the
“nco” wire length, and the logical effort of AOI21 are known. The logical effort of AOI21 can be used since that
cell and this group have a two high p-channel stack and a two high n-channel stack. The beta ratio of this group
will be determined later by simulation, so for now set the beta ratio of this group to one. An important thing to
note about this group of transistors is that they should never be folded, no matter what the drive strength of the
ADDF cell. Due to the topology of the cell, these transistors can not be folded.
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Figure 12-6 ADDF Schematic – GROUP 4
he next step is to size the transistors noted as ‘GROUP 5’ in Figure 12-7. These transistors should be sized the
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same as the transistors in GROUP 4. An important thing to note about this group of transistors is that they
should never be folded, no matter what the drive strength of the ADDF cell. Due to the topology of the cell, these
transistors can not be folded.
Figure 12-7 ADDF Schematic – GROUP 5
ow that all of the transistors have been sized initially and the total transistor size has been determined,
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simulations need to be run to determine the timing from each of the inputs to each of the outputs. The minimum
of the maximum timing needs to be found for each input to ‘CO’ and also for each input to ‘S’. The total
transistor size of the cell should not change, only the beta ratio of GROUPS 2 – 5 will change. The GROUP 1
output inverter sizes and beta ratio are fixed depending on the beta ratio of the cell.
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13 LATCHES
13.1 Basic Latch Types
here are two basic latch topologies: inverting latches like LATQN and non-inverting latches like LATQ. The
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variants of these two basic latch topologies have reset or set inputs and/or an active-low clock input.
13.2 Latch Sizing Philosophy
he goal of latch sizing is to minimize the maximum delay from input to output of the cell. The ‘LATQ’ and
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‘LATQN’ cells should be sized first. Then the other latch cells can be sized quickly using the same clock inverter
and transmission gate sizes as the ‘LATQ’ and ‘LATQN’ cells.
13.3 Latch Cells
13.3.1Phi1 Latches
13.3.1.1 LATQ
The LATQ cell is a non-inverting, phi1 latch as shown in Figure 13-1.
Figure 13-1 LATQ Schematic
he output stage of a LATQ cell is an inverter as shown in Figure 13-1. Size the inverter just like a single-stage
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inverter. For example, a LATQ_X1X cell has an output inverter with the same sizes as INV_X1X. Now that the
output inverter has been sized, use the stick diagram to determine the lengths of the input wires, the “nm” wire,
and the output wire.
The inverter that drives net ‘m’ and the tri-state inverter have minimum sized transistors.
he input inverter and transmission gate should be sized as a pair using a stage effort of four as a starting point.
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The clock inverter should be sized so that the clock to output delay closely matches the input to output delay.
The clock inverter and transmission gate need to be sized with power in mind. These gates should be sized
using the assumption that a one percent improvement in delay is worth a three percent increase in power. These
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ates should not be upsized if doing so will result in a greater than 3 – 1 ratio of power increase to performance
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improvement.
imulations need to be run to determine the ‘D’ to ‘Q’ timing, the ‘G’ to ‘Q’ timing, and the power of the cell. If
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the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to ‘Q’
delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.1.2 LATQN
The LATQN cell is an inverting, phi1 latch as shown in Figure 13-2.
Figure 13-2 LATQN Schematic
he output stage of a LATQN cell is an inverter as shown in Figure 13-2. Size the inverter just like a single-stage
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inverter. For example, a LATQN_X1X cell has an output inverter with the same sizes as INV_X1X. Now that the
output inverter has been sized, use the stick diagram to determine the lengths of the input wires, the “nm” wire,
the “m” wire, and the output wire.
he tri-state inverter has minimum sized transistors. The inverter that drives net “m” is sized using a stage effort
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of four. The beta ratio of this inverter needs to be determined by simulation.
he input inverter and transmission gate should be sized as a pair using a stage effort of four as a starting point.
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The clock inverter should be sized so that the clock to output delay closely matches the input to output delay.
The clock inverter and transmission gate need to be sized with power in mind. These gates should be sized
using the assumption that a one percent improvement in delay is worth a three percent increase in power. These
gates should not be upsized if doing so will result in a greater than 3 – 1 ratio of power increase to performance
improvement.
Simulations need to be run to determine the ‘D’ to ‘QN’ timing, the ‘G’ to ‘QN’ timing, and the power of the cell.
13.3.1.3 LATRQ
The LATRQ cell is a non-inverting, phi1 latch with an active low reset as shown in Figure 13-3.
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Figure 13-3 LATRQ Schematic
he output stage of a LATRQ cell is an inverter as shown in Figure 13-3. Size the inverter just like a single-stage
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inverter. For example, a LATRQ_X1X cell has an output inverter with the same sizes as INV_X1X. Now that the
output inverter has been sized, use the stick diagram to determine the lengths of the input wires, the “nm” wire,
and the output wire.
he inverter that drives net ‘m’ has minimum sized transistors. The three p-fet transistors driven my ‘G’, ‘m’, and
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‘RN’ are minimum sized. The three n-fet transistors driven by ‘m’, ‘nclk’, and ‘RN’ are sized about 1/3 larger than
minimum size.
he input device and transmission gate should be sized as a pair using the LATQ sizing as a starting point. For
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example, if the LATQ_X1X cell has an input inverter sized as 0.5u/0.35u and a transmission gate sized as
0.3/0.3u, then the LATRQ_X1X initial sizing should be 0.5u/0.5u for the input device and 0.3u/0.3u for the
transmission gate size. The clock inverter should be sized the same as the LATQ with the same drive strength.
imulations need to be run to determine the ‘D’ to ‘Q’ timing, the ‘G’ to ‘Q’ timing, and the power of the cell. If
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the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to ‘Q’
delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.1.4 LATRPQN
The LATRPQN cell is an inverting, phi1 latch with an active high reset as shown in Figure 13-4.
Figure 13-4 LATRPQN Schematic
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he output stage of a LATRPQN cell is an inverter as shown in Figure 13-4. Size the inverter just like a
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single-stage inverter. For example, a LATRPQN_X1X cell has an output inverter with the same sizes as INV_X1X.
Now that the output inverter has been sized, use the stick diagram to determine the lengths of the input wires,
the “nm” wire, the “m” wire, and the output wire.
he tri-state inverter has minimum sized transistors. The NOR2 that drives net “m” is sized using a stage effort of
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four. The beta ratio of this NOR2 needs to be determined by simulation.
he input inverter and transmission gate should be sized as a pair using the LATQN sizing as a starting point. For
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example, if the LATQN_X1X cell has an input inverter sized as 0.5u/0.35u and a transmission gate sized as
0.3/0.3u, then the LATRPQN_1x initial sizing should be 0.5u/0.35u for the input inverter and 0.3u/0.3u for the
transmission gate size. The clock inverter should be sized the same as the LATQN with the same drive strength.
Simulations need to be run to determine the ‘D’ to ‘QN’ timing, the ‘G’ to ‘QN’ timing, and the power of the cell.
13.3.1.5 LATSPQ
The LATSPQ cell is a non-inverting, phi1 latch with an active high set as shown in Figure 13-5.
Figure 13-5 LATSPQ Schematic
he output stage of a LATSPQ cell is an inverter as shown in Figure 13-5. Size the inverter just like a single-stage
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inverter. For example, a LATSPQ_X3M cell has an output inverter with the same sizes as INV_X3M. Now that the
output inverter has been sized, use the stick diagram to determine the lengths of the input wires, the “nm” wire,
and the output wire.
he inverter that drives net ‘m’ has minimum sized transistors. The three p-fet transistors driven my ‘G’, ‘m’, and
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‘S’ are sized about 1/3 larger than minimum size. The three n-fet transistors driven by ‘m’, ‘nclk’, and ‘S’ are
minimum sized.
he input device and transmission gate should be sized as a pair using the LATQ sizing as a starting point. For
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example, if the LATQ_X1X cell has an input inverter sized as 0.5u/0.35u and a transmission gate sized as
0.3/0.3u, then the LATSPQ_X1X initial sizing should be 0.7u/0.35u for the input device and 0.3u/0.3u for the
transmission gate size. The clock inverter should be sized the same as the LATQ with the same drive strength.
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imulations need to be run to determine the ‘D’ to ‘Q’ timing, the ‘G’ to ‘Q’ timing, and the power of the cell. If
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the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to ‘Q’
delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.1.6 LATSQN
The LATSQN cell is an inverting, phi1 latch with an active low set as shown in Figure 13-6.
Figure 13-6 LATSQN Schematic
he output stage of a LATSQN cell is an inverter as shown in Figure 13-6. Size the inverter just like a
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single-stage inverter. For example, a LATSQN_X1X cell has an output inverter with the same sizes as INV_X1X.
Now that the output inverter has been sized, use the stick diagram to determine the lengths of the input wires,
the “nm” wire, the “m” wire, and the output wire.
he tri-state inverter has minimum sized transistors. The NAND2 that drives net “m” is sized using a stage effort
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of four. The beta ratio of this NAND2 needs to be determined by simulation.
he input inverter and transmission gate should be sized as a pair using the LATQN sizing as a starting point. For
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example, if the LATQN_X1X cell has an input inverter sized as 0.5u/0.35u and a transmission gate sized as
0.3/0.3u, then the LATRPQN_X1X initial sizing should be 0.5u/0.35u for the input inverter and 0.3u/0.3u for the
transmission gate size. The clock inverter should be sized the same as the LATQN with the same drive strength.
imulations need to be run to determine the ‘D’ to ‘QN’ timing, the ‘G’ to ‘QN’ timing, and the power of the cell.
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If the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to
‘QN’ delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.2Phi2 Latches
13.3.2.1 LATNQ
The LATNQ cell is a non-inverting, phi2 latch as shown in Figure 13-7.
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Figure 13-7 LATNQ Schematic
This cell should be sized using the LATQ sizing of the same drive strength as a starting point.
imulations need to be run to determine the ‘D’ to ‘Q’ timing, the ‘GN’ to ‘Q’ timing, and the power of the cell. If
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the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to ‘Q’
delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.2.2 LATNQN
The LATNQN cell is an inverting, phi2 latch as shown in Figure 13-8.
Figure 13-8 LATNQN Schematic
This cell should be sized using the LATQN sizing of the same drive strength as a starting point.
imulations need to be run to determine the ‘D’ to ‘QN’ timing, the ‘GN’ to ‘QN’ timing, and the power of the cell.
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If the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to
‘QN’ delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.2.3 LATNRQ
The LATNRQ cell is a non-inverting, phi2 latch with an active low reset as shown in Figure 13-9.
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Figure 13-9 LATNRQ Schematic
This cell should be sized using the LATRQ sizing of the same drive strength as a starting point.
imulations need to be run to determine the ‘D’ to ‘Q’ timing, the ‘GN’ to ‘Q’ timing, and the power of the cell. If
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the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to ‘Q’
delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.2.4 LATNRPQN
The LATNRPQN cell is an inverting, phi2 latch with an active high reset as shown in Figure 13-10.
Figure 13-10 LATNRPQN Schematic
This cell should be sized using the LATRPQN sizing of the same drive strength as a starting point.
Simulations need to be run to determine the ‘D’ to ‘QN’ timing, the ‘GN’ to ‘QN’ timing, and the power of the cell.
13.3.2.5 LATNSPQ
The LATNSPQ cell is a non-inverting, phi2 latch with an active high set as shown in Figure 13-11.
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Figure 13-11 LATNSPQ Schematic
This cell should be sized using the LATSPQ sizing of the same drive strength as a starting point.
imulations need to be run to determine the ‘D’ to ‘Q’ timing, the ‘GN’ to ‘Q’ timing, and the power of the cell. If
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the latch is not flood-filled (X), the output inverter’s beta ratio can be adjusted to minimize the maximum ‘D’ to ‘Q’
delay. If the latch is flood-filled, the output inverter’s transistor sizes can not be changed.
13.3.2.6 LATNSQN
The LATNSQN cell is an inverting, phi2 latch with an active low set as shown in Figure 13-12.
Figure 13-12 LATNSQN Schematic
This cell should be sized using the LATSQN sizing of the same drive strength as a starting point.
Simulations need to be run to determine the ‘D’ to ‘QN’ timing, the ‘GN’ to ‘QN’ timing, and the power of the cell.
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14 FLOPS
14.1 Basic Flop Types
here are two basic types of flops: scan flops and non-scan flops. The scan flops contain extra signals that are
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used only in test mode.
14.2 Flop Sizing Philosophy
he goal of flop sizing is to minimize the total insertion delay of the cell. Total insertion delay, also known as total
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insertion penalty, is the sum of the clock to output delay and the setup time. In each case, the idea is to
minimize the maximum of the delay.
he clock to output delay is measured with a large setup time. The setup time is defined as the point where the
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clock to output delay increases by ten percent over the delay measured with a large setup time. For example, if
the clock to output delay measured with a large setup time is 100 ps and the clock to output delay measured
with a setup time of 40 ps is 110 ps, then the clock to output delay is 100 ps and the setup time is 40 ps.
he scan flops should be sized first and then the non-scan flops can be quickly sized by removing the scan
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signals from the scan flops and simulating to find the cell timing. In particular, the set of scan flops known as the
“Base 9” should be sized first. The “Base 9” flops consist of all five drive strengths of the SDFFQ cell and all four
drive strengths of the SDFFQN cell. Most of the design effort is spent getting these cells to be optimal.
14.3 Flop Cells
14.3.1Phi2/Phi1 Scan Flops
14.3.1.1 SDFFQ
The SDFFQ cell is a non-inverting, phi2/phi1 flop as shown in Figure 14-1.
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Figure 14-1 SDFFQ Schematic
lthough there are many inverters, tri-state inverters, and transmission gates in flops, many of them are either for
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scan or feedback. The transistors that have the most effect on the timing of the flop are shown with a dashed
line box around them in Figure 14-2. The most important transistors are the clock inverters and the ‘D’ to ‘Q’
forward path.
Figure 14-2 SDFFQ Schematic with Important Gates Noted in the Dashed Line Boxes
he output stage of an SDFFQ cell is an inverter as shown in Figure 14-2. Size the output inverter just like a
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single-stage inverter. For example, a SDFFQ_X1X cell has an output inverter with the same sizes as INV_X1X.
Now that the output inverter has been sized, use the stick diagram to determine the lengths of the input wires,
the internal wires, and the output wire.
he feedback tri-state inverters have minimum sized transistors. The tri-state inverter driven by ‘SI’ should have
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the n-channel transistor set to minimum size. The p-channel transistor should be set to the minimum size
transistor times the inverter ‘M’ beta ratio. The inverter that drives net ‘ns’ is initially sized using a stage effort of
four. The beta ratio of this inverter needs to be determined by simulation.
he inverter that drives net ‘m’ and the transmission gate that drives net ‘s’ should be sized as a pair using a
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stage effort of four as a starting point. Likewise, the input device in the dashed line box in Figure 14-2 that drives
net ‘nmux’ and the transmission gate that drives net ‘nm’ should be sized as a pair. This transmission gate
should have the same total transistor size as the other transmission gate. The clock inverters and transmission
gates need to be sized with power in mind. These gates should be sized using the assumption that a one
percent improvement in delay is worth a three percent increase in power. These gates should not be upsized if
doing so will result in a greater than 3 – 1 ratio of power increase to performance improvement.
or the SDFFQ_X4M cell, increase the cell size by one track if the slave transmission gate can be made larger
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without folding. Be sure to include the larger wire length when tuning.
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imulations need to be run to determine the ‘CK’ to ‘Q’ timing, the ‘D’ to ‘CK’ timing (setup time), and the power
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of the cell.
14.3.1.2 SDFFQN
The SDFFQN cell is an inverting, phi2/phi1 flop as shown in Figure 14-3.
Figure 14-3 SDFFQN Schematic
lthough there are many inverters, tri-state inverters, and transmission gates in flops, many of them are either for
A
scan or feedback. The transistors that have the most effect on the timing of the flop are shown with a dashed
line box around them in Figure 14-4. The most important transistors are the clock inverters and the ‘D’ to ‘QN’
forward path.
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Figure 14-4 SDFFQN Schematic with Important Gates Noted in the Dashed Line Boxes
he output stage of an SDFFQN cell is an inverter as shown in Figure 14-4. Size the output inverter just like a
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single-stage inverter. For example, a SDFFQN_X1X cell has an output inverter with the same sizes as INV_X1X.
Now that the output inverter has been sized, use the stick diagram to determine the lengths of the input wires,
the internal wires, and the output wire.
he feedback tri-state inverters and the inverter that drives net ‘ns’ have minimum sized transistors. The tri-state
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inverter driven by ‘SI’ should have the n-channel transistor set to minimum size. The p-channel transistor should
be set to the minimum size transistor times the inverter ‘M’ beta ratio.
he inverter that drives net ‘m’ and the transmission gate that drives net ‘s’ should be sized as a pair using a
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stage effort of four as a starting point. Likewise, the input device in the dashed line box in Figure 14-4 that drives
net ‘nmux’ and the transmission gate that drives net ‘nm’ should be sized as a pair. This transmission gate
should have the same total transistor size as the other transmission gate. The clock inverters and transmission
gates need to be sized with power in mind. These gates should be sized using the assumption that a one
percent improvement in delay is worth a three percent increase in power. These gates should not be upsized if
doing so will result in a greater than 3 – 1 ratio of power increase to performance improvement.
imulations need to be run to determine the ‘CK’ to ‘QN’ timing, the ‘D’ to ‘CK’ timing (setup time), and the
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power of the cell.
he remaining flops should not be sized until the SDFFQ and SDFFQN flops have been tuned, layed out, and
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retuned based on the layout.
14.3.1.3 SDFFRPQ
The SDFFRPQ cell is a non-inverting, phi2/phi1 flop with active high reset as shown in Figure 14-5.
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Figure 14-5 SDFFRPQ Schematic
ize this cell using the same clock transistor sizes and transmission gate sizes as SDFFQ. The n-channel
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transistors of the slave latch feedback structure should be minimum sized. The p-channel transistors should be
about 1/3 larger than minimum size. The NOR2 gate should initially be sized with the same n-channel transistor
size as the inverter that drives net ‘m’ in SDFFQ. The p-channel transistor size should be initially set using the
NOR2 ‘M’ beta ratio.
14.3.1.4 SDFFRPQN
The SDFFRPQN cell is an inverting, phi2/phi1 flop with active high reset as shown in Figure 14-6.
Figure 14-6 SDFFRPQN Schematic
ize this cell using the same clock transistor sizes and transmission gate sizes as SDFFQN. The n-channel
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transistors of the slave latch feedback structure should be minimum sized. The p-channel transistors should be
about 1/3 larger than minimum size. The NOR2 gate should initially be sized with the same n-channel transistor
size as the inverter that drives net ‘m’ in SDFFQ. The p-channel transistor size should be initially set using the
NOR2 ‘M’ beta ratio.
14.3.1.5 SDFFSQ
The SDFFSQ cell is a non-inverting, phi2/phi1 flop with active low set as shown in Figure 14-7.
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Figure 14-7 SDFFSQ Schematic
ize this cell using the same clock transistor sizes and transmission gate sizes as SDFFQ. The p-channel
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transistors of the slave latch feedback structure should be minimum sized. The n-channel transistors should be
about 1/3 larger than minimum size. The NAND2 gate should initially be sized with the same p-channel transistor
size as the inverter that drives net ‘m’ in SDFFQ. The n-channel transistor size should be initially set using the
NAND2 ‘M’ beta ratio.
14.3.1.6 SDFFSQN
The SDFFSQN cell is an inverting, phi2/phi1 flop with active low set as shown in Figure 14-8.
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Figure 14-8 SDFFSQN Schematic
ize this cell using the same clock transistor sizes and transmission gate sizes as SDFFQN. The p-channel
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transistors of the slave latch feedback structure should be minimum sized. The n-channel transistors should be
about 1/3 larger than minimum size. The NAND2 gate should initially be sized with the same p-channel transistor
size as the inverter that drives net ‘m’ in SDFFQ. The n-channel transistor size should be initially set using the
NAND2 ‘M’ beta ratio.
14.3.1.7 SDFFSRPQ
he SDFFSRPQ cell is a non-inverting, phi2/phi1 flop with active low set and active high reset as shown in Figure
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14-9. The set signal has priority over reset.
Figure 14-9 SDFFSRPQ Schematic
ize this cell using the same clock transistor sizes and transmission gate sizes as SDFFQ. The transistors of the
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slave latch feedback structure should be about 1/3 larger than minimum size. Simulations are needed to
determine the sizes of the transistors of the master latch forward path.
14.3.1.8 SDFFYQ
The SDFFYQ cell is a non-inverting, phi2/phi1 flop as shown in Figure 14-10.
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Figure 14-10 SDFFYQ Schematic
he SDFFYQ flop is sized exactly the same as the SDFFQ flop except that the two clock inverters are upsized
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compared to the SDFFQ flop. The clock inverter driving ‘bclk’ is sized using a stage effort of three. Also, the
feedback tri-state inverters should be made double the minimum size.
14.3.1.9 A2SDFFQ
he A2SDFFQ cell is a non-inverting, phi2/phi1 flop with an AND gate integrated to the front as shown in Figure
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14-11.
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Figure 14-11 A2SDFFQ Schematic
he A2SDFFQ flop is sized exactly the same as the SDFFQ flop except that the input stage size needs to be
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determined by simulation.
14.3.1.10 A2SDFFQN
he A2SDFFQN cell is an inverting, phi2/phi1 flop with an AND gate integrated to the front as shown in Figure
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14-12.
Figure 14-12 A2SDFFQN Schematic
he A2SDFFQN flop is sized exactly the same as the SDFFQN flop except that the input stage size needs to be
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determined by simulation.
14.3.1.11 ESDFFQ
The ESDFFQ cell is a non-inverting, phi2/phi1 flop with an active high enable as shown in Figure 14-13.
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Figure 14-13 ESDFFQ Schematic
he ESDFFQ flop is sized using the SDFFQN flop as a starting point. The inverter that drives net ‘semux’ should
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be sized using a beta ratio of one with the same sizes as the transmission gate that it drives. The remaining three
transmission gates should all be sized the same. Initially they should all be set to the size of the transmission
gate that drives net ‘m’. The input inverter and the inverter that drives net ‘nfb’ should also be sized the same.
The beta ratio of the input inverter needs to be determined by simulation. The n-channel transistor of the input
inverter should be set equal to the n-channel size of the transmission gate that drives net ‘nenmux’. Finally, the
enable inverter should be sized using a stage effort of two with the inverter ‘M’ beta ratio.
14.3.1.12 ESDFFQN
The ESDFFQN cell is an inverting, phi2/phi1 flop with an active high enable as shown in Figure 14-14.
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Figure 14-14 ESDFFQN Schematic
he ESDFFQN flop is sized using the SDFFQ flop as a starting point. The inverter that drives net ‘semux’ should
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be sized using a beta ratio of one with the same sizes as the transmission gate that it drives. The remaining three
transmission gates should all be sized the same. Initially they should all be set to the size of the transmission
gate that drives net ‘m’. The input inverter and the inverter that drives net ‘nfb’ should also be sized the same.
The beta ratio of the input inverter needs to be determined by simulation. The n-channel transistor of the input
inverter should be set equal to the n-channel size of the transmission gate that drives net ‘nenmux’. Finally, the
enable inverter should be sized using a stage effort of two with the inverter ‘M’ beta ratio.
14.3.1.13 M2SDFFQ
The M2SDFFQ cell is a non-inverting, phi2/phi1 flop with a MUX integrated to the front as shown in Figure 14-15.
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Figure 14-15 M2SDFFQ Schematic
he M2SDFFQ flop is sized using the SDFFQN flop as a starting point. The inverter that drives net ‘semux’
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should be sized using a beta ratio of one with the same sizes as the transmission gate that it drives. The
remaining three transmission gates should all be sized the same. Initially they should all be set to the size of the
transmission gate that drives net ‘m’. The ‘D0’ and ‘D1’ input inverters should also be sized the same. The beta
ratio of the input inverters needs to be determined by simulation. The n-channel transistor of the input inverters
should be set equal to the n-channel size of the transmission gate that drives net ‘nenmux’. Finally, the select
inverter should be sized using a stage effort of two with the inverter ‘M’ beta ratio.
14.3.1.14 M2SDFFQN
The M2SDFFQN cell is an inverting, phi2/phi1 flop with a MUX integrated to the front as shown in Figure 14-16.
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Figure 14-16 M2SDFFQN Schematic
he M2SDFFQN flop is sized using the SDFFQ flop as a starting point. The inverter that drives net ‘semux’
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should be sized using a beta ratio of one with the same sizes as the transmission gate that it drives. The
remaining three transmission gates should all be sized the same. Initially they should all be set to the size of the
transmission gate that drives net ‘m’. The ‘D0’ and ‘D1’ input inverters should also be sized the same. The beta
ratio of the input inverters needs to be determined by simulation. The n-channel transistor of the input inverters
should be set equal to the n-channel size of the transmission gate that drives net ‘nenmux’. Finally, the select
inverter should be sized using a stage effort of two with the inverter ‘M’ beta ratio.
14.3.2Phi1/Phi2 Scan Flops
14.3.2.1 SDFFNQ
The SDFFNQ cell is a non-inverting, phi1/phi2 flop as shown in Figure 14-17.
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Figure 14-17 SDFFNQ Schematic
he sizing strategy for the SDFFNQ flop is the same as the SDFFQ flop. However, the SDFFNQ flop will have
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much different clock inverter sizes and transmission gate sizes.
14.3.2.2 SDFFNRPQ
The SDFFNRPQ cell is a non-inverting, phi1/phi2 flop with active high reset as shown in Figure 14-18.
Figure 14-18 SDFFNRPQ Schematic
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he sizing strategy for the SDFFNRPQ flop is the same as the SDFFRPQ flop. However, the SDFFNRPQ flop will
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have much different clock inverter sizes and transmission gate sizes.
14.3.2.3 SDFFNSQ
The SDFFNSQ cell is a non-inverting, phi1/phi2 flop with active low set as shown in Figure 14-19.
Figure 14-19 SDFFNSQ Schematic
he sizing strategy for the SDFFNRPQ flop is the same as the SDFFRPQ flop. However, the SDFFNRPQ flop will
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have much different clock inverter sizes and transmission gate sizes.
14.3.2.4 SDFFNSRPQ
he SDFFNSRPQ cell is a non-inverting, phi1/phi2 flop with active low set and active high reset as shown in
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Figure 14-20. The set signal has priority over reset.
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Figure 14-20 SDFFNSRPQ Schematic
he sizing strategy for the SDFFNSRPQ flop is the same as the SDFFQ flop. However, the SDFFNSRPQ flop will
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have much different clock inverter sizes and transmission gate sizes.
14.3.3Phi2/Phi1 Non-Scan Flops
14.3.3.1 DFFQ
The DFFQ cell is a non-inverting, phi2/phi1 non-scan flop as shown in Figure 14-21.
Figure 14-21 DFFQ Schematic
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he DFFQ cell is similar to the SDFFQ cell. The DFFQ cell does not have a scan enable inverter, a scan in
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tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The DFFQ cell sizing
should be made the same as the SDFFQ cell except for the input inverter. The n-channel transistor size should
be set equal to the n-channel transistor size of the transmission gate that drives net ‘nm’. The beta ratio of the
input inverter needs to be determined by simulation.
14.3.3.2 DFFQN
The DFFQN cell is an inverting, phi2/phi1 non-scan flop as shown in Figure 14-22.
Figure 14-22 DFFQN Schematic
he DFFQN cell is similar to the SDFFQN cell. The DFFQN cell does not have a scan enable inverter, a scan in
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tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The DFFQN cell
sizing should be made the same as the SDFFQN cell except for the input inverter. The n-channel transistor size
should be set equal to the n-channel transistor size of the transmission gate that drives net ‘nm’. The beta ratio
of the input inverter needs to be determined by simulation.
14.3.3.3 DFFRPQ
The DFFRPQ cell is a non-inverting, phi2/phi1 non-scan flop with active high reset as shown in Figure 14-23.
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Figure 14-23 DFFRPQ Schematic
he DFFRPQ cell is similar to the SDFFRPQ cell. The DFFRPQ cell does not have a scan enable inverter, a scan
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in tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The DFFRPQ cell
sizing should be made the same as the SDFFRPQ cell except for the input inverter. The n-channel transistor size
should be set equal to the n-channel transistor size of the transmission gate that drives net ‘nm’. The beta ratio
of the input inverter needs to be determined by simulation.
14.3.3.4 DFFRPQN
The DFFRPQN cell is an inverting, phi2/phi1 non-scan flop with active high reset as shown in Figure 14-24.
Figure 14-24 DFFRPQN Schematic
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he DFFRPQN cell is similar to the SDFFRPQN cell. The DFFRPQN cell does not have a scan enable inverter, a
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scan in tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The
DFFRPQN cell sizing should be made the same as the SDFFRPQN cell except for the input inverter. The
n-channel transistor size should be set equal to the n-channel transistor size of the transmission gate that drives
net ‘nm’. The beta ratio of the input inverter needs to be determined by simulation.
14.3.3.5 DFFSQ
The DFFSQ cell is a non-inverting, phi2/phi1 non-scan flop with active low set as shown in Figure 14-25.
Figure 14-25 DFFSQ Schematic
he DFFSQ cell is similar to the SDFFSQ cell. The DFFSQ cell does not have a scan enable inverter, a scan in
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tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The DFFSQ cell
sizing should be made the same as the SDFFSQ cell except for the input inverter. The n-channel transistor size
should be set equal to the n-channel transistor size of the transmission gate that drives net ‘nm’. The beta ratio
of the input inverter needs to be determined by simulation.
14.3.3.6 DFFSQN
The DFFSQN cell is an inverting, phi2/phi1 non-scan flop with active low set as shown in Figure 14-26.
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Figure 14-26 DFFSQN Schematic
he DFFSQN cell is similar to the SDFFSQN cell. The DFFSQN cell does not have a scan enable inverter, a scan
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in tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The DFFSQN cell
sizing should be made the same as the SDFFSQN cell except for the input inverter. The n-channel transistor size
should be set equal to the n-channel transistor size of the transmission gate that drives net ‘nm’. The beta ratio
of the input inverter needs to be determined by simulation.
14.3.3.7 DFFSRPQ
he DFFSRPQ cell is a non-inverting, phi2/phi1 non-scan flop with active low set and active high reset as shown
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in Figure 14-27. The set signal has priority over reset.
Figure 14-27 DFFSRPQ Schematic
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he DFFSRPQ cell is similar to the SDFFSRPQ cell. The DFFSRPQ cell does not have a scan enable inverter, a
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scan in tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The
DFFSRPQ cell sizing should be made the same as the SDFFSRPQ cell except for the input inverter. The
n-channel transistor size should be set equal to the n-channel transistor size of the transmission gate that drives
net ‘nm’. The beta ratio of the input inverter needs to be determined by simulation.
14.3.3.8 DFFYQ
The DFFYQ cell is a non-inverting, phi2/phi1 non-scan flop as shown in Figure 14-28.
Figure 14-28 DFFYQ Schematic
he DFFYQ cell is similar to the SDFFYQ cell. The DFFYQ cell does not have a scan enable inverter, a scan in
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tri-state inverter, and has an inverting input stage instead of a tri-state inverter input stage. The DFFYQ cell
sizing should be made the same as the SDFFYQ cell except for the input inverter. The n-channel transistor size
should be set equal to the n-channel transistor size of the transmission gate that drives net ‘nm’. The beta ratio
of the input inverter needs to be determined by simulation.
14.3.3.9 A2DFFQ
he A2DFFQ cell is a non-inverting, phi2/phi1 non-scan flop with an AND gate integrated to the front as shown in
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Figure 14-29.
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Figure 14-29 A2DFFQ Schematic
he A2DFFQ cell is similar to the A2SDFFQ cell. The A2DFFQ cell does not have a scan enable inverter, a scan
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in tri-state inverter, and has an NAND2 input stage instead of a tri-state NAND2 input stage. The A2DFFQ cell
sizing should be made the same as the A2SDFFQ cell except for the input NAND2 gate. The p-channel transistor
size should be set equal to the p-channel transistor size of the input gate of the A2SDFFQ cell. The beta ratio of
the input NAND2 gate needs to be determined by simulation.
14.3.3.10 A2DFFQN
he A2DFFQN cell is an inverting, phi2/phi1 non-scan flop with an AND gate integrated to the front as shown in
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Figure 14-30.
Figure 14-30 A2DFFQN Schematic
he A2DFFQN cell is similar to the A2SDFFQN cell. The A2DFFQN cell does not have a scan enable inverter, a
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scan in tri-state inverter, and has an NAND2 input stage instead of a tri-state NAND2 input stage. The A2DFFQN
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ell sizing should be made the same as the A2SDFFQN cell except for the input NAND2 gate. The p-channel
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transistor size should be set equal to the p-channel transistor size of the input gate of the A2SDFFQN cell. The
beta ratio of the input NAND2 gate needs to be determined by simulation.
14.3.3.11 EDFFQ
The EDFFQ cell is a non-inverting, phi2/phi1 non-scan flop with an active high enable as shown in Figure 14-31.
Figure 14-31 EDFFQ Schematic
he EDFFQ cell is similar to the ESDFFQ cell. The EDFFQ cell does not have a scan enable inverter, a scan in
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tri-state inverter, or a scan enable transmission gate. The EDFFQ cell sizing should be made the same as the
ESDFFQ cell except for the input inverter. The n-channel transistor size should be set equal to the n-channel
transistor size of the transmission gate that drives net ‘nm’. The beta ratio of the input inverter needs to be
determined by simulation. Both of the ‘E’ transmission gates need to be sized the same. Likewise, the input
inverter and the inverter driving net ‘nfb’ need to be sized the same.
14.3.3.12 EDFFQN
The EDFFQN cell is an inverting, phi2/phi1 non-scan flop with an active high enable as shown in Figure 14-32.
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Figure 14-32 EDFFQN Schematic
he EDFFQN cell is similar to the ESDFFQN cell. The EDFFQN cell does not have a scan enable inverter, a scan
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in tri-state inverter, or a scan enable transmission gate. The EDFFQN cell sizing should be made the same as the
ESDFFQN cell except for the input inverter. The n-channel transistor size should be set equal to the n-channel
transistor size of the transmission gate that drives net ‘nm’. The beta ratio of the input inverter needs to be
determined by simulation. Both of the ‘E’ transmission gates need to be sized the same. Likewise, the input
inverter and the inverter driving net ‘nfb’ need to be sized the same.
14.3.3.13 M2SDFFQ
he M2DFFQ cell is a non-inverting, phi2/phi1 non-scan flop with a MUX integrated to the front as shown in
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Figure 14-33.
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Figure 14-33 M2DFFQ Schematic
he M2DFFQ cell is similar to the M2SDFFQ cell. The M2DFFQ cell does not have a scan enable inverter, a scan
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in tri-state inverter, or a scan enable transmission gate. The M2DFFQ cell sizing should be made the same as the
M2SDFFQ cell except for the input inverters. The n-channel transistor size should be set equal to the n-channel
transistor size of the transmission gates that drive net ‘nenmux’. The beta ratio of the input inverters needs to be
determined by simulation. Both of the ‘S0’ transmission gates need to be sized the same. Likewise, the input
inverters need to be sized the same.
14.3.3.14 M2DFFQN
he M2DFFQN cell is an inverting, phi2/phi1 non-scan flop with a MUX integrated to the front as shown in Figure
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14-34.
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Figure 14-34 M2DFFQN Schematic
he M2DFFQN cell is similar to the M2SDFFQN cell. The M2DFFQN cell does not have a scan enable inverter, a
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scan in tri-state inverter, or a scan enable transmission gate. The M2DFFQN cell sizing should be made the
same as the M2SDFFQN cell except for the input inverters. The n-channel transistor size should be set equal to
the n-channel transistor size of the transmission gates that drive net ‘nenmux’. The beta ratio of the input
inverters needs to be determined by simulation. Both of the ‘S0’ transmission gates need to be sized the same.
Likewise, the input inverters need to be sized the same.
14.3.4Phi1/Phi2 Non-Scan Flops
14.3.4.1 DFFNQ
The DFFNQ cell is a non-inverting, phi1/phi2 non-scan flop as shown in Figure 14-35.
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Figure 14-35 DFFNQ Schematic
he sizing strategy for the DFFNQ flop is the same as the DFFQ flop. However, the DFFNQ flop will have much
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different clock inverter sizes and transmission gate sizes.
14.3.4.2 DFFNRPQ
The DFFNRPQ cell is a non-inverting, phi1/phi2 non-scan flop with active high reset as shown in Figure 14-36.
Figure 14-36 DFFNRPQ Schematic
he sizing strategy for the DFFNRPQ flop is the same as the DFFRPQ flop. However, the DFFNRPQ flop will
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have much different clock inverter sizes and transmission gate sizes.
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14.3.4.3 DFFNSQ
The DFFNSQ cell is a non-inverting, phi1/phi2 non-scan flop with active low set as shown in Figure 14-37.
Figure 14-37 DFFNSQ Schematic
he sizing strategy for the DFFNSQ flop is the same as the DFFSQ flop. However, the DFFNSQ flop will have
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much different clock inverter sizes and transmission gate sizes.
14.3.4.4 DFFNSRPQ
he DFFNSRPQ cell is a non-inverting, phi1/phi2 non-scan flop with active low set and active high reset as
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shown in Figure 14-38. The set signal has priority over reset.
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Figure 14-38 DFFNSRPQ Schematic
he sizing strategy for the DFFNSRPQ flop is the same as the DFFSRPQ flop. However, the DFFNSRPQ flop will
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have much different clock inverter sizes and transmission gate sizes.
15 BUFZ
15.1 Cell Usage
UFZ cells are combinatorial cells that are used very infrequently. There have been unsuccessful attempts to
B
remove these cells from future Base libraries.
15.2 Cell Structure
Figure 15-1 shows the schematic of a BUFZ cell.
Figure 15-1 BUFZ Schematic
15.3 Cell Sizing
he output stage of a BUFZ cell is an inverter structure as shown in Figure 15-1. Size the inverter structure just
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like a single-stage inverter. For example, a BUFZ_X1M cell has an output inverter with the same sizes as
INV_X1M. If those sizes do not fit in layout, draw the largest sizes possible while maintaining the correct beta
ratio. Now that the output inverter has been sized, use the stick diagram to determine the lengths of the input
wires, the internal wires, and the output wire.
ize the p-channel transistor driven by input ‘A’ by dividing the output p-channel transistor size by two. Size the
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n-channel transistor driven by input ‘A’ by dividing the output n-channel transistor size by two. Size the
p-channel transistors driven by input ‘OE’ and net ‘noe’ the same. Their sizes are half the size of the p-channel
transistor driven by input ‘A’. Size the n-channel transistors driven by input ‘OE’ and net ‘noe’ the same. Their
sizes are half the size of the n-channel transistor driven by input ‘A’.
Finally, size the inverter driven by input ‘OE’ using a stage effort of two with the inverter ‘M’ beta ratio.
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16 DLY4
16.1 Cell Usage
LY4 cells are combinatorial cells that are used to fix hold paths. They are designed to have a large amount of
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delay in a very small area.
16.2 Cell Structure
Figure 16-1 shows the schematic of a DLY4 cell.
Figure 16-1 DLY4 Schematic
16.3 Cell Sizing
he output stage of a DLY4 cell is an inverter. Size the output inverter just like a single-stage inverter. For
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example, a DLY4_X1M cell has an output inverter with the same sizes as INV_X1M. Now that the output inverter
has been sized, use the stick diagram to determine the lengths of the input wires, the internal wires, and the
output wire.
he next step is to size the three tri-state inverters. The total transistor size of the tri-state inverter that drives net
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‘nba’ can be found using Logical Effort, since the output inverter size, the ‘nba’ wire length, and the logical effort
of a tri-state inverter are known. Ignore the transistors used as capacitors when sizing the tri-state inverter. The
other two tri-state inverters should be sized the same as this tri-state inverter. At this point, simulations are
needed to determine the beta ratio for the tri-state inverters depending on the beta ratio type for the cell, with the
two transistors used as capacitors set to zero width. Once the tri-state inverters have been sized, set the
transistors used as capacitors to the size of the same transistors in the DLY2 cell.
he layout area of this cell should match the layout area of two equivalent buffers. For instance, a DLY4_X0P5M
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cell should have the same area as two BUF_X0P5M cells.
17 VOLTAGE REFERENCE CELLS
here are two voltage reference cells in the Base library: TIEHI and TIELO. As the names imply, TIEHI generates
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a logic one and TIELO generates a logic zero.
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17.1 TIEHI
17.1.1Cell Usage
TIEHI cells are combinatorial cells used to generate logic one voltage values.
17.1.2Cell Structure
Figure 17-1 shows the schematic of a TIEHI cell.
Figure 17-1 TIEHI Schematic
17.1.3Cell Sizing
ize the p-channel transistor that drives the output the same as the p-channel transistor of an inverter with the
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same drive strength. For example, a TIEHI_X1M cell has a p-channel transistor size with the same size as the
p-channel transistor of INV_X1M.
he n-channel transistors are set to minimum size. The remaining p-channel transistor is set to the minimum size
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times the inverter ‘M’ beta ratio.
17.2 TIELO
17.2.1Cell Usage
TIELO cells are combinatorial cells used to generate logic zero voltage values.
17.2.2Cell Structure
Figure 17-2 shows the schematic of a TIELO cell.
Figure 17-2 TIELO Schematic
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17.2.3Cell Sizing
ize the n-channel transistor that drives the output the same as the n-channel transistor of an inverter with the
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same drive strength. For example, a TIELO_X1M cell has an n-channel transistor size with the same size as the
n-channel transistor of INV_X1M.
he other n-channel transistor is set to minimum size. The p-channel transistor on the left is set to the minimum
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size times the inverter ‘M’ beta ratio. The other p-channel transistor is set to minimum size.
18 REGISTER FILES
egister file cells are latch based cells with one or two read ports and one or two write ports. These cells are not
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used during Logic Synthesis.
18.1 RF1R1WS
18.1.1Cell Usage
RF1R1WS cells are latch cells with one read port and one write port.
18.1.2Cell Structure
Figure 18-1 shows the schematic of an RF1R1WS cell.
Figure 18-1 RF1R1WS Schematic
18.1.3Cell Sizing
se a beta ratio of one for the output transmission gate. For the RF1R1WS_X1M cell, the transistor size is set to
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the largest single finger transmission gate size. For other drive strengths, the transistor sizes are scaled
accordingly.
ize the n-channel transistor of the inverter that drives net ‘rbl_int’ the same as the output transmission gate size.
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Size the p-channel transistor using the inverter ‘M’ beta ratio.
Set the feedback inverter and tri-state inverter to minimum size.
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ize the input inverter and transmission gate as a pair using a stage effort of four. Use a beta ratio of one for the
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input transmission gate. Size the n-channel transistor of the input inverter the same as the input transmission
gate size. Size the p-channel transistor using the inverter ‘M’ beta ratio.
he input inverter and transmission gate can not be folded. If a stage effort of four results in these devices being
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more than finger, they need to be downsized to a single finger size.
Size the WWL and RWL inverters using a stage effort of two and the inverter ‘M’ beta ratio.
18.2 RF2R1WS
18.2.1Cell Usage
RF2R1WS cells are latch cells with two read ports and one write port.
18.2.2Cell Structure
Figure 18-2 shows the schematic of an RF2R1WS cell.
Figure 18-2 RF2R1WS Schematic
18.2.3Cell Sizing
se a beta ratio of one for the output transmission gates. For the RF2R1WS_X1M cell, the transistor size is set to
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the largest single finger transmission gate size. For other drive strengths, the transistor sizes are scaled
accordingly.
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ize the n-channel transistor of the inverters that drives net ‘rbl1_int’ and ‘rbl2_int’ the same as the output
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transmission gate size. Size the p-channel transistor using the inverter ‘M’ beta ratio.
Set the feedback inverter and tri-state inverter to minimum size.
ize the input inverter and transmission gate as a pair using a stage effort of four. Use a beta ratio of one for the
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input transmission gate. Size the n-channel transistor of the input inverter the same as the input transmission
gate size. Size the p-channel transistor using the inverter ‘M’ beta ratio.
he input inverter and transmission gate can not be folded. If a stage effort of four results in these devices being
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more than finger, they need to be downsized to a single finger size.
Size the WWL, RWL1, and RWL2 inverters using a stage effort of two and the inverter ‘M’ beta ratio.
18.3 RF1R2WS
18.3.1Cell Usage
RF1R2WS cells are latch cells with one read port and two write ports.
18.3.2Cell Structure
Figure 18-3 shows the schematic of an RF1R2WS cell.
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Figure 18-3 RF1R2WS Schematic
18.3.3Cell Sizing
se a beta ratio of one for the output transmission gate. For the RF1R2WS_X1M cell, the transistor size is set to
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the largest single finger transmission gate size. For other drive strengths, the transistor sizes are scaled
accordingly.
ize the n-channel transistor of the inverter that drives net ‘rbl_int’ the same as the output transmission gate size.
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Size the p-channel transistor using the inverter ‘M’ beta ratio.
et the feedback inverter to minimum size. Set the three high p-channel transistor and three high n-channel
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transistor feedback stack to about one-third larger than minimum size.
ize the input inverters and transmission gates as a pair using a stage effort of four. Use a beta ratio of one for
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the input transmission gate. Size the n-channel transistor of the input inverters the same as the input
transmission gate size. Size the p-channel transistor using the inverter ‘M’ beta ratio.
he input inverter and transmission gate can not be folded. If a stage effort of four results in these devices being
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more than finger, they need to be downsized to a single finger size.
Size the WWL, WWL2, and RWL inverters using a stage effort of two and the inverter ‘M’ beta ratio.
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18.4 RF2R2WS
18.4.1Cell Usage
RF2R2WS cells are latch cells with one read port and two write ports.
18.4.2Cell Structure
Figure 18-4 shows the schematic of an RF2R2WS cell.
Figure 18-4 RF2R2WS Schematic
18.4.3Cell Sizing
se a beta ratio of one for the output transmission gates. For the RF2R2WS_X1M cell, the transistor size is set to
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the largest single finger transmission gate size. For other drive strengths, the transistor sizes are scaled
accordingly.
ize the n-channel transistor of the inverters that drives net ‘rbl1_int’ and ‘rbl2_int’ the same as the output
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transmission gate size. Size the p-channel transistor using the inverter ‘M’ beta ratio.
et the feedback inverter to minimum size. Set the three high p-channel transistor and three high n-channel
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transistor feedback stack to about one-third larger than minimum size.
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ize the input inverters and transmission gates as a pair using a stage effort of four. Use a beta ratio of one for
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the input transmission gate. Size the n-channel transistor of the input inverters the same as the input
transmission gate size. Size the p-channel transistor using the inverter ‘M’ beta ratio.
he input inverters and transmission gates can not be folded. If a stage effort of four results in these devices
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being more than finger, they need to be downsized to a single finger size.
Size the WWL1, WWL2, RWL1, and RWL2 inverters using a stage effort of two and the inverter ‘M’ beta ratio.
19 LAYOUT FINISHING CELLS
The Base library contains various layout finishing cells including the following.
● NTENNA
A
● FILL
● FILLCAP
● FILLTIE
● ENDCAPTIE
The only layout finishing cells that have schematics and symbols are the following.
A
● NTENNA
● FILLCAP
19.1 ANTENNA Cells
19.1.1Cell Usage
ANTENNA cells are n-type diffusion diode cells used to fix antenna violations.
19.1.2Cell Structure
Figure 19-1 shows the schematic of an ANTENNA cell.
Figure 19-1 ANTENNA Schematic
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19.1.3Cell Sizing
he sizing of this cell is different from all of the previous cells. ANTENNA cells do not have transistor sizes;
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instead they have diode area and perimeter values. When the layout is complete, the diode area and perimeter
values must be measured and added to the schematic.
he perimeter value is the perimeter of the n-type diffusion. It is not the perimeter of the cell. It is usually
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expressed in units of microns. For example, if the n-type diffusion has a length of 0.22μand a widthof 0.25μ,
then the perimeter value is 0.94μ (2 * length + 2 * width).
he area value is the area of the n-type diffusion. It is not the area of the cell. It can be expressed in units of
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microns, picometers, or femtometers. Using the sizes from the example above, the area value is 0.000000055μ,
0.055p, or 55f.
19.2 FILLCAP Cells
19.2.1Cell Usage
ILLCAP cells are fill cells with decoupling capacitance and no well taps. They are used to fill in gaps in a chip
F
where there are no cells.
19.2.2Cell Structure
Figure 19-2 shows the schematic of a FILLCAP cell.
Figure 19-2 FILLCAP Schematic
19.2.3Cell Sizing
or FILLCAP cells, simply set the transistor width and length equal to the sizes in layout. Use the ‘no_conn’
F
symbol to tie off the VPW net.
20 ATK CELLS
tarting with 45nm, the ATK library is moving into the Base library. This section describes how to design all of
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the ATK cells.
There are five basic types of ATK cells as shown in Table 20-1.
Cell Type Cell Topologies
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Full Adders ADDFCIN, ADDFH
Booth Encoders BENC
Booth Muxes BMXIT, BMXT
Carry Generators CGENCIN, CGENCON, CGENI, CGEN
Compressors CMPR42
Table 20-1 ATK Cell Types
20.1 Full Adders
There are two full adder cell topologies that were previously a part of the ATK library: ADDFCIN and ADDFH.
20.1.1ADDFCIN
20.1.1.1 Cell Usage
ADDFCIN cells are adder cells with an inverted carry input.
20.1.1.2 Cell Structure
Figure 20-1 shows the schematic of an ADDFCIN cell.
Figure 20-1 ADDFCIN Schematic
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0.1.1.3
2 Cell Sizing
The output stage of an ADDFCIN cell is an inverter. Size the output inverters just like a single-stage inverter. For
example, an ADDFCIN_X1M cell has output inverters with the same sizes as INV_X1M. Now that the output
inverters have been sized, use the stick diagram to determine the lengths of the input wires, the internal wires,
and the output wires.
he eight transmission gates can not be folded. Only the two output inverters can be folded. All eight
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transmission gates should be sized the same. They should all be set to the largest single finger transmission
gate size.
he p-channel size of the five input inverters should be set equal to the largest single finger p-channel transistor
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size. The n-channel transistor sizes need to be determined by simulation. The inverters driving ‘na’ and ‘ba’
should be sized the same as a starting point. Also, the inverters driving ‘ci’ and ‘cinb’ should be sized the same
as a starting point. The inverter driving ‘nb’ should be sized the same as the inverter driving ‘ci’ as a starting
point.
20.1.2ADDFH
20.1.2.1 Cell Usage
DDFH cells are high speed adder cells. They are similar to the ADDFCIN cells except that these cells have a
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non-inverting carry input.
20.1.2.2 Cell Structure
Figure 20-2 shows the schematic of an ADDFH cell.
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Figure 20-2 ADDFH Schematic
20.1.2.3 Cell Sizing
The ADDFH cells should be sized the same as the ADDFCIN cells with the same drive strength.
20.2 Booth Encoders
20.2.1BENC
20.2.1.1 Cell Usage
BENC cells are radix-4 booth encoder cells. They are used in conjunction with booth muxes.
20.2.1.2 Cell Structure
igure 20-3 shows the schematic of a BENC cell. Figure 20-4 shows the high drive strength version. The high
F
drive strength schematic adds an extra inverter stage because neither the transmission gates nor the AOI21
gates can fold. In the high drive strength version, the OAI21 gates can not be folded.
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Figure 20-3 BENC Schematic
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Figure 20-4 BENC High Drive Strength Schematic
0.2.1.3
2 Cell Sizing
The output stage of a BENC cell is an inverter. Size the output inverters just like a single-stage inverter. For
example, a BENC_X2M cell has output inverters with the same sizes as INV_X2M. Now that the output inverters
have been sized, use the stick diagram to determine the lengths of the input wires, the internal wires, and the
output wires.
oth AOI21 gates should be sized the same. These gates can not be folded. For the smaller drive strengths, use
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a stage effort of four. When a stage effort of four results in folded gates, use a higher stage effort up to a stage
effort of 5.5 to maintain a single fold. When a stage effort of 5.5 results in folded gates, the cell topology needs
to be modified as shown in Figure 20-4.
hen using the schematic shown in Figure 20-4, size the inverters driving nets ‘a’ and ‘s’ using a stage effort of
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four. Use a stage effort of four to size the OAI21 gates. When a stage effort of four results in folded OAI21 gates,
use a higher stage effort to maintain a single fold.
In either the AOI21 or OAI21 case, the beta ratio needs to be determined by simulation.
se a stage effort of four to size the inverter that drives net ‘bm0’ and the transmission gate that it drives. The
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inverter that drives net ‘nm0’ and the transmission gate that it drives should be sized the same as the other
inverter and transmission gate. The beta ratios of the inverters need to be determined by simulation. These
inverters and transmission gates can not be folded. Increase the stage effort to 5.5 before adding an inverter to
the path as shown in Figure 20-4. The n-channel transistor of the inverter that drives output ‘X2’ can be changed
to improve the delay.
he inverter driven by input ‘M1’ should be sized using a stage effort of three. This stage effort is used because
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although it is a “one-zero fork”, it is also used to drive the AOI21 or OAI21 gate. The beta ratio of this inverter
needs to be determined by simulation.
he inverter driven by input ‘M2’ should be sized using a stage effort of four. The beta ratio of this inverter needs
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to be determined by simulation.
20.3 Booth Muxes
There are two booth mux topologies that were previously a part of the ATK library: BMXIT and BMXT.
20.3.1BMXIT
20.3.1.1 Cell Usage
BMXIT cells are inverting radix-4 booth mux cells. They are used in conjunction with booth encoders.
20.3.1.2 Cell Structure
Figure 20-5 shows the schematic of a BMXIT cell.
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Figure 20-5 BMXIT Schematic
0.3.1.3
2 Cell Sizing
The output stage of a BMXIT cell is an inverter. Initially, size the output inverter just like a single-stage inverter.
For example, a BMXIT_X2M cell has an output inverter with the same sizes as INV_X2M. The p-channel or
n-channel transistor size can be changed later if it improves the cell timing. Now that the output inverters have
been sized, use the stick diagram to determine the lengths of the input wires, the internal wires, and the output
wire.
he inverter – transmission gate – transmission gate triplet should be sized as a set using a stage effort of four.
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The inverters driven by inputs ‘AN’ and ‘SN’ should be sized the same. The beta ratio of these inverters needs to
be determined by simulation. Also, all six transmission gates should be sized the same. Sometimes the two
transmission gates closest to the outputs will need to be downsized due to the layout. These inverters and
transmission gates can not be folded. When a stage effort of four results in folded gates, use a higher stage
effort to maintain a single fold.
se a stage effort of two to size the inverters that are driven by inputs ‘D0’, ‘D1’, and ‘X2’. The beta ratio of these
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inverters needs to be determined by simulation.
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20.3.2 BMXT
20.3.2.1 Cell Usage
BMXT cells are non-inverting radix-4 booth mux cells. They are used in conjunction with booth encoders.
20.3.2.2 Cell Structure
igure 20-6 shows the schematic of a BMXT cell. The cell is similar to the BMXIT cell except this cell has an
F
extra inverter stage between the transmission gates.
Figure 20-6 BMXT Schematic
0.3.2.3
2 Cell Sizing
The output stage of a BMXT cell is an inverter. Initially, size the output inverter just like a single-stage inverter.
For example, a BMXT_X2M cell has an output inverter with the same sizes as INV_X2M. The p-channel or
n-channel transistor size can be changed later if it improves the cell timing. Now that the output inverters have
been sized, use the stick diagram to determine the lengths of the input wires, the internal wires, and the output
wire.
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he inverter – transmission gate pairs that drive net ‘npp’ should be sized as a set using a stage effort of four.
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The inverters that drive nets ‘nint0’ and ‘nint1’ should be sized the same using the inverter ‘M’ beta ratio. Also,
the two transmission gates that drive net ‘npp’ should be sized the same. These inverters and transmission
gates can not be folded. When a stage effort of four results in folded gates, use a higher stage effort to maintain
a single fold.
he four transmission gates closest to the inputs should have the same sizes as the other two transmission
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gates. The beta ratio of the inverters driven by inputs ‘AN’ and ‘SN’ need to be determined by simulation.
Generally, this beta ratio is greater than the ‘M’ beta ratio.
se a stage effort of two to size the inverters that are driven by inputs ‘D0’, ‘D1’, and ‘X2’. The beta ratio of these
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inverters needs to be determined by simulation.
20.4 Carry Generators
here are four carry generator topologies that were previously a part of the ATK library: CGENCIN, CGENCON,
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CGENI, and CGEN.
20.4.1CGENCIN
20.4.1.1 Cell Usage
CGENCIN cells are carry generator cells with an inverted carry input.
20.4.1.2 Cell Structure
Figure 20-7 shows the schematic of a CGENCIN cell.
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Figure 20-7 CGENCIN Schematic
20.4.1.3 Cell Sizing
Folding summary (folding is not allowed on any device unless explicitly stated here):
1. Folding allowed on output transmission gates.
2. Folding allowed on inverters driven by CIN and driven by “nb”.
Sizing constraints:
1. Four non-output transmission gates are sized identically to each other. Maintain a beta ratio of at least 1.
2. Inverters driven by B, A, and “na” may be sized independently, maintaining a beta ratio of 1 or higher.
3. Inverters driven by CIN and “nb” must be sized identically, in order to maintain similar drive
characteristics for the two possible output paths.
4. The nfet or pfet of any inverter driving the input of a transmission gate cannot be smaller than the nfet or
pfet of the receiving transmission gate.
20.4.2CGENCON
20.4.2.1 Cell Usage
CGENCON cells are carry generator cells with an inverted carry output.
20.4.2.2 Cell Structure
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Figure 20-8 shows the schematic of a CGENCON cell.
Figure 20-8 CGENCON Schematic
0.4.2.3
2 Cell Sizing
Size the CGENCON cell the same as the CGENCIN cell. The only topology difference is that this cell does not
have an inverter driven by net ‘nb’.
20.4.3CGENI
20.4.3.1 Cell Usage
GENI cells are carry generator cells with an inverted carry output. They have the same function as the
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CGENCON cells, but these cells has a higher density and fewer transistors.
20.4.3.2 Cell Structure
Figure 20-9 shows the schematic of a CGENI cell.
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Figure 20-9 CGENI Schematic
0.4.3.3
2 Cell Sizing
The CGENI cell is very easy to size, since this cell is a single-stage cell. All of the p-channel transistors should be
the same size and all of the n-channel transistors should be the same size. The transistor sizes should be sized
the same as the AOI22 cell. Sometimes the layout will not support the same sizes as the AOI22 cell. In that
case, downsize both the p-channel and n-channel transistors to maintain the proper beta ratio.
20.4.4CGEN
20.4.4.1 Cell Usage
CGEN cells are carry generator cells.
20.4.4.2 Cell Structure
Figure 20-10 shows the schematic of a CGEN cell. It is a CGENI cell with an output inverter.
Figure 20-10 CGEN Schematic
0.4.4.3
2 Cell Sizing
The output stage of a CGEN cell is an inverter. Size the output inverter just like a single-stage inverter. For
example, a CGEN_X2M cell has an output inverter with the same sizes as INV_X2M. Now that the output inverter
has been sized, use the stick diagram to determine the lengths of the input wires, the internal wires, and the
output wire.
ize the remaining transistors (the input stage) using a stage effort of four. Use the same beta ratio as the CGENI
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cell. However, these transistors can not be folded. When a stage effort of four results in folded transistors, use a
higher stage effort to maintain a single fold.
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20.5 Compressors
CMPR42 is the only cell topology that was previously a part of the ATK library.
20.5.1CMPR42
20.5.1.1 Cell Usage
CMPR42 cells are 4-2 compressor cells.
0.5.1.2
2 Cell Structure
There are two cell structures for CMPR42 cells depending on the number of tracks, the process, and whether or
not Metal 2 can be used for wiring within the cell.
If the number of tracks is small (roughly less than twelve tracks) or if Metal 2 can not be used in the cell, then the
CMPR42 cell structure is simply two ADDF cells tied back-to-back. In the sc library, this cell is called
“CMPR42_ALT”.
n the other hand, if there are many tracks and Metal 2 can be used in the cell, then the structure shown in
O
Figure 20-11 can be used.
or 32nm and newer process technologies, the CMPR42_ALT topology is used in all cases. The CMPR42
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topology shown in Figure 20-11 is not used because it creates large glitches at small process technologies.
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Figure 20-11 CMPR42 Schematic
here are many other possible cell topologies for the CMPR42 cell. These are just a couple of ways that have
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been used in previous libraries. Other possibilities include using NAND2 and OAI21 structures to form the four
input XNOR instead of using transmission gates.
0.5.1.3
2 Cell Sizing
The sizing depends on the topology used. If the topology is ADDF based, simply use the ADDF sizing
techniques to size the CMPR42 cell. If the topology is the one shown in Figure 20-11, size the cell initially using
the techniques of Logical Effort and then simulate and retune to find the minimum of the maximum delay from
each input to each output.
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21 LVS GUIDELINES
21.1 General Recommendations
21.1.1Layout N-Well and Substrate Layers
urrent standard cell practice dictates that VNW and VPW layers be explicitly indicated in layout using
C
associated text on the respective layers. Simply put, both n-well and substrate pins must exist in the layout. The
source library schematics and symbols serve as the reference, and layout text should match that of the
schematic.
21.1.2Schematic 1-Ohm Resistors
Well and substrate connections should be modeled in schematics using 1-ohm resistors.
21.1.3CDL Netlist *.CONNECT Statements
Cell-level CDL netlists should use *.CONNECT statements to model well and substrate connections.
21.1.4Transistor Folding
urrent ARM schematics, drawn using Cadence tools, may not always have the ability to represent the exact
C
layout configuration with respect to device folding. Netlists generated from Cadence Virtuoso will usually be
hierarchical in nature and may also share the same inability to represent device fold configuration in some cases.
DA LVS tools generally have the ability to recognize and merge folded devices, and can perform adequate
E
comparison for internal development. However, some customers use LVS flows that reject the ability to
recognize and merge folded devices. Thus, they require that ARM provide netlists that reflect the exact layout
configuration with respect to device folding.
his is accomplished by (1) Verifying ARM hierarchical schematic vs. layout as usual, with device merging
T
enabled, as proof that layout conforms to the “golden” hierarchical schematic. (2) Generating a flattened
transistor-level netlist directly from the layout by using an LVS tool such as Calibre or Hercules. (3) Verifying that
the flattened transistor netlist matches the layout by using an LVS tool.
In the case of cells that do not contain devices but do contain tap structures that need to be modeled with
*.CONNECT statements, flattened netlist generation cannot be accomplished with current LVS tools. Use the
Cadence-generated netlist, instead. These cells will be covered in the cell-specific guidelines, below.
21.2 Known Limitations
isted below are a summary of foundry and EDA-tool issues for LVS on base library cells, followed by specific
L
issues and workarounds (if needed) for each base library topology.
21.2.1Foundry-provided LVS Deck Issues
In some cases, foundry-provided lvs decks may be missing definitions for the well or substrate text layers. Past
methodology has been to use an altered lvs deck to enable recognition of these text layers.
21.2.2EDA tool issues
sers should be aware that most LVS tools will not create a connectivity netlist from layout that does not contain
U
semiconductor devices. This limitation affects certain layout finishing cell families in the base library, as noted
below.
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21.3 Cell-Specific Guidelines
nly cells that require special treatment during cell-level LVS will be addressed in this section. The reader may
O
assume that all other cell families can be verified without special accommodation.
21.3.1Layout Finishing Cells
21.3.1.1 ENDCAPTIE
urrently, neither Calibre nor Hercules LVS tools have the ability to perform cell-level LVS compare on this
C
topology, due to its lack of semiconductor devices. However, note that the CDL netlist should have the following
format in order to support block-level LVS:
subckt ENDCAPTIE VDD VNW VPW VSS
.
*.CONNECT VNW VDD
*.CONNECT VPW VSS
.ends ENDCAPTIE
21.3.1.2 FILL
urrently, neither Calibre nor Hercules LVS tools have the ability to perform cell-level LVS compare on this
C
topology, due to its lack of semiconductor devices. However, note that the CDL netlist should have the following
format in order to support block-level LVS:
subckt FILL VDD VNW VPW VSS
.
.ends FILL
21.3.1.3 FILLTIE
urrently, neither Calibre nor Hercules LVS tools have the ability to perform cell-level LVS compare on this
C
topology, due to its lack of semiconductor devices. However, note that the CDL netlist should have the following
format in order to support block-level LVS:
subckt FILLTIE VDD VNW VPW VSS
.
*.CONNECT VNW VDD
*.CONNECT VPW VSS
.ends FILLTIE
21.3.1.4 FILLTIESB
urrently, neither Calibre nor Hercules LVS tools have the ability to perform cell-level LVS compare on this
C
topology, due to its lack of semiconductor devices. However, note that the CDL netlist should have the following
format in order to support block-level LVS:
subckt FILLTIESB VDD VNW VPW VSS
.
*.CONNECT VSB VSS
.ends FILLTIESB
22 ELECTROMIGRATION
22.1 Definition
lectromigration is also known as metal migration or more commonly, EM. It is the movement of metal ions in a
E
conductor due to the influence of an electric field and the collision of electrons with atoms that leads to
momentum transfer. Metal atoms gather in the direction of current flow which causes the conductor to shrink in
width or even break over time. Along with metal, contacts and vias also become degraded due to
electromigration.
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22.2 Causes
lectromigration is caused by heat and current density. High temperatures increase the amount of electron
E
scattering against the atoms of the conductor. High current density increases the number of electrons that are
scattering.
here are typically three current densities that can cause electromigration failures: peak current, average current,
T
and rms (root mean squared) current. Process design rules have specific equations for the maximum allowed
values of these currents for metal, contacts, and vias.
22.3 Failure Rate
rocess design rules typically express the percentage of devices that will fail due to electromigration, assuming
P
that the EM design rules are followed. The failure rate is expressed either as a percentage that will fail after a
specific number of hours or in terms of FIT (failure unit). An example of the former is a 0.1% failure rate after
100K hours. An example of the latter is 10 FIT, which is ten failures per billion hours or equivalently 0.1% failure
rate after ten years. Ten years is approximately 100K hours. 1 FIT is one failure per billion hours.
22.4 Prevention
he best way to prevent EM from ruining circuits is to follow the guidelines that are given for each process. The
T
largest cells might need to have metal widths that are larger than minimum and have more than one contact or
via.
22.5 Pre-Analysis
efore EM analysis is run, the inverters need to be layed out a couple of different ways: C-shaped outputs and
B
H-shaped outputs. After they have been layed out, RC timing simulations need to be run using SPICE to
determine which layout type results in better performance for each beta ratio and drive strength. The H-shaped
output should be better for low drive strength inverters and the C-shaped output should be better for high drive
strength inverters. The point of this analysis is to determine the point where C-shaped outputs become preferred
over H-shaped outputs.
22.6 Analysis
he best way to determine which cells need to have larger metal widths and/or more contacts and vias is to run
T
SPICE simulations. The first simulation is needed to determine the output load. The other simulation is needed
to measure the current. The current values are then compared to the EM design rules for the process. If either
the peak, average, or rms current is greater than the values specified in the design rules, the metal width needs
to increase and/or there needs to be more contacts or vias. If the metal width needs to increase, the C-shape
metal of a C-shaped output needs to increase or the “–“ shaped metal of an H-shaped output needs to increase.
The width of the metal fingers needs to be set so that the fingers can drive X2 DC and RMS current.
This analysis applies to clock or signal nets only. It does not apply to supply nets.
22.6.1Schematic
he schematic that is used for analyzing EM for inverters is shown in Figure 21-1. The voltage sources ‘Vp’ and
T
‘Vn’ are used only to measure current and are set to zero volts.
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Figure 21-1 EM Analysis Schematic for Inverters
he schematic that is used for analyzing EM for nand2 cells is shown in Figure 21-2. The voltage sources ‘Vp’
T
and ‘Vn’ are used only to measure current and are set to zero volts.
Figure 21-2 EM Analysis Schematic for Nand2 Cells
he ‘mult =4’ blocks are ‘imult’ symbols in the armPrimitives library. They are used to generate a fanout of four
T
for the first three inverters. In Figure 20-1, ‘wp_inv’ and ‘wn_inv’ are the p-channel and n-channel transistor sizes
of the inverter that is being analyzed for EM. In Figure 20-2, ‘wp_nand2’ and ‘wn_nand2’ are the p-channel and
n-channel transistor sizes of the nand2 that is being analyzed for EM. Also in Figure 20-2, ‘wp_inv’ and ‘wn_inv’
have a total device width equal to the sum of ‘wp_nand2’ and ‘wn_nand2’ and they have a beta ratio equal to the
‘m’ or ‘x’ beta ratio. ‘load’ is a parameter that is swept in the first SPICE simulation. In the second SPICE
simulation, ‘load’ is set to the value determined in the first simulation.
ther high drive cells, such as nor cells, might need to be analyzed for EM depending on the results of the EM
O
analysis for inverters and nand cells. If the largest nand cells need to have larger than minimum width metal for
EM, then the largest nor cells need to be analyzed.
22.6.2Load Simulation
he first SPICE simulation determines the output capacitance that is used in the second simulation. The details
T
of the simulation are given below with sample library parameters in parenthesis.
● slow transistor models (SS)
● high temperature (125° C)
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● 9
0% of nominal Vdd of the highest voltage domain supported by the product operating condition
definition (1.08 V)
● t he lowest threshold voltage that the library will support (NVT because LVT is not available in the sample
library)
● square wave input: rises at 0 ns, falls at 1 ns
● 2 ns simulation time
● ‘Vp’ and ‘Vn’ are set to zero volts
he ‘load’ parameter is swept until the edge rate of the slower of the rising or falling edge of the ‘out’ signal is
T
200 ps, which is 20% of the cycle time. Note that the clock cycle time for this example is 1 ns. We simulate a
rising edge in one clock cycle and a falling edge in the other clock cycle because this models the worst case for
a 100% activity factor. The edge rates are measured ten percent of Vdd to ninety percent of Vdd (0.09 V to 0.81
V for the sample library). This ‘load’ value is then used in the second SPICE simulation.
22.6.3Current Simulation
he second SPICE simulation determines the values of the peak, average, and rms currents. The details of the
T
simulation are given below with the sample library parameters in parenthesis.
● fast transistor models (FF)
● temperature determined by EM guidelines for each process (110° C for the sample library)
● n
ominal Vdd of the highest voltage domain supported by the product operating condition definition (1.2
V for TSMC 65G)
● t he lowest threshold voltage that the library will support (NVT because LVT is not available in the sample
library)
● square wave input: rises at 0 ns, falls at 1 ns
● 2 ns simulation time
● ‘Vp’ and ‘Vn’ are set to zero volts
● ‘load’ is set equal to the value determined in the first SPICE simulation
2.6.3.1
2 Average Current
The average current is measured using the following two lines in SPICE.
.measure tran avgip avg I1(vp) from=0ns to=2ns
.measure tran avgin avg I1(vn) from=0ns to=2ns
ompare the larger of ‘avgip’ and ‘avgin’ to the average current values specified in the Design Rules for the
C
process. The average current limit is a unidirectional current limit that applies to Metal 1, Via 1, and contacts. It
can also apply to Metal 2 when used in standard cells.
2.6.3.2
2 Peak Current
The peak current is measured using the following two lines in SPICE.
.measure tran maxip max I1(vp) from=0ns to=2ns
.measure tran maxin max I1(vn) from=0ns to=2ns
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ompare the larger of ‘maxip’ and ‘maxin’ to the average current values specified in the Design Rules for the
C
process. It is rare to have EM violations due to peak current. The peak current limit is a unidirectional current
limit that applies to Metal 1. It can also apply to Metal 2 when used in standard cells.
2.6.3.3
2 RMS Current
The rms current is measured using the following line in SPICE.
.measure tran rmsi rms I1(cout) from=0ns to=2ns
ompare ‘rmsi’ to the rms current values specified in the Design Rules for the process. Use the temperature rise
C
specified by the customer for Joule heating. The rms current limit is a bidirectional current limit that applies to all
metal layers.
22.7 Sample Library Analysis
The following EM analysis was run for the sample library.
22.7.1Understanding the Design Rules
For the sample library, the maximum DC current rules are really the average current rules.
ther fabs and processes will have their own set of EM guidelines. It is essential to read the EM guidelines for
O
each process carefully, as some of the terminology will vary depending on the process.
22.7.2Applying the Design Rules
ince the sample library uses 110° C as the junction temperature; the second simulation, where the current is
S
measured, is run at 110° C.
2.7.2.1
2 Average Current
The average current is measured using the following two lines in SPICE.
.measure tran avgip avg I1(vp) from=0ns to=2ns
.measure tran avgin avg I1(vn) from=0ns to=2ns
or Metal 1 only, compare the larger of ‘avgip’ and ‘avgin’ to the average current values specified in the table in
F
the library design document. Table 21-1 shows the minimum values for ‘w’, the width of the metal line for the
sample library.
Metal Layer w (width of the metal line)
Metal 1 0.09 um
Metal 2 – Metal 7 0.10 um
Metal 8 – Metal 9 0.40 um
Table 21-1 TSMC 65G Minimum Metal Widths
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If the current value is larger in the table in the TSMC document than the value measured in SPICE for a cell, then
use the minimum Metal 1 width for that cell. If the current value is smaller in the table in the TSMC document
than the value measured in SPICE for a cell, increase the ‘w’ value in 0.01 um increments until the value
measured in SPICE is smaller than the value in the table in the TSMC document. The increased ‘w’ value is the
size that the Metal 1 line must be increased to for that particular cell. Metal 2 and up do not need to follow the
average current guidelines unless they are used in standard cells.
or contacts, compare the larger of ‘avgip’ and ‘avgin’ to the average current values specified in the table in
F
Section 9.1.1.3 “Maximum DC Current for Contacts and Vias (Tj = 110° C)” of the TSMC document to findthe
number of contacts per finger. Divide the larger of ‘avgip’ and ‘avgin’ by 0.296 mA (the value in the table for
TSMC 65G) and round up. For instance, if ‘avgip’ is 0.24 mA and ‘avgin’ is 0.22 mA, divide 0.24 by 0.296.
Round this number up to one; only one contact per finger is necessary. As another example, if ‘avgip’ is 0.3 mA
and ‘avgin’ is 0.4 mA, divide 0.4 by 0.296. Round this number up to two; two contacts per finger are necessary
for this example.
or vias, compare the larger of ‘avgip’ and ‘avgin’ to the average current values specified in the table in Section
F
9.1.1.3 “Maximum DC Current for Contacts and Vias (Tj = 110° C)” of the TSMC document to find the numberof
Via 1’s needed for supply. Divide the larger of ‘avgip’ and ‘avgin’ by 0.158 mA (the value in the table for TSMC
65G) and round up. For instance, if ‘avgip’ is 0.12 mA and ‘avgin’ is 0.11 mA, divide 0.12 by 0.158. Round this
number up to one; only one Via 1 for supply is necessary. As another example, if ‘avgip’ is 0.15 mA and ‘avgin’
is 0.2 mA, divide 0.2 by 0.158. Round this number up to two; two Via 1’s for supply are necessary for this
example.
2.7.2.2
2 Peak Current
The peak current is measured using the following two lines in SPICE.
.measure tran maxip max I1(vp) from=0ns to=2ns
.measure tran maxin max I1(vn) from=0ns to=2ns
In the TSMC 65G Design Rules document, two subsections describe measuring the peak current: Section 9.1.3.1
“Pulsed Signal Terminology” and Section 9.1.3.4 “Peak Current”. Section 9.1.3.1 gives definitions of peak
current, period (tau), and duration (tD) . This sectionalso contains waveforms that show how to measure these
values. Section 9.1.3.4 gives a definition of peak current in terms of a peak DC current, the period, and duration.
This section also contains a table of peak DC current for each metal layer.
ince the TSMC 65G EM rules are in terms of peak DC current and not peak current, the peak current that is
S
measured in SPICE (‘maxip’ and ‘maxin’) must be converted to an equivalent peak DC current. The following
SPICE commands show how to do this conversion.
.param tau=2n
.measure tran current_widthp trig I1(vp) Val = 'maxip*0.5' rise=1 targ I1(vp) Val = 'maxip*0.5' fall=1
.measure tran current_widthn trig I1(vn) Val = 'maxin*0.5' rise=1 targ I1(vn) Val = 'maxin*0.5' fall=1
.measure duty_ratiop param='current_widthp/tau'
.measure duty_ration param='current_widthn/tau'
.measure peakdcip param='maxip*sqrt(duty_ratiop)'
.measure peakdcin param='maxin*sqrt(duty_ration)'
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he first line sets the parameter of tau (the period) to 2 ns. The next two lines measure the duration (tD) of the
T
current waveform through the p-channel and n-channel transistors of the output, respectively. The following two
lines divide the duration (tD) by the period (tau). This value is referred to as ‘r’ or the ‘duty ratio’ in the TSMC 65G
EM rules. The last two lines find the peak DC current for the p-channel and n-channel transistors respectively.
These calculations are based on the equation Ipeak equals Ipeak_DCdivided by the square root of r,found in Section
9.1.3.4 in the TSMC 65G EM rules.
If the value for Ipeak_DCin the table in Section9.1.3.4 is larger than the maximum of ‘peakdcip’ and ‘peakdcin’, then
the peak current EM rules are not violated. If the maximum of ‘peakdcip’ and ‘peakdcin’ is larger than the value
for Ipeak_DC, increase the ‘w’ value in 0.01 um incrementsuntil the value measured in SPICE is smaller than the
value in the table in the TSMC document. The increased ‘w’ value is the size that the metal line must be
increased to for that particular cell.
he TSMC 65G Design Rules document states that peak current is not an issue for contacts and vias. Therefore,
T
the number of signal Via 1’s is always one.
2.7.2.3
2 RMS Current
The rms current is measured using the following line in SPICE.
.measure tran rmsi rms I1(cout) from=0ns to=2ns
In the TSMC 65G Design Rules document, rms current is discussed in Section 9.1.3.3 “Root-Mean-Square
Current”. This section gives a definition of rms current and contains tables of current for each metal layer.
ompare ‘rmsi’ to the rms current values specified in the tables. Use 10° C as the temperature rise due to Joule
C
heating, referred to as ΔT in the TSMC 65G design rules document.
If the value for Irmsin the table in Section 9.1.3.3.1is larger than ‘rmsi’, then the rms current EM rules are not
violated. If ‘rmsi’ is larger than the value for Irms, increase the ‘w’ value in 0.01 um incrementsuntil the value
measured in SPICE is smaller than the value in the table in the TSMC document. The increased ‘w’ value is the
size that the metal line must be increased to for that particular cell.
he TSMC 65G Design Rules document states that rms current is not an issue for contacts and vias. Therefore,
T
the number of signal Via 1’s is always one unless more are required by other design rules.
22.8 Final Comments
fter the average, peak DC, and rms currents have been measured and compared to the design rules, use the
A
worst case metal width that is found. As an example, a particular cell is required to have a Metal 1 width of 120
nm for average current rules, 90 nm for peak DC current rules, and 100 for rms current rules. The worst case is
the average current rule, so the Metal 1 width needs to be set to 120 nm for this particular cell.
s a practical matter, when running EM analysis, start with the largest inverter and go down to the next smaller
A
inverter until you find the one that can have minimum width metal and single contacts and vias. All of the cells
that are smaller will not have EM problems. Any cell that uses this size of inverter on its output stage should
follow the EM characteristics determined for the stand-alone inverter. If the smallest stand-alone inverter which
needed to be upsized is smaller than the highest drive versions of other logical functions in the library, then the
EM analysis described above needs to be run for these topologies as well. Start with the logical function that
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as the lowest logical effort for the output stage. There is no need to run EM analysis on any topology whose
h
output stage’s logical effort is higher than the logical effort of a cell that passes EM with no upsizing.
23 CONCLUSION
esigning high quality libraries can be achieved by understanding how the cells are used, which topologies are
D
optimal, and which device sizes give the best power, performance, and area.
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