Department of Electronics and Communication Engineering

Jnanaprabha, Virgo Nagar Post, Bengaluru- 560049

LABORATORY MANUAL
2023-2024

Semester : III Semester

Subject : Analog and Digital System Design Lab

code : BECL305

Name of the Student :

University Seat Number :
Batch :
 INSTITUTE VISION AND MISSION

VISION
The East Point College of Engineering and Technology aspires to be a globally acclaimed
institution, recognized for excellence in engineering education, applied research and
nurturing students for holistic development.

MISSION
M1: To create engineering graduates through quality education and to nurture innovation,
creativity and excellence in teaching, learning and research

M2: To serve the technical, scientific, economic and societal developmental needs of our
communities

M3: To induce integrity, teamwork, critical thinking, personality development and ethics in
students and to lay the foundation for lifelong learning
 Department of Electronics and communication Engineering
DEPARTMENT VISION AND MISSION
VISION

The Department aspires to be a centre of excellence in Electronics and Communication

Engineering to develop competitive and ethical professionals through holistic development.

MISSION

M1: To impart quality education and provide a conducive environment for innovation and
Research
M2: To develop skills to meet the scientific, technological and socio-economic needs

M3: To inculcate professional ethics, team work, leadership qualities and lifelong learning

PROGRAM EDUCATIONAL OBJECTIVES (PEO’s):

PEO-1: To produce graduates to have successful professional career with the acquired
knowledge in Electronics and Communication Engineering to analyse, design, develop and
implement electronic systems
PEO-2: To produce graduates who apply their engineering skills and develop ingenious
solutions for real world problems
PEO-3: To produce graduates who can exhibit leadership qualities, ethical values and adapt to
current trends by engaging in lifelong learning.

PROGRAM SPECIFIC OUTCOMES (PSO’s):

PSO1: To conceptualise, model, design, simulate, analyse, develop, test electronic and
communication systems and solve technical problems arising in the field of Electronics and
Communication Engineering.

PSO2: To specialize in the areas of Electronics and Communication Engineering such as

Analog and Digital electronics, communication, Signal processing, VLSI systems, Embedded
Systems and IOT.
 PSO3: To demonstrate building and testing of electronics and communication systems and
evaluate their performance and efficiency using appropriate tools and techniques.
PROGRAMME OUTCOMES (PO)
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyse complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modelling to complex
engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
Engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
12. Life -long learning: Recognize the need for and have the preparation and ability to engage in
independent and life -long learning in the broadest context of technological change.
 COURSE LEARNING OBJECTIVES

Course Learning Objectives:

This course will enable students to:

 Understand the electronic circuit schematic and its working

 Realize and test amplifier and oscillator circuits for the given specification
 Realize the opamp circuits for the applications such as DAC, implement mathematical
functions and precision rectifiers.
 Study the static characteristics of SCR and test the RC triggering circuit.
 Design and test the combinational and sequential logic circuits for their functionalities
 Use the suitable ICs based on the specifications and functions.

COURSE OUTCOMES

On the completion of this laboratory course, the students will be able to:

 Design and analyze the BJT/FET amplifier and oscillator circuits.

 Design and test Opamp circuits to realize the mathematical computations, DAC and precision
rectifiers.
 Design and test the combinational logic circuits for the given specifications.
 Test the sequential logic circuits for the given functionality.
 Demonstrate the basic circuit experiments using 555 timer.
 Analog and Digital System Design
Laboratory
Effective from Academic year 2022-2023
SEMESTER-III
Subject Code BECL305 CIE Marks 50

Number of Lecture Hours/Week 0:0:2 SEE Marks 50

L:T:P
Total Number of Lab Hours 32 Exam Hours 3 Hours

Credits – 1
Course Learning Objectives :

This laboratory course enables students to:

 Understand the electronic circuit schematic and its working
 Realize and test amplifier and oscillator circuits for the given specification
 Realize the opamp circuits for the applications such as DAC, implement mathematical
functions and precision rectifiers.
 Study the static characteristics of SCR and test the RC triggering circuit.
 Design and test the combinational and sequential logic circuits for their functionalities
 Use the suitable ICs based on the specifications and functions.

Syllabus:
PART A : HARDWARE EXPERIMENTS
Design and set up the BJT common emitter voltage amplifier with and without
1 feedback and determine the gain- bandwidth product, input and output
impedances.

2 Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator and
iii) RC-Phase shift oscillator
3 Design and set up the circuits using op-amp: i) Adder, ii) Integrator,
iii) Differentiator and iv) Comparator
4 Design and implement (a) Half Adder & Full Adder using basic gates and
NAND gates, (b) Half subtractor & Full subtractor using NAND gates, (c) 4-
variable function using IC74151(8:1MUX).
5 Realize (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD
to Excess-3 code conversion and vice versa
6 a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and
iii) T-Flip-Flop b) Realize the shift registers using IC7474/7495: (i) SISO (ii) SIPO
(iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter
7 Realize a) Design Mod – N Synchronous Up Counter & Down Counter using
7476JK Flip-flop b) Mod-N Counter using IC7490 / 7476 c) Synchronous counter
using IC74192
8 Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) for a 4-bit binary
input using toggle switches (ii) by generating digital inputs using mod-16

Demonstration Experiments ( For CIE )

9 Design and test the following using 555 timer

i)Monostable and ii)Astable Multivibrator
10 Design and Test the second order Active Filters and plot the frequency response,
i) Low Pass and ii) High Pass Filter
11 Design and Test a Regulated Power supply

12 Design and test an audio amplifier by connecting a microphone input and observe the
output using a loud speaker.
Additional Experiments

13 Illustration of (a) AM modulation and demodulation and display the signal and its
spectrum. (Use MATLAB/SCILAB)
14 Illustration of FM modulation and demodulation and display the signal and its spectrum.
(Use MATLAB/SCILAB)
 Index
Sl EXPERIMENTS LIST CO PO RBT PAGE
No NO.
HARDWARE EXPERIMENTS
Design and set up the BJT common emitter voltage
amplifier with and without feedback and determine the
1 gain- bandwidth product, input and output impedances. CO1 PO1 L4 1-3
Design and set-up BJT/FET i) Colpitts Oscillator, ii)
2 Crystal Oscillator and iii) RC-Phase shift oscillator CO1 PO1 L4 4-12
Design and set up the circuits using op-amp: i)
3 Adder, ii) Integrator,iii) Differentiator and iv) CO2 PO2 L4 13-20
Comparator
Design and implement (a) Half Adder & Full
4 Adder using basic gates and NAND gates, (b) CO2 PO1 L4 21-31
Half subtractor & Full subtractor using NAND
gates, (c) 4- variable function using
IC74151(8:1MUX).
Realize (i) Binary to Gray code conversion & vice-
5 versa (IC74139), (ii) BCD to Excess-3 code CO3 PO2 L4 32-37
conversion and vice versa
a) Realize using NAND Gates: i) Master-Slave JK Flip-
Flop, ii) D Flip-Flop andiii) TFlip-Flop b) Realize the
6 shift registers using IC7474/7495: (i) SISO (ii) SIPO(iii) CO3 PO2 L3 38-45
PISO (iv) PIPO (v) Ring counter and (vi) Johnson
counter
Realize a) Design Mod – N Synchronous Up Counter &
Down Counter using
7 7476JK Flip-flop b) Mod-N Counter using IC7490 / CO4 PO2 L3 46-47
7476 c) Synchronous counter using IC74192
Design 4-bit R – 2R Op-Amp Digital to Analog Converter
(i) for a 4-bit binary input using toggle switches (ii) by
8 generating digital inputs using mod-16 CO4 PO2 L3 48-54

Demonstration Experiments ( For CIE )

9 Design and test the following using 555 timer 55-59
CO5 PO3 L3
i)Monostable and ii)Astable Multivibrator
Design and Test the second order Active Filters and plot
10 the frequency response, i) Low pass and CO2 PO3 L3 60-65
ii)High pass Filter
11 Design and Test a Regulated Power supply
C05 PO3 L3 66-67
Design and test an audio amplifier by connecting a
12 microphone input and observe the output using a loud C05 PO3 L3 68-69
speaker
Additional Experiments
Illustration of (a) AM modulation and demodulation and PO5 L4
13 display the signal and its spectrum. 70-71
(Use MATLAB/SCILAB)
Illustration of FM modulation and demodulation and PO5 L4
14 display the signal and its spectrum. 72-73
(Use MATLAB/SCILAB)
 LAB DO’S & DON’TS

DO’S
 Study the theory behind the experiment before coming to the lab
 Submit the record of previously conducted experiment

 Bring Observation book during laboratory hours

 Take the signature of the Staff in-charge before taking the components
 Note down the specifications of the devices and equipment used
 Avoid unnecessary talking while conducting the experiments
 Handle the equipment, devices and components carefully
 Checked and Okayed the circuit rigged – up by the staff in-charge before energizing
 Note down proper readings
 After the completion of the experiments switch off the power supply

 Do necessary calculations and draw the graph if any

 Show the results to the staff in-charge and get it approved
 Handover the components to the lab instructors

DONT’S

 Do not come late to the lab

 Do not exceed the voltage/current ratings of the device
 Do not energize the equipment and circuits without checked by the in-charge
 Do not spoil the connecting wires/patch chords
 Avoid loose connection and short circuits
 Do not misbehave in the computer laboratory.
 Don’t use chat rooms, online games or multiuser domains
 Analog & Digital System Design Lab Sub.Code:BECL305

EXPERIMENT NO. 1

CE AMPLIFIER USING VOLTAGE DIVIDER BIAS

Aim: Wiring ofa two stage BJT Voltage series feedback amplifier - with and without feedback and to
determine the respective Gain-Bandwidth product, input impedance and output impedance.

Components Required:
1. Transistor (SL100)-2 No.
2. Resistor (Carbon, 1/4W, 10%) – 9 Nos.
3. Capacitor (Ceramic Disk) – 3 Nos.
4. Capacitor (Electrolytic) – 1 Nos.

Equipment Required:
1. Spring Board – 1 No.
2. Function Generator -2MHz -1 No.
3. Dual Power Supply (0-30V, 2A, ±12V)-1 No.
4. Dual Channel CRO (20MHz)-1 No.
5. DRB – (1Ω - 100KΩ) - 1 No.
6. Patch Cards / Wires -10Nos.
7. Probes – 3 Nos.

Circuit diagram:

CE amplifier without feedback

DEPT. OF ECE,EPCET 1
 Analog & Digital System Design Lab Sub.Code:BECL305

Design: Let Vcc = 12V ; IC = 4mA ; VE = 2V ; VCEQ = 6V ; hfe (βDC) = 100.

To find RE :
Given VE = 2V. Therefore, RE = VE / IE  VE / IC = 500Ω Let RE = 470 ( standard)
To find RC :
From the collector loop writing KVL we get

VCC = ICRC + VCE + VE

 RC = (VCC – VCE – VE) / IC
RC = 1k

To find R1 and R2 :

The base current IB = IC / hfe = 4mA / 100 = 0.04mA
Let I1 be current through R1 and I1 be 10 times of IB
Writing the base loop KVL we get VB = VE + VBE = 2 + 0.7= 2.7V

Now, R1 = (VCC – VB) / I1

R1 = (12 - 2.7)/0.4m = 23.25 k R1 = 33 k (standard)
Also R2 = VB / (I1 – IB)
R2 = 2.7/0.36m =7.5 k


CE amplifier with feedback

DEPT. OF ECE,EPCET 2
 Analog & Digital System Design Lab Sub.Code:BECL305

Procedure:

1. Rig up the circuit as per the given circuit diagram.

2. Switch on the D.C. power supply = 12V is given to the circuit.
3. Check the D.C. conditions without any input signal and record in table 1.
4. Select sine wave input and set the input signal amplitude to 20mV frequency at 1kHz
constant, and observe the input / output waves on the CRO and adjust the input amplitude
such that the output is undistorted waveform. Calculate mid-band gain using

AV =Vo(p-p) / Vin(p-p).

5. Keeping the input amplitude constant, vary the frequency from 100Hz to 2MHz and note
down the corresponding output voltage (p-p) in the table 2.
6. Calculate gain in dB and plot the frequency response curve and find the bandwidth.

Observations:

Parameter VRC VCE VE VBE V

Theoretical

Practical

Frequency response with feedback:

Frequency ()Hz) Vo(p-p) AV = Vo/Vin(p-p) AV (dB) =20*log Av

Result:

DEPT. OF ECE,EPCET 3
 Analog & Digital System Design Lab Sub.Code:BECL305

EXPERIMENT NO. 02
A.COLPITT’S OSCILLATOR
Aim: Design and Testing of Colpitt‟s Oscillator for given frequency.

Components Required:
1. Transistor (SL100)-1 No.
2. Resistor (Carbon, 1/4W, 10%) – 4 Nos.
3. Capacitor (Ceramic Disk) – 5 Nos.
4. Capacitor (Electrolytic) – 1 Nos.
5. Potentiometer (0-1KΩ)-1 No.

Equipment Required:
1. Spring Board – 1 No.
2. Function Generator -2MHz -1 No.
3. Dual Power Supply (0-30V,2A, ±12V)-1 No.
4. Dual Channel CRO (20MHz)-1 No.
5. Patch Cards / Wires -10Nos.
6. Probes – 3 Nos.

Design Procedure:

(A) Forbiasing circuit:

Let VCC = 12 V, IC = 4.5 mA, β = 100(for SL 100)

To determine RE :

Choose VE = VCC / 10 = 12/10 = 1.2 V

VE = IERE = 1.2 V
RE = 1.2/Ic= 1.2/4.5mA = 0.267 KΩ (IE ≈ IC)
RE = 270 Ω

To determine RC
VB = VBE + VE = 0.7 + 1.2 = 1.9 V
R2
Weknow V  Vcc 
B
R1  R2

R2
1.9  12 
R1  R2

R2 1.9
  0.158
R1  R2 12

DEPT. OF ECE,EPCET 4
 Analog & Digital System Design Lab Sub.Code:BECL305

R2 = 0.158R1 + 0.158R2
0.8416R2 = 0.158R1

Let us assume R2 = 4.7KΩ

 R1 = 22.44 KΩ. Choose R1 = 22KΩ

To determine Bypass capacitor CE:

RE
Let XCE 
10 1
At f=100 Hz;  RE
2fce 10

10
Ce   59F
2 100  270

Choose CE = 47 µF (electrolytic)

Cc1 and CC2: Assume CC1 =CC2=0.1 µF(ceramic)

R1 = 22KΩ, R2= 4.7KΩ, RE = 270Ω, RC = 1 KΩ

CE = 47µF (Electrolytic), CC = 0.1µF (Ceramic)

A) Tank Circuit design:

The oscillating frequency for the above circuit is given by -

1
f  Where Ceq C1C2
2 LCeq  C2
Let f= 112.5KHz
C1 = C2= 0.01µF
1
L=
= 0.4mH
4 π2 f 2 Ceq

DEPT. OF ECE,EPCET 5
 Analog & Digital System Design Lab Sub.Code:BECL305

Typical Circuit diagram:

Procedure:

1. Connect the circuit as shown in circuit diagram.

2. Switch on the D.C. power supply.
3. Observe the output VO on CRO. Adjust 1KΩpotentiometer to get astable output waveform.
4. Measure the frequency of the output wave.
5. Compare the measured frequency with theoretical value.

Result:

Theoretical Practical
Frequency

DEPT. OF ECE,EPCET 6
 Analog & Digital System Design Lab Sub.Code:BECL305

B.CRYSTAL OSCILLATOR
Aim: Design and Testing of Crystal Oscillator for given frequency.

Components Required:
1. Transistor (SL100)-1 No.
2. Resistor (Carbon, 1/4W, 10%) – 4 Nos.
3. Capacitor (Ceramic Disk) – 5 Nos.
4. Capacitor (Electrolytic) – 1 Nos.
5. Potentiometer (0-1KΩ)-1 No.

Equipment Required:
1. Spring Board – 1 No.
2. Function Generator -2MHz -1 No.
3. Dual Power Supply (0-30V, 2A, ±12V)-1 No.
4. Dual Channel CRO (20MHz)-1 No.
5. Patch Cards / Wires -10Nos.
6. Probes – 3 Nos.

Design Procedure:

Let VCC = 12 V, IC = 4.5 mA, β = 100(for SL 100)

To determine RE:

Choose VE = VCC / 10 = 12/10 = 1.2 V

VE = IERE = 1.2 V
RE = 1.2/Ic= 1.2/4.5mA = 0.267 KΩ (IE ≈ IC)
RE = 270 Ω
To determine RC

Choose VCE = VCC /2 = 12/2 = 6V

Apply KVL in CE loop:
VCC – ICRC – VCE – VRE = 0
12 – 4.5Rc – 6 – 1.2 = 0
RC = 1.07 KΩ
RC = 1KΩ

To determine R1 and R2
VB = VBE + VE = 0.7 + 1.2 = 1.9 V
R2
We know VB  Vcc 
R1  R2
R2
1.9  12
R1  R2

DEPT. OF ECE,EPCET 7
 Analog & Digital System Design Lab Sub.Code:BECL305

R2 1.9
  0.158
R1  R2 12

R2 = 0.158R1 + 0.158R2
0.8416R2 = 0.158R1

Let us assume R2 = 4.7KΩ

R1-22.44KΩ Choose R1=22KΩ

To determine Bypass capacitor CE:

RE 1 10
Let XCE  . At f = 100 Hz;  RE .CE   59F
10 2fce 10 2 100  270

Choose CE = 47 µF (electrolytic). Cc1 and CC2:Assume CC1=CC2=0.1 µF (ceramic)

R1 = 22KΩ, R2= 4.7KΩ, RE = 270Ω, RC = 1 KΩ

CE = 47µF (Electrolytic), CC = 0.1µF (Ceramic)

Typical Circuit diagram:

DEPT. OF ECE,EPCET 8
 Analog & Digital System Design Lab Sub.Code:BECL305

Procedure:
1. Connect the circuit as shown in circuit diagram.
2. Switch onthe D.C. power supply.
3. Observe the output VO onCRO. Adjust 10KΩ potentiometer to get astable output waveform.
4. Measure the frequency ofthe output wave.
5. Compare the measured frequency with the frequency ofthe crystal.

RESULT:

Theoretical Practical
Frequency

DEPT. OF ECE,EPCET 9
 Analog & Digital System Design Lab Sub.Code:BECL305

C. RC- PHASE SHIFT OSCILLATOR

Aim: Design and Testing of R-C Phase Shift Oscillator for given frequency.
Components Required:
1. Transistor (SL100)-1 No.
2. Resistor (Carbon, 1/4W, 10%) – 4 Nos.
3. Capacitor (Ceramic Disk) – 5 Nos.
4. Capacitor (Electrolytic) – 1 Nos.
5. Potentiometer (0-1KΩ)-1 No.
Equipment Required:
1. Spring Board – 1 No.
2. Function Generator -2 MHz -1 No.
3. Dual Power Supply (0-30V,2A, ±12V)-1 No.
4. Dual Channel CRO (20MHz)-1 No.
5. Patch Cards / Wires -10Nos.
6. Probes – 3 Nos.
Design:
A.For biasing circuit:
Let VCC = 12 V, IC = 4.5 mA, β = 100(for SL 100)
To determine RE:
Choose VE = VCC / 10 = 12/10 = 1.2 V
VE = IERE = 1.2 V
RE = 1.2/Ic = 1.2/4.5mA = 0.267 KΩ (IE ≈ IC)
RE = 270 Ω
To determine RC:
Choose VCE = VCC /2 = 12/2 = 6V
Apply KVL in CE loop:
VCC – ICRC – VCE – VRE = 0
12 – 4.5Rc – 6 – 1.2 = 0
RC = 1.07 KΩ
To determine R1 and R2:
VB = VBE + VE = 0.7 + 1.2 = 1.9 V
RE = 270 Ω
RC = 1KΩ

DEPT. OF ECE,EPCET 10
 Analog & Digital System Design Lab Sub.Code:BECL305
We know that

R2 = 0.158R1 + 0.158R2

0.8416R2 = 0.158R1

Let us assume R2 = 4.7KΩ

R1 = 22.44 KΩ. Choose R1 = 22KΩ

To determine Bypass capacitor CE

Choose CE = 47 µF (electrolytic)
Cc1 and CC2: Assume CC1= CC2=0.1 µF (ceramic)

R1 = 22KΩ, R2= 4.7KΩ, RE = 270Ω, RC = 1 KΩ

CE = 47µF (Electrolytic), CC = 0.1µF (Ceramic)

A.Phase shifting network (Tank Circuit) design:

The frequency of oscillations is determined by phase shifting network.

The oscillating frequency for the above circuit is given by

Let f= 3KHz and choose C= 0.01µF

DEPT. OF ECE,EPCET 11
 Analog & Digital System Design Lab Sub.Code:BECL305

Circuit diagram:

Procedure:

1. Connect the circuit as shown in circuit diagram.

2. Switch on the D.C. power supply.
3. Observe the output VO on CRO. Adjust 10KΩ potentiometer to get a stable output waveform.
4. Measure the frequency of the output wave.
Compare the measured frequency with theoretical value

RESULT:

Theoretical Practical
Frequency

DEPT. OF ECE,EPCET 12
 Analog & Digital System Design Lab Sub.Code:BECL305

EXPERIMENT NO. 03

A.ADDER
Aim: To design and implement Adder using IC 741 Operational amplifier

Components and Equipment’s Required: Resistors, IC μA741, DC power supply, function generator
and CRO.
Design Procedure:

WRT I1=V1/V2 and I2=V2/I2

All of (I1 and I2) flows through resistor Rf, giving:

With R1 = R2

Where Av = -Rf/R1
With R1 = Rf
VO = −( V1 + V2)
I1(min) = 100 ∗ IB(max) = 100 * 500nA = 50 μA
R = V1/I1 = 0.1/ 50 μA V = 2KΩ (use 1.8KΩ standard value)
for AV = 1, 𝐑𝟏 = 𝐑𝟐 = 𝐑𝐟 = 𝟏. 𝟖𝐊Ω
R4 = R1 ll R2ll Rf = 1.8KΩ ll 1.8KΩ ll 1.8KΩ = 600Ω (use 560Ω standard value)
Circuit diagram:

DEPT. OF ECE,EPCET 13
 Analog & Digital System Design Lab
SUB CODE:21ECL35
Procedure:
1. Connect the Adder circuit as shown in circuit diagram.
2. Switch „ON‟ the power supply and apply +12V to pin no.7 and -12V to pin no.4 of the IC - μA741.
3. Apply the input voltages from the regulated supplies to the corresponding inputs at the inverting input
terminal of IC741 (pin no.2).
4. Connect the Digital Multimeter at the Output terminals (pin no.6), and note down the output voltage and
verify with theoretical values.
5. Repeat the above steps for different input voltages and complete the tabular column.
6. Repeat the above procedure for sinewave input from function generator at inverting input
terminal of IC 741 (pin num 2) and observe the output in CRO
Tabular Column:

Sl.no V1 V2 Vo= - (V1+V2)

Expected Graph:

RESULT: Adder using OP-Amp was designed and implemented

DEPT. OF ECE,EPCET 14
 Analog & Digital System Design Lab
SUB CODE:21ECL35

B. INTEGRATOR

Aim: To design, construct and verify the response of Integrator using Op-amp IC741.

Components and Equipments Required: Resistors, Capacitors, IC μA741, DC power supply, function
generator and CRO.

Design Procedure:
Let VI be input Square wave or sine wave or triangular wave of amplitude ±5V , 500Hz
Let ∇𝑉 be the peak to peak amplitude of the output waveform.

Cf = 0.1μF

𝑇 1 1
∇𝑡 = = = = 1𝑚𝑠

2 2𝑓 2 ∗ 500

∇𝑉 = 4𝑉
𝐶𝑓 𝑉
∇ 0.1μF∗4V = 400ma
W.R.T, 𝐼1 = 1𝑚s
∇𝑡
R1=V1/I1=V/400Μa=12.5KΩ (Use a 12KΩ standard value with a 470Ω connected d in
series)
𝑅𝑓 = 20 * 𝑅1= 20 * 12.5KΩ = 250 KΩ (Use a 270KΩ standard value)
𝑅2 = 𝑅1= 12.5KΩ (Use a 12KΩ standard value)

DEPT. OF ECE,EPCET 15
 Analog & Digital System Design Lab Sub.Code:BECL305

Circuit diagram:

Procedure:

1. Connect the circuit as shown in circuit diagram.

2. Switch „ON‟ the power supply and apply +12V to pin no.7 and -12V to pin no.4 of the IC741.
3. Apply input signal from the function generator (at pin no.2 of the IC741).
4. Connect the C.R.O at (pin no.6) the output terminals.
5. Measure the output voltage (Vo) from the pin number 6
6. Observe and plot the input & output voltage waveforms.
7. Apply different input signal from the function generator and repeat the above steps.

Tabular Column and expected waveforms:

Sl No VI(V) . VO (V)

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Triangular wave of amplitude ±5 V P-P,

500Hz

Result:Integrator using Op-amp μA741 was designed, constructed and its response was verified

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C.DIFFERENTIATOR
Aim: To design, construct and verify the response ofIntegrator using Op-amp IC741.

Components and Equipments Required: Resistors, Capacitors, IC μA741, DC power supply,

function generator and CRO.

Design Procedure:

Let VI be the input of Square wave or sine wave or triangular wave of amplitude ±1V , 500Hz

Let I1>>IB(max)

I1 = 500μA

𝑹 = 𝑉𝑂 = 5𝑉 = 𝟏𝟎𝑲Ω
𝟐 𝐼1 500𝜇𝐴

𝐼1∇𝑡
500μA ∗ 100μs
𝑪𝟏 = = 0.05μF
∇𝑉 1𝑉

𝑅1 = 𝑅2= 10KΩ / 20 = 500Ω(Use a 470Ω standard value)

20

𝑹𝟑 = 𝑹𝟏= 10KΩ

Circuit diagram:

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Procedure:

1. Connect the circuit as shown in the circuit diagram.

2. Switch „ON‟ the power supply and apply +12V to pin no.7 and -12V to pin no.4 ofthe IC741.
3. Apply a input signal from the function generator (at pin no.2 of the IC741).
4. Connect the C.R.O at (pin no.6) the output terminals.
5. Measure the output voltage (Vo) from pin number 6
6. Observe and plot the input & output voltage waveforms.
7. Apply different input signal from the function generator and repeat the above steps.

Tabular Column and expected waveforms:

Sl VI(V) VO(V)
No
.
Sine wave ofamplitude ±1V, 500Hz Cosine
wave

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Amplitude Duration Amplitude Duration

Triangular wave ofamplitude ±1V P-P, 500Hz Near square wave

Amplitude Duration Amplitude Duration

RESULT: Differentiator using Op-amp μA741 was designed, constructed and its response was verified.

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EXPERIMENT NO. 04
Design and Implement

a) Half and Full Adder Using basic gates and NAND gates
b) Half and Full subtractor using NAND gates
c) 4-variable function using IC74151(8:1 MUX)

Pin Details of Logic Gates:

TWO INPUT AND GATE

LOGIC SYMBOL

TRUTH TABLE

INPUT OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

TWO INPUT OR GATE

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NOT GATE

TWO INPUT NAND GATE

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TWO INPUT EX-OR GATE

TWO INPUT NOR GATE

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(a) Half and Full Adder using Basic Gates and NAND Gates
Aim: To Realize and verify the truth Table of Half and Full adder Basic gates.

Equipment’s and Components

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7486(XOR) 02
3 IC 7408 (AND) 03
4 IC 7432(OR) 02
5 IC 7400(NAND) 04
6 Patch chords 1 set

Half Adder Using basic gates: Truth Table:

Half Adder Using NAND gates:

Procedure

1. For Half Adder setup the circuit as shown in the diagram

2. Give the input bit combinations, observe the output corresponding to input combinations and
Verify the respective truth tables.

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Full – Adder

Truth Table

INPUTS OUTPUTS
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

K –Map for Sum

K –Map for Carry

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Full Adder Using Basic Gates

Full Adder Using NAND Gates

Procedure

1. For Full Adder setup the circuit as shown in the diagram

2. Give the input bit combinations, observe the output corresponding to input combinations and
Verify the respective truth tables.

Result:

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b. Half and Full Subtractor using Basic Gates and NAND Gates

Aim: To Realize and verify the truth Table of Half and Full Subtractor Basic gates.

Equipment’s and Components

Sl. Components Quantity

No
1 Trainer Kit 01
2 IC 7486(XOR) 01
3 IC 7408 (AND) 03
4 IC 7432(OR) 01
5 IC 7404(NOT) 01
6 IC 7400(NAND) 08
7 IC 7410(3 i/p NAND) 02
8 Patch chords 1 set

Half Subtractor using basic gates: Truth Table

Procedure

1. For Half subtractor setup the circuit as shown in the diagram

2.Give the input bit combinations, observe the output corresponding to input combinations and
verify the respective truth tables.

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Full – Subtractor

Truth Table
INPUTS OUTPUTS
A B C D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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Full Subtractor Using Basic Gates

Full Subtractor Using NAND Gates

RESULT:

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c) 4-Variable function using IC74151(8:1 MOX)

Aim: To Realize the 4 variable function using IC 74151 (8:1 Multiplexer).

Components Required:
Digital Trainer Kit
NOT Gate IC 7404
8x1 MUX IC 74151
Patch chords / Connecting wires

Connection Diagram (Top view)

Design Example: To implement the following function: F(A,B,C,D) = Σ (0,1,3,4,8,9,15).

Step-1: Using K-map Boolean terms are determined for the variable A as shown below.

Step-2: Construct digital circuit for the given 4 variable function F(A,B,C,D) = Σ (0,1,3,4,8,9,15), such that a logic
is needed to give combination of A as inputs (1, 1, 0, Ā, Ā, 0, 0, A) while only B, C and D as select line inputs.

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Basic pin Description of IC 74151 IC74151 designed for F(A,B,C,D) = Σ (0,1,3,4,8,9,15)

Step-3: Connect the circuit as shown in the fig. above and verify the following truth table.

Result: 4 variable function F(A,B,C,D) = Σ (0,1,3,4,8,9,15) using IC 74151 (8:1 Multiplexer) is realized.

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EXPERIMENT NO-05
Realize:
a) Binary to Gray code conversion & vice versa (IC 74139)
b) BCD to Excess-3 code conversion and vice-ver

a) Binary to Gray code conversion & vice versa (IC 74139)

Aim: To realize binary to gray code conversion and vice versa using IC74139 (2-4 Decoder).
Components Required:
Digital Trainer Kit
NOT Gate IC 7404
DeMux IC 74139
NAND Gage (4 inputs) IC 7420
Patch chords / Connecting wires
Binary to gray code conversion
Following steps are required in this conversion:
(1) The MSB of the gray code is equal to MSB of binary number.
(2) Second bit of the gray code will be exclusive-or of the first and second bit of the given binary number.
(3) The third bit of gray code will be equal to the exclusive -or of the second and third bit of the given binary
number.
Thus the Binary to gray code conversion goes on.
One example given below can make your idea clear on this type of conversion

Pin Diagram:

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Truth Table: Binary to Gray conversion

Circuit Diagram:

Gray code to binary conversion

Following steps are required in this conversion:
1) The MSB of the binary number will be equal to the MSB of the given gray code.
2) Start with MSB of Binary number and EXOR it to the second bit of gray number to get next bit of binary.
3) This step is continued for all the bits to do Gray code to binary conversion.
One example given below can make your idea clear on this type of conversion

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Truth Table: Gray to Binary conversion

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Circuit Diagram:

Procedure:
1) Check all the components for their working.
2) Insert the appropriate IC into the IC base.
3) Make connections as shown in the circuit diagram.
4) Verify the Truth Table and observe the outputs.

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b) BCD to Excess-3 code conversion and vice-ver

Aim: To realize BCD to Excess-3 code conversion and vise versa using IC 7483

Components Required:

Digital Trainer Kit

EXOR Gate IC 7486
4- bit binary full adder IC 7483
Patch chords / Connecting wires

Excess-3 Code - It is non-weighted code used to express decimal numbers. The Excess -3 code words
are derived from the 8421 BCD code words adding (0011) 2 or (3)10 to each code word in 8421.

Circuit Diagram: BCD to excess -3 / excess -3 to BCD conversion

NOTE: Neglect Cout in the circuit

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Truth Tables

BCD to Excess-3 Code Excess-3 to BCD Code

Procedure

1) Check all the components for their working.

2) Insert the appropriate IC into the IC base.
3) Make connections as shown in the circuit diagram.
4) Verify the Truth Table and observe the outputs.

RESULT: BCD to Excess-3 code conversion and vise versa using IC 7483 are realized.

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EXPERIMENT-06

a) Realize using NAND Gates:

(i) Master-Slave JK Flip Flop

Aim: To verify the truth table of JK, D & T flip-flops using NAND Gates

Equipment’s and components

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7400 02
3 IC 7410 02
4 Patch chords 1 set
Procedure
1. Connections are made as shown in circuit diagram
2. The clock pulses are applied, different inputs are given and for each circuit, the truth table is verified.

J K Flip - Flops: Logic Symbol Truth Table

Clock J K Q Q Comment

0 0 Q Q No change

0 1 0 1 Reset

1 0 1 0 Set
1 1 Race around
Note: Keep Pr=1, Cr=1 for verifying the truth tables of master slave JK, D, T Flip-Flops

J K Flip - Flops: Logic Diagram

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Logic Symbol Truth Table

CLK T Qn+1 Comments

X Qn No change

0 Qn No change

1 Toggles

D Flip flop: Logic Symbol Truth Table

CLK D Qn+1 Comments

0 X Qn No change

Data
0 0
transfered
Data
1 1
transfered

RESULT:

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b) Shift Registers using IC7474/IC7495

Aim: To realize and study of Shift Register.

a) SISO (Serial in Serial out)

b) SIPO (Serial in Parallel out)
c) PIPO (Parallel in Parallel out)
d) PISO (Parallel in Serial out).
e) Ring counter
f) Johnson Counter

Equipments and Components

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7474 04
3 IC 7404(NOT) 01
4 IC 7408(AND) 06
5 IC 7432(OR) 03
6 IC 7495 01
7 IC 7404 01
8 Patch chords 1 set

Pin Details of IC 7474 (4 bit Shift Register)

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Functional Table for 7474:

Procedure:

SIPO (Serial input serial output)

1) Clock 1 is connected to pulses.

2) Serial input is given to SI. After each i/p give one clock pulse.
3) After 4 clock pulses. The serial input appears in Parallel form Q3, Q2, Q1, Q0

Truth Table:

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DEPT. OF ECE,EPCETIPO (Serial input parallel output)

1) Clock 1 is connected to pulses.

2) Serial input is given to SI. After each i/p give one clock pulse.
3) After 4 clock pulses. The serial input appears in Parallel form Q3, Q2, Q1, Q0.

Procedure:
PIPO (Parallel input parallel output)

a. Parallel inputs are given to D3, D2, D1, D0 inputs

b. Clk1 is pulsed once and parallel data appears on Q3, Q2, Q1, Q0.

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PISO (Parallel input Serial output)

a. Load/Shift control is made ‘1’

b. Clock 1 is connected to pulses.
c. Parallel inputs are given to D3, D2, D1, D0 inputs
d. Now, make Load/Shift control is made ‘0’
e. CLK 1 is connected to pulses.
After 4 clock pulses, parallel inputs are converted in to serial output data on ‘Q0’

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RING COUNTER using IC7495:

Procedure
1. Rig up the circuit as shown in the diagram, serial input(pin 1) is not given as input
3. Load data parallel with clk & MC=1
4. Then make MC=0, apply clk pulses
5. Verifying the working of a ring counter
6. Observe the output are passed to the input and keeps rotating like a ring.

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Circuit Diagram of Ring Counter Truth Table

MC Time QA QB QC QD

1 t0 1 0 0 0

0 t1 0 1 0 0

0 t2 0 0 1 0

0 t3 0 0 0 1

JOHNSON COUNTER using IC7495:

Procedure
1. Rig up the circuit as shown in the diagram, serial input(pin 1) is not given as input
2. Load data parallel with clk & MC=1
3. Then make MC=0, apply clk pulses
4. Verify whether the circuit works as a Johnson counter or twisted ring counter

Circuit Diagram of Johnson Counter Truth Table

MC Time QA QB QC QD

1 t0 1 0 0 0
0 t1 1 1 0 0
0 t2 1 1 1 0
0 t3 1 1 1 1
0 t4 0 1 1 1
0 T5 0 0 1 1
0 t6 0 0 1 1
0 t7 0 0 0 1
0 t8 1 0 0 0

RESULT:

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EXPERIMENT-07
Mod-N Counters

Aim: i)To realize Mod-N Asynchronous Counter using IC7490

ii)To realize Mod-N Synchronous Counter using IC74192

Equipments and components

Sl.No Components Quantity

1 Trainer Kit 01
2 IC 7490 01
3 IC 7400 02
4 IC 74192 01
5 Patch chords 1 set

Procedure
1. Connections are made as shown in circuit diagram.
2. Apply clock pulses and observe the output and verify the Truth Table.

Realization of MOD – N Counter: MOD 6 Counter Using 7490

Truth Table:

Clock Flip – Flop

pulse outputs
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 0 0 0

Realization of MOD – N Counter: MOD 6 Counter Using 74192

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Analog & Digital System Design Lab Sub.Code:BECL305
Pin details of IC74192

Logic diagram:
Truth Table:

Clock Flip – Flop

pulse outputs
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 0 0 0

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EXPERIMENT NO. 08
4 BIT R – 2R OP-AMP DAC
1. Using 4 bit binary input from toggle switches
2. By generating digital inputs using mod-16
1. Using 4 bit binary input from toggle switches
Aim: To design and implement R – 2R DAC using 4 bit binary input from toggle switches
Components and Equipment’s Required: Resistors, IC μA741, DC power supply, function generator
and CRO.
Design Procedure:
Let Vre f = 5V , R = 1k ;. Since R = 1k therefore 2R = 2k (Use standard value 2.2kΩ)
We know that for R-2R DAC the output voltage is given by the expression

Vo = −𝑹𝒇/R1 * [Vin ]

From the circuit diagram, 𝑹𝒇 = 2R. And by thevenin‟s equivalent circuit, we get 𝑹𝟏 = 2R
Therefore, we have -

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Circuit diagram:

Procedure:
1. Rig up the circuit as shown in the circuit diagram.
2. Set all the logic switches representing the inputs B3B2B1B0 to logical 0 [low state] and switch on the
supply for the trainer kit.
3. Vary the input switches from 0000 to 1111 as shown in the table using the logic switches and note
down the corresponding analog output Voltage in the table. Compare the practical value with the
theoretical value.
4. Plot the staircase waveform and hence calculate the value of stepsize or resolution obtained practically
Observation :

Decimal Eqnt. Digital inputs Vo (Theo) Vo(prac)

B3B2B1B
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 1010

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11 1011

12 1100

13 1101
14 1110
15 1111

Expected Wave from:

Result:
Thus the 4-bit R – 2R DAC is designed using Op-Amp μA741 and implemented.
Resolution (theoretical) =
Resolution (practical) =

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2. BY GENERATING DIGITAL INPUTS USING MOD – 16

Aim: To design and implement R – 2R DAC using 4 bit binary input by generating digital inputs using
MOD– 16.
Components and Equipment’s Required: Resistors, ICμA741, DC power supply, function generator
and CRO.
Design Procedure:
Let Vref = 5V , R = 1k ;Since R = 1k therefore 2R = 2k (Use standard value 2.2kΩ)
We know that for R-2R DAC the output voltage is given by the expression

From the circuit diagram, 𝑹𝒇 = 2R.

And by thevenin‟s equivalent circuit, we get 𝑹𝟏 = 2R

Therefore, we have

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 Analog & Digital System Design Lab Sub.Code:BECL305
Circuit diagram:

Procedure:
1. Rig up the circuit as shown in the circuit diagram.
2. Set all the logic switches representing the inputs B3B2B1B0 to logical 0 [low state] and switch on the
supply for the trainer kit.
3. Vary the input switches from 0000 to 1111 as shown in the table using the logic switches and note
down the corresponding analog output Voltage in the table. Compare the practical value with the
theoretical value.
4. Plot the staircase waveform and hence calculate the value of step size or resolution obtained practically

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Observation :

Decimal eqt Clock Digital inputs Vo(prac)

B3B2B1B0 Vo (Theo)
Vo (Theo)
Vo(prac)
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111

Expected Wave forms:

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Result:
Thus the 4 bit R – 2R DAC is designed using Op-Amp μA741 and implemented.
Resolution (theoretical) =
Resolution (practical) =

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EXPERIMENT NO.09

Design and test Monostable and Astable Multivibrator using 555 Timer

a). Monostable multivibrator using 555 timer

Aim: To design and test a Monostable multivibrator for a given pulse width ω using IC 555.

Components and Equipment’s Required: Resistors, Capacitors, IC 555, DC power supply,

function generator and CRO.

Design Procedure:
Let ω = 10msecs
ω = 1.1 R C
Choose C = 0.1μF
Then, R = 90.9kΩ (use standard value 90kΩ)
Frequency of the trigger input f = 1/ω = 100Hz

Circuit diagram:

Procedure:

1. Connect the circuit as shown in circuit diagram.

2. Switch on the D.C. power supply and set VCC = 5V.
3. Give the trigger input from the signal generator to pin no. 2 of555 timer.
4. Measure the output waveform at pin no. 3 on CRO.

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5. Measure the pulse width fromthe output waveform

Observe the capacitor voltage across pin no.6 and plot waveforms

Expected waveforms:

Result:

The monostable multivibrator circuit using 555 timer was designed and tested for a given pulse width.
Pulse width = 10 ms (theoretical)
Pulse width = ms (practical)

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b).Astable Multivibrator using 555 Timer

Aim: To design and test the symmetrical astable multivibrator with a frequency of 2kHz and duty
cycle of50%

Components and Equipment’s Required: Resistors, Capacitors, IC 555, diode IN4007, DC power
supply, function generator and CRO.

Design Procedure:

Let f = 2kHz, duty cycle = 50%, T = 1/f =1/2k = 0.5msecs

Let RA = RB = R

T = 1.386 R Ct

Choose Ct = 0.1μF

Then, calculate R =T/1.386 *Ct = 3.6

kΩChoose C = 0.01μF

Circuit diagram:

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Procedure:

1. Connect the circuit as shown in circuit diagram.

2. Switch onthe D.C. power supply and set VCC = 5V.
3. Observe the output wave form at pin no. 3 on CRO and calculate Ton , Toff and hence T.
1 2
4. Observe the capacitor voltage at pin no. 6 and verify VCC and VCC voltage levels.
3 3

5. Plot the waveform onthe graph sheet.

Calculations

Duty Cycle = 𝑇𝑂𝑁

𝑇𝑂𝑁+ 𝑇𝑂𝐹𝐹

Theoretical Theoretical

Vcc

1/3 Vcc

2/3Vcc

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Expected Waveforms:

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EXPERIMENT NO.10
1. Active Second Order Butterworth Low-pass Filter
Aim: To design & conduct an experiment on II order butterworth low pass filter and to study the
frequency response.

Components and Equipment’s Required: Resistors, Capacitors, IC μA741, DC power

supply, function generator and CRO.

Design Procedure:

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Circuit Diagram:

Procedure:

Tabular Column: Vin=

------------ V

Sl No. Frequency (Hz) VO (V) Av=Vo/Vin AV =[20log Av]dB

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Expected Graph:

Result: Second order Butterworth LPF was designed and tested. The following results were observed
Cut off frequency (fH) Hz
Theoretical
Practical

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2. Active Second Order Butterworth High-pass Filter

Aim: To design & conduct an experiment on II order butterworth high pass filter and to study the
frequencyresponse

Components and Equipment’s Required: Resistors, Capacitors, IC μA741, DC power supply,

function generator and CRO
Design Procedure:

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Circuit Diagram:

Procedure:

Tabular Column:
Vin= ------- V

Sl No. Frequency (Hz) VO (V) Av=Vo/Vin AV =[20log Av]dB

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Expected Graph:

Result: Second order Butterworth HPF was designed and tested. The following results were observed

Cut off frequency (fH) Hz

Theoretical
Practical

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EXPERIMENT NO.11
Design and Test Regulated Power supply

Aim: Design and Test the regulated power supply determine the load regulation and efficiency
of the regulated power supply.

Components and Equipment’s Required:

 30 MHz Dual Channel Cathode Ray Oscilloscope
 3 MHz Function Generator
 0-30 V dc dual regulated power supply
 230 V/ 12 V, 1A Step down transformer
 1N4007 Diode IC 7805
 Resistor 100Ω,
 1000µF/25V Ceramic Capacitor
 0.33 µF, 0.1 µF
 Breadboard and Connecting wires
 BNC Cables and Probes
Design Procedure: Design a DC regulated power supply to deliver up to 1A of current to the load
with 5% ripple. The input supply is 50Hz at 230 V AC.
Ripple voltage = ΔV = Vr Two figures of merit for power supplies are the ripple voltage, Vr, and the
ripple factor, RF.

Circuit Diagram:

Procedure:
 Power Supply :
 Connect the circuit as shown in Figure
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 Apply 230V AC from the mains supply

 Observe the following waveforms using oscilloscope (i) Waveform at the secondary of
the transformer (ii) Waveform after rectification (iii) Waveform after filter capacitor
(iv) Regulated DC output

 Load Regulation
 Observe the No load voltage and Full load voltage
 Calculate the load regulation. Load Regulation = ((VNL – VFL)/VFL) x 100 %
 Theoretical efficiency of linear voltage regulator =
Graph:
1. Waveform at the Primary of the transformer

2. Waveform at the secondary of the transformer

3. Waveform after rectification

4. Waveform after filter capacitor

5. Regulated DC output

Result:
DEPT. OF ECE,EPCET 67
Analog & Digital System Design Lab Sub.Code:BECL305

EXPERIMENT NO.12
Design and test an audio amplifier by connecting a microphone input and observe the output
using a loud speaker

Aim: Design and test an audio amplifier by connecting a microphone input and observe the output using a
loud speaker

Components Required:

1. LM386
2. 10uF Capacitor
3. 470uF Capacitor
4. 0.047uF / 16V PolystarFlim Capacitor
5. 10R ¼ Watt Resistor
6. 12V Power Supply unit
7. 8 Ohms / .5 Watt Speaker
8. Microphone
9. .1uF capacitor
10. 10k 1/4th Watt Resistor
11. Bread Board

Circuit diagram:

DEPT. OF ECE,EPCET 68
Analog & Digital System Design Lab Sub.Code:BECL305

Pinout and Pin description of LM386 audio amplifier IC:

Procedure:

1. Construct the circuit in a breadboard. PCB is a good choice.

2. Remove the R2 and use a potentiometer to adjust the gain of the microphone.
3. Connect a long wire across Speaker and keep it at larger distance from the microphone. The
feedback will be lower.
4. Use additional filters to get clean sound output.
5. Use proper low ripple power supply unit.

Wave forms:

Voice Input Voice output

At Microphone at Loud speaker

DEPT. OF ECE,EPCET 69
Analog & Digital System Design Lab Sub.Code:BECL305

EXPERIMENT NO. 13
Illustration of AM Modulation and Demodulation and display the signal and its spectrum

Aim: Write a MATLAB program to generate Amplitude Modulated signal, Amplitude Demodulated
signal(using synchronous detector),and spectrum of AM signal.

Amplitude Modulation:
Program:
clc;
clear all;
close all;
t=linspace(0,0.1,50000);
%defining time range for the signal
fc=1000; %frequency of carrier signal
fm=500; %frequency of message signal
fs=100000;
%sampling frequency---fs>=2(fc+BW)
Am=5; %amplitude of the message signal
Ac=10; %amplitude of the carrier signal
m=Am/Ac %modulation index for the AM wave
wc=2*pi*fc*t; %carrier frequency in radians
wm=2*pi*fm*t; %message frequency in radians
ec=Ac*sin(wc); %carrier signal
em=Am*sin(wm); %message signal
y=ammod(em,fc,fs,0,Ac); %AM signal
z=amdemod(y,fc,fs,0,Ac);%demodulated AM signal l=50000;
\ subplot(4,1,1),
plot(t(1:l),
em(1:l))
xlabel('time(sec)');
ylabel('amplitude in volts(V)');
title('MODULATING SIGNAL');
subplot(4,1,2),
plot(t(1:l/2),
ec(1:l/2))
xlabel('time(sec)');
ylabel('amplitude in volts(V)');
title('CARRIER SIGNAL');
subplot(4,1,3),
plot(t(1:l),

DEPT. OF ECE,EPCET 70
Analog & Digital System Design Lab Sub.Code:BECL305

y(1:l))
axis([0 0.02 -20 20]) %setting axis dimensions
xlabel('time(sec)');
ylabel('amplitude in volts(V)');
title('AMPLITUDE MODULATED SIGNAL');
subplot(4,1,4),
plot(t(1:l),z(1:l))
xlabel('time(sec)');
ylabel('amplitude in volts(V)');
title(' AM DEMODULATED SIGNAL');

Output Wave forms:

Result:

DEPT. OF ECE,EPCET 71
Analog & Digital System Design Lab Sub.Code:BECL305

EXPERIMENT NO. 14
Illustration of FM Modulation and Demodulation and Display the signal and its spectrum (Use
MATLAB/SCILAB)

DEPT. OF ECE,EPCET 72
Analog & Digital System Design Lab Sub.Code:BECL305

Output Wave forms:

Result:

DEPT. OF ECE,EPCET 73