INTRODUCTION

ARM
PROCESSO
R
(ARM7TDMI)
Chronicle (history) of ARM

▪ Developed at Acorn Computer Limited of Cambridge, England between 1983 and 1985.
▪ Initially it was known as Acorn RISC Machine with 26 bit processor named after Berkeley RISC
project.
▪ Later joint venture was cofounded by Acorn and Apple designate it as ADVANCED RISC
MACHINE.
Developments in ARM
• 1985: Acorn Computer Group manufactures the first commercial RISC microprocessor.
• 1990: Acorn and Apple participation leads to the founding of Advanced RISC Machines (ARM).
• 1991: ARM6, First embeddable RISC microprocessor.
• 1992 – 1994: Various companies use ARM (Sharp, Samsung), while in 1993 ARM7, the first
multimedia microprocessor is introduced.
• 1995: Introduction of Thumb and ARM8.
• 1996 – 2000: Alcatel, Huindai, Philips, Sony, use ΑRM, while in 1999 ARM cooperates with
Erickson for the development of Bluetooth.
Features
• ARM executes almost all the instruction in only one cycle Ex:1 cycles for execution of BNEQ in
ARM.
• ARM is General-Register Based Architecture or load-store L/S architecture.
• ARM is a 32 bit microprocessor with one word being 32 bits long.
• The ARM is a 32-bit architecture.
• Auto increment and auto decrement addressing mode
• Multiple load and store, Only Load/Store instructions can access Memory.
• Conditional execution
• ALU and shifter in a single clock cycle
• Thumb instructions-16bit instruction format
• Support 8-bit jazzel (java byte code).
• Parallel processing, Three stage pipe line structure
• All data processing instructions operate on registers only
• All data processing instructions can use the barrel shifter (an interesting and unique feature) to
shift or rotate an operand
• Can operate in either Big or Little endian mode
• Memory is byte-oriented, each byte of memory has its own unique address
• Must use an address divisible by 4 to access a word.

ARM7TDMI Processor Core:

• Current low-end ARM core for applications like digital mobile phones
• TDMI
– T: Thumb, 16-bit compressed instruction set
– D: on-chip Debug support, enabling the processor to halt in response to a debug request
– M: enhanced Multiplier, yield a full 64-bit result, high performance
– I: Embedded ICE hardware
• Von Neumann architecture
• 3-stage pipeline
Operating modes: The ARM Processor has seven basic operating modes
• User :Un privileged mode under which most task run. [10000]
• Fiq: Entered when a high priority interrupt is raised [10001]
• Irq: Entered when a low priority interrupt is raised [10010]
• System: Privileged mode using the same registers as user mode
• Supervisor: Entered on reset and when software instruction is executed [10011]
• Abort: Used to handle memory access violations [10111]
• Undef: Used to handle undefined instructions [11011]

Block diagram showing Simple view of Microcontroller

Block diagram showing detailed view of Microcontroller

Block diagram showing ARM microcontroller

16 bit RAM 32 bit RAM

Interrupt
Controller
nIR nFI
Peripherals
Q Q

ARM
8 bit ROM Core

Registers:

• ARM has 37 registers, all of which are 32 bits long

– 1 dedicated program counter
– 1 dedicated current program status register(CPSR)
– 5 dedicated saved program status registers(SPSR)
– 30 general purpose registers
• These registers are not all accessible at the same time. The processor state and operating mode
determine which registers are available to the programmer.

➢ These are arranged into several banks. The accessible bank being governed by the processor
mode. Each mode can access
▪ a particular set of r0-r12 registers
▪ a particular r13 (the stack pointer) and r14 (link register)
▪ r15 (the program counter)
▪ CPSR (current program SR) & privileged modes can also access a particular SPSR
(saved program status register)
Data Sizes:
➢ When used in relation to the ARM:
▪ Byte means 8 bits
▪ Halfword means 16 bits (two bytes)
▪ Word means 32 bits (four bytes)

ARM Instruction Feature:

Most ARM’s implement two instruction sets
▪ 32-bit ARM Instruction Set
▪ 16-bit Thumb Instruction Set
▪ Jazelle cores can also execute Java bytecode Java bytecodes are 8-bit instructions
designed to be architecture independent. Jazelle transparently executes most bytecodes
in hardware and some in highly optimized ARM code. This is due to a tradeoff between
hardware complexity (power consumption & silicon area) and speed.

ARM7TDMI-S processor has two Instruction sets:

• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code
while retaining most of the Arm’s performance advantage over a traditional 16-bit processor using 16-bit
registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an
equivalent ARM Processor connected to a 16-bit memory system.

Merits:
 • Low power consumption
• Cost sensitive embedded application
• Cheap
• Easy to develop
• High performance
• Low code size
• Increases speed
Demerits:
• Need all software’s to be developed for new architecture

Scope and Applications:

• Mobile phones and PDA
• Patient Monitoring
• Automotive power train
• Anti lock braking
• Washing Machine
• Image processing
 ARM Instruction Set
Categories of Instruction Set based on functionality as follows:
• Data Processing Instructions:
MOVE INSTRUCTIONS: MOV, MVN
BARREL SHIFT OPERATIONS: LSL, LSR, ASR, ROR, RRX
ARITHMETIC INSTRUCTIONS: ADD, ADC, RSB, RSC, SUB, SBC
LOGICAL INSTRUCTIONS: AND, ORR, EOR, BIC
COMPARISON INSTRUCTIONS: CMP, CMN, TEQ, TST
MULTIPLY INSTRUCTIONS: MUL, MLA
• Load Store Instructions:
• Branch Instructions:
Other instruction set:
Software Interrupt Instruction
Program status Register instructions
Coprocessor instructions

1. Data Processing Instructions

MOVE INSTRUCTIONS:

MOV Move a 32-bit value into a register Rd=N

MVN Move the NOT of the 32-bit value into a register Rd= ~N

Barrel Shift Operation:

Mnemonics Description Shift Result

LSL Logical shift left xLSLy x<< y
LSR Logical shift right xLSRy (unsigned) x>>y
ASR Arithmetic right shift xASRy (signed) x>>y
ROR Rotate right xRORy ((unsigned)x>>y)|(x<<(32-
y))
RRX Rotate right extended xRRX (c flag<<31)|((unsigned )
x>>1)

ARITHMETIC INSTRUCTIONS: ADD, ADC, RSB, RSC, SUB, SBC

ADC Add two 32-bit values and carry Rd=Rn+N+carry

ADD Add two 32-bit values Rd=Rn+N
RSB Reverse subtract of two 32-bits values Rd=N-Rd
RSC Reverse subtract with carry of two 32-bits Rd=N-Rd-!(carry
values flag)
SBC Subtract with carry of two 32-bits values Rd=Rn-N-!(carry
flag)
SUB Subtract two 32-bit values Rd=Rn-N
LOGICAL INSTRUCTIONS: AND, ORR, EOR, BIC

ADD Logical bitwise AND of two 32 bits values Rd=Rn & N

ORR Logical bitwise OR of two 32-bits values Rd= Rn|N
EOR Logical exclusive OR of two 32-bits values Rd=Rn^N
BIC Logical bit clear (AND NOT) Rd= Rn^~N

COMPARISON INSTRUCTIONS: CMP, CMN, TEQ, TST

CMN Compare negated Flags set as result of Rn+N

CMP Compare Flags set as result of Rn-N
TEQ Test for quality of two 32-bit values Flags set as result of Rn^N
TST Test bits of a 32-bit value Flags set as result of Rn&N

MULTIPLY INSTRUCTIONS: MUL, MLA

MLA Multiply and accumulate Rd=(Rm*Rs)+Rn

MUL Multiply Rd=Rm*Rs

SMLAL Signed multiply accumulate long {RdHi, RdLo}={ RdHi,

RdLo}+(Rm*Rs)
SMULL Signed multiply long {RdHi, RdLo}= Rm*Rs
UMLAL Unsigned multiply accumulate long {RdHi, RdLo}={ RdHi,
RdLo}+(Rm*Rs)
UMULL Unsigned multiply long {RdHi, RdLo}=Rm*Rs

2. Load Store Instructions:

LDR Load constant pseudo instruction Rd=32-bit constant

ADR Load address pseudo instruction Rd=32-bit relative address

3. Branch Instructions:
B Branch pc=label
BL Branch with link pc=label
lr=address of the next instruction after the BL
BX Branch exchange pc=Rm & 0xfffffffe, T=Rm & 1
BLX Branch exchange with pc=label, T=1
link pc= Rm & 0xfffffffe, T=Rm & 1
lr=address of the next instruction after the
BLX
Other instruction set:
Software Interrupt Instruction: A software interrupt instruction (SWI) causes a software
interrupt exception, which provides a mechanism for applications to call operating system
routines.
Syntax: SWI {<cond>} SWI_number

SWI Software lr_svc=address of instruction following the

interrupt SWI
spsr_svc=cpsr
pc=vectors+0x8
cpsr mode= SVC
cpsr I=I (mask IRQ interrupt)

Program status Register instructions

The ARM instruction set provides two instructions to directly control a program status register
(psr). The MRS instruction transfers the contents of either the cpsr or spsr into a register; in the
reverse direction, the MSR instruction transfers the contents of a register into the cpsr or spsr.
Together these instructions are used to read and write the cpsr and spsr.
Syntax: MRS {<cond>} Rd <cpsr |spsr>
MSR {<cond>} <cpsr|spsr} _<fields>,Rm
MSR {<cond>} <cpsr|spsr} _<fields>, #immediate
The table shows the program status register instructions
MRS Copy program status register to a Rd=psr
general-purpose register
MSR Move a general-purpose register to a psr[field]=Rm
program status register
MSR Move an immediate value to a program psr[field]=immediate
status register

Coprocessor instructions: used to extend the instruction set

Syntax: CPD {<cond>} cp,opcode1, Cd, Cn {,opcode2}
<MRC|MCR>{<cond>}cp,opcode1,Rd,Cn,Cm{,opcode2}
<LDC|STC>{<cond>}cp,Cd,addressing
CDP Coprocessor data processing-perform an operation in a coprocessor
MRC, Coprocessor register transfer-move data to/from coprocessor
MCR registers
LDC,STC Coprocessor memory transfer-load and store blocks of memory
to/from a coprocessor
WRITE STEPS TO CREATE-DEBUG-EXECUTE ASSEMPLY LANGUAGE PROGRAM & C
PROGRAM FOR ARM USING KEIL 4 uVISION IDE.