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Electrical Engineering Sanchez
Canton

Microcontrollers
HIGH-PERFORMANCE SYSTEMS
AND PROGRAMMING

Microcontrollers

Microcontrollers
Microcontrollers: High-Performance Systems and Programming
discusses the practical factors that make the high-performance PIC
series a better choice than their mid-range predecessors for most
systems. However, one consideration in favor of the mid-range
devices is the abundance of published application circuits and code
samples. This book fills that gap:
• Provides downloadable software, including tools, resources,
supplementary materials, and code listings
HIGH-PERFORMANCE SYSTEMS
• Includes sample circuits with their corresponding programs,
as well as tested PCB files
AND PROGRAMMING
• Focuses on the popular embedded systems with PIC18
series microcontrollers
• Contains an appendix with a C language tutorial, PIC18
instruction set, links to useful tools and software
• Supplies sample circuits that are not copyrighted or patented, so
readers can freely use them in their own applications
• Covers selected topics and examples that provide solutions to
Julio Sanchez
problems that practicing engineers may encounter and are not
readily found in the literature Maria P. Canton
Designed to be functional and hands-on, this book provides sample
circuits with their corresponding programs. It clearly depicts and
labels the circuits, in a way that is easy to follow and reuse. The
book matches sample programs to the individual circuits and
discusses general programming techniques.

K16291
 Microcontrollers
HIGH-PERFORMANCE SYSTEMS
AND PROGRAMMING

K16291_FM.indd 1 9/24/13 11:25 AM

K16291_FM.indd 2 9/24/13 11:25 AM
 Microcontrollers
HIGH-PERFORMANCE SYSTEMS
AND PROGRAMMING

Julio Sanchez
Eastern Florida State College

Maria P. Canton
Brevard Public Schools

Boca Raton London New York

CRC Press is an imprint of the

Taylor & Francis Group, an informa business

K16291_FM.indd 3 9/24/13 11:25 AM

CRC Press
Taylor & Francis Group
6000 Broken Sound Parkway NW, Suite 300
Boca Raton, FL 33487-2742
© 2014 by Taylor & Francis Group, LLC
CRC Press is an imprint of Taylor & Francis Group, an Informa business

No claim to original U.S. Government works

Version Date: 20130923

International Standard Book Number-13: 978-1-4665-6668-2 (eBook - PDF)

This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been
made to publish reliable data and information, but the author and publisher cannot assume responsibility for the valid-
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 Table of Contents

Preface xx

Chapter 1 Microcontrollers for Embedded Systems 1

1.1 Embedded Systems 1
1.2 Microchip PIC 1
1.2.1 PIC Architecture 2
1.2.2 Pro gramming the PIC 2
PIC Programmers 3
Development Boards 4
1.3 PIC Architec ture 4
1.3.1 Baseline PIC Family 5
PIC10 devices 6
PIC12 Devices 7
1.3.2 Mid-Range Family 9
PIC14 Devices 9
PIC16 Devices 9
1.3.3 High-Perfor mance PICs and DSPs 10
Digital Signal Processor 11
Analog-to-Digital 12

Chapter 2 PIC18 Architecture 13

2.1 PIC18 Family Over view 13
2.1.1 PIC18FXX2 Group 14
2.1.2 PIC18FXX2 Device Group Over view 15
2.1.3 PIC18F4X2 Block Diagram 16
2.1.4 Central Process ing Unit 17
Status Register 17
Program Counter Register 17
Hardware Multiplier 18
Inter rupts 18
2.1.5 Special CPU Features 19
Watch dog Timer 20
Wake-Up by In ter rupt 21
Low Voltage Detection 21
Device Configuration 21
2.2 Memory Organization 22
2.2.1 Program Memory 22

v
vi Table of Contents

2.2.2 18FXX2 Stack 23

Stack Operations 23
Fast Reg ister Stack 24
Instructions in Memory 25
2.2.3 Data Mem ory 25
2.2.4 Data EEPROM Mem ory 27
2.2.5 Indirect Addressing 28
2.3 PIC18FXX2 Oscillator 29
2.3.1 Oscil lator Options 29
Crystal Oscil lator and Ceramic Resonator 29
RC Oscillator 30
Exter nal Clock Input 31
Phase Locked Loop Os cillator Mode 31
2.4 System Reset 31
2.4.1 Re set Ac tion 32
Power-On Reset (POR) 33
Power-Up Timer (PWRT) 33
Oscillator Start-Up Timer (OST) 33
PLL Lock Time-Out 33
Brown-Out Re set (BOR) 33
Time-Out Sequence 33
2.5 I/O Ports 34
2.5.1 Port Reg isters 34
2.5.2 Parallel Slave Port 35
2.6 Inter nal Modules 35
2.6.1 PIC18FXX2 Mod ules 35

Chapter 3 Programming Tools and Software 37

3.1 Environment 37
3.1.1 Embedded Sys tems 37
3.1.2 High- and Low-Level Languages 38
3.1.3 Lan guage-Spe cific Soft ware 40
3.2 Microchip's MPLAB 40
3.2.1 MPLAB X 40
3.2.2 Development Cycle 40
3.3 An Integrated Development Environment 41
3.3.1 Install ing MPLAB 42
3.3.2 Creating the Pro ject 43
3.3.3 Setting the Project Build Options 45
3.3.4 Adding a Source File 47
3.3.5 Building the Pro ject 48
3.3.6 .hex File 48
3.3.7 Quickbuild Op tion 50
3.4 MPLAB Simulators and Debuggers 50
3.4.1 MPLAB SIM 51
Using Break points 51
Watch Window 52
Simulator Trace 52
3.4.2 MPLAB Stimulus 54
Stimulus Dialog 54
3.4.3 MPLAB Hard ware Debuggers 55
Table of Contents vii

3.4.4 An Improvised Debugger 56

3.5 Development Programmers 56
3.5.1 Micro chip PICkit 2 and PICkit 3 58
3.5.2 Micropro USB PIC Programmer 60
3.5.3 MPLAB ICD 2 and ICD 3 In-Cir cuit Debuggers/Programmers 60
3.6 Test Circuits and Development Boards 61
3.6.1 Commercial Development Boards 61
3.6.2 Cir cuit Prototype 63
3.6.3 Breadboard 64
Limitations of Breadboards 65
Breadboarding Tools and Techniques 66
3.6.4 Wire Wrapping 67
3.6.5 Perfboards 67
3.6.6 Printed Cir cuit Boards 68

Chapter 4 Assembly Language Program 71

4.1 Assembly Language Code 71
4.1.1 A Coding Template 71
Pro gram Header 73
Program Environment Directives 73
Configuration Bits 73
Er ror Mes sage Level Control 74
Variables and Constants 74
Code Area and In ter rupts 74
4.1.2 Programming Style 74
Source File Comments 75
4.2 Defining Data Elements 75
4.2.1 equ Di rec tive 76
4.2.2 cblock Direc tive 76
4.2.3 Access to Banked Mem ory 77
4.3 Naming Conventions 77
4.3.1 Reg ister and Bit Names 77
4.4 PIC 18Fxx2 Instruction Set 79
4.4.1 Byte-Oriented In structions 80
4.4.2 Bit-Oriented In structions 80
4.4.3 Lit eral Instructions 80
4.4.4 Con trol Instructions 80

Chapter 5 PIC18 Programming in C Language 85

5.1 C Compilers 85
5.1.1 C versus As sem bly Language 85
5.1.2 MPLAB C18 86
5.2 MPLAB C18 Installation 86
5.2.1 MPLAB Software Com ponents 87
5.2.2 Configuration Options 88
5.2.3 Sys tem Re quirements 89
5.2.4 Execution Flow 90
5.3 C Compiler Project 91
5.3.1 Creating the Pro ject 91
viii Table of Contents

Select Hardware Device 92

Select the Language Toolsuite 92
Create a New Pro ject 93
Add Files to the Project 95
5.3.2 Select ing the Build Di rec tory 96
5.4 A First Program in C 98
5.4.1 Source Code Anal ysis 99
main() Function 100
Local Functions 101

Chapter 6 C Language in an Embedded Environment 103

6.1 MPLAB C18 Sys tem 103
6.1.1 PIC18 Ex tended Mode 104
6.2 MPLAB C18 Librar ies 104
6.2.1 Start-Up Rou tines 104
6.2.2 Online Help for C18 and Librar ies 105
6.3 Processor-Independent Libraries 106
6.3.1 General Software Library 106
Character Classification Functions 107
Data Conversion Functions 107
Memory and String Manipulation Functions 108
Delay Functions 110
Reset Functions 111
Character Output Functions 112
6.4 Processor-Specific Librar ies 115
6.4.1 Hardware Peripheral Library Func tions 115
6.4.2 Soft ware Peripherals Library Functions 116
6.4.3 Macros for Inline Assem bly 116
6.4.4 Proces sor-Spe cific Header Files 117
6.5 Math Librar ies 118
6.5.1 ANSI-IEEE 754 Bi nary Float ing-Point Standard 118
Encodings 119
Rounding 119
6.5.2 Standard Math Li brary Func tions 120
6.5.3 Float ing-Point Math Sam ple Pro gram 120
6.6 C18 Language Specifics 122
6.6.1 C18 Integer Data Types 122
6.6.2 C18 Float ing-Point Data Types 122
6.6.3 Endianness 123
6.6.4 Storage Classes 123
6.6.5 Static Func tion Ar gument 123
6.6.6 Storage Qualifi ers 123
far and near Qual ifi ers 123
rom and ram Qualifi ers 124

Chapter 7 Programming Simple Input and Output 125

7.1 Port-Connected I/O 125
7.1.1 A Sim ple Circuit and Code 125
7.1.2 Cir cuit Schemat ics 125
7.1.3 Assem bler Sim ple I/O Pro gram 126
Table of Contents ix

7.1.4 Assem bler Source Code Analysis 129

Command Monitor ing Loop 129
Action on the LEDs 130
A Delay Routine 130
7.2 C Language Simple I/O Program 131
7.2.1 C Source Code Anal ysis 132
main() Function 133
7.3 Seven-Segment LED Programming 134
7.3.1 Com puted Goto 135
7.3.2 Assem bler Seven-Seg ment LED Program 136
Access Bank Operation 136
Port A for Digital Operation 137
DIP Switch Processing 138
Seven-Seg ment Code with Computed Goto 139
7.3.3 Assem bler Table Lookup Sam ple Pro gram 140
7.4 C Language Seven-Segment LED Programs 141
7.4.1 Code Selection by Switch Construct 142
7.4.2 Code Selection by Table Lookup 142
7.5 A Demonstration Board 143
7.6.1 Power Sup ply 145
Voltage Regulator 145

Chapter 8 Interrupts 147

8.1 Interrupt Mechanism 147
8.2 PIC18 Interrupt System 147
8.2.1 Hardware Sources 148
8.2.2 Inter rupt Con trol and Status Reg isters 148
INTCON Registers 149
PIE Registers 151
PIR Registers 152
IPR Registers 152
8.2.3 Inter rupt Prior ities 154
High-Prior ity Inter rupts 154
Low-Prior ity Inter rupts 155
An Inter rupt Inter rupting Another One 155
8.2.4 Context Saving Operations 155
Context Saving during Low-Prior ity Inter rupts 156
8.3 Port B Interrupts 157
8.3.1 Port B Ex ter nal In ter rupt 158
8.3.2 INT0 In ter rupt Demo Program 158
cblock Directive 158
Vectoring the In ter rupt 159
Initialization 160
Setup INT0 160
Pro gram Foreground 161
Inter rupt Ser vice Routine 161
Switch Debouncing 162
Inter rupt Action 162
8.3.3 Port B Line Change Inter rupt 163
Reentrant Inter rupts 164
Multiple Exter nal Inter rupts 165
x Table of Contents

8.3.4 Port B Line Change Inter rupt Demo Program 165

Set ting Up the Line Change In ter rupt 165
Inter rupt Ser vice Routine 166
8.4 Sleep Mode and Interrupts 168
8.4.1 Wake-Up from SLEEP 169
8.4.2 Sleep_Demo Pro gram 170
8.5 Interrupt Programming in C Language 171
8.5.1 Inter rupt Ac tion 171
Context in the Stack 172
Inter rupt Data 172
8.5.2 Inter rupt Pro gramming in C18 173
Sleep Mode and RB0 Inter rupt Demo Program 174
Port B Inter rupt on Change Demo Program 176

Chapter 9 Delays, Counters, and Timers 179

9.1 PIC18 Family Timers 179
9.2 De lay Timers 179
9.2.1 Power-Up Timer (PWRT) 179
9.2.2 Oscillator Start-Up Timer (OST) 180
9.2.3 Phase Locked Loop (PLL) 180
Power-Up De lay Sum mary 181
9.2.4 Watch dog Timer 181
Watch dog Timer Uses 181
9.3 Hardware Timer-Counters 182
9.4 Timer0 Module 182
9.4.1 Timer0 Ar chitec ture 184
16-bit Mode Operation 184
Timer and Counter Modes 185
Timer0 Inter rupt 185
Exter nal Clock Source 185
Timer0 Prescaler 186
9.4.2 Timer0 as a De lay Timer 186
Long Delay Loops 187
Delay Accuracy Issues 188
Black–Ammerman Method 188
Delays with 16-Bit Timer0 189
9.4.3 Coun ter and Timer Programming 189
Pro gramming a Counter 190
Timer0_as_Counter.asm Program 190
A Timer/Coun ter Test Cir cuit 191
Timer0 _Delay.asm Program 191
A Variable Time-Lapse Routine 193
Timer0_VarDelay.asm Program 193
Inter rupt-Driven Timer 196
9.5 Other Timer Modules 199
9.5.1 Timer1 Mod ule 199
Timer1 in Timer Mode 200
Timer1 in Syn chro nized Counter Mode 201
Exter nal Clock In put Tim ing in Syn chro nized Mode 201
Timer1 Read and Write Op erations 201
16-bit Mode Timer1 Write 201
Table of Contents xi

16-Bit Read-Mod ify-Write 202

Reading and Writ ing Timer1 in Two 8-bit Operations 202
9.5.2 Timer2 Mod ule 203
Timer Clock Source 204
TMR2 and PR2 Registers 204
Prescaler and Postscaler 205
Timer2 Initial ization 205
9.5.3 Timer3 Mod ule 205
Timer3 in Timer Mode 207
Timer3 in Syn chro nized Counter Mode 207
Exter nal Clock Input Timing 208
Timer3 in Asyn chron ous Counter Mode 208
Exter nal Clock In put Tim ing with Unsynchronized Clock 208
Timer3 Reading and Writ ing 208
Writ ing in 16-Bit Mode 208
16-bit Read-Modify-Write Operation 209
Reading in Asyn chron ous Counter Mode 209
Timer1 Os cillator in Timer3 210
9.6 C-18 Timer Functions 210
9.6.1 CloseTimerx Func tion 210
9.6.2 OpenTimerx Func tion 211
9.6.3 ReadTimerx Function 211
9.6.4 WriteTimerx Func tion 212
9.7 Sample Programs 212
9.7.1 Timer0_as_Coun ter pro gram 212
9.7.2 Timer0_De lay Pro gram 215
9.7.3 Timer0_VarDelay Pro gram 216
9.7.4 Timer0_VarInt Pro gram 220
9.7.5 C_Timer_Show Program 224

Chapter 10 Data EEPROM 227

10.1 EEPROM on the PIC18 Microcontrollers 227
10.1.2 On-Board Data EEPROM 227
10.2 EEPROM Programming 228
10.2.1 Read ing EEPROM Data 228
10.2.2 Writ ing EEPROM Data 230
10.3 Data EEPROM Programming in C Language 231
10.3.1 EEPROM Li brary Func tions 232
10.3.2 Sample Code 232
10.4 EEPROM Demonstration Programs 233
10.4.1 EEPROM_to_7Seg Pro gram 233
10.4.2 C_EEPROM_Demo Pro gram 237

Chapter 11 Liquid Crystal Displays 239

11.1 LCD 239
11.1.1 LCD Features and Architec ture 239
11.1.2 LCD Functions and Com ponents 240
Inter nal Registers 240
Busy Flag 240
Address Coun ter 240
xii Table of Contents

Display Data RAM (DDRAM) 240

Character Generator ROM (CGROM) 241
Character Generator RAM (CGRAM) 241
Timing Generation Circuit 241
Liquid Crystal Dis play Driver Circuit 242
Cursor/Blink Con trol Cir cuit 242
11.1.3 Con nectiv ity and Pin Out 242
11.2 Interfacing with the HD44780 243
11.2.1 Busy Flag and Timed Delay Op tions 244
11.2.2 Con trast Control 245
11.2.3 Dis play Backlight 245
11.2.4 Dis play Mem ory Map ping 245
11.3 The HD44780 Instruction Set 247
11.3.1 Instruction Set Over view 247
Clear ing the Dis play 248
Return Home 248
Entry Mode Set 248
Display and Cur sor ON/OFF 248
Cursor/Dis play Shift 248
Func tion Set 248
Set CGRAM Address 249
Set DDRAM Address 249
Read Busy Flag and Address Reg ister 249
Write data 249
Read data 250
11.3.2 18F452 8-Bit Data Mode Cir cuit 250
11.4 LCD Programming 251
11.4.1 De fin ing Constants and Variables 252
Constants 252
11.4.2 Us ing MPLAB Data Di rec tives 253
Data Def inition in Ab solute Mode 253
Relocatable Code 254
Issues with Initial ized Data 254
11.4.3 LCD Initial ization 255
Reset Function 255
Initial ization Commands 256
Function Preset Command 256
Func tion Set Command 256
Display Off 257
Display and Cur sor On 257
Set En try Mode 258
Cursor and Dis play Shift 258
Clear Display 258
11.4.4 Auxiliary Operations 259
Time De lay Routine 259
Puls ing the E Line 260
Reading the Busy Flag 261
Bit Merging Operations 262
11.4.5 Text Data Storage and Display 264
Generating and Stor ing a Text String 265
Data in Program Memory 265
Displaying the Text String 266
Sam ple Pro gram LCD_18F_MsgFlag 268
Table of Contents xiii

11.5 Data Compression Techniques 278

11.5.1 4-Bit Data Transfer Mode 279
11.5.2 Preserving Port Data 279
11.5.3 Master/Slave Sys tems 280
11.5.4 4-Bit LCD Inter face Sam ple Pro grams 281
11.6 LCD Programming in C18 291
11.6.1 Edit ing xlcd.h 292
Defining the Inter face 292
Defin ing the Data Port and Tris Register 293
11.6.2 Timing Routines 294
11.6.3 XLCD Library Func tions 295
BusyXLCD 295
OpenXLCD 296
putrXLCD 296
putsXLCD 296
ReadAddr 296
ReadDataXLCD 297
SetDDRamAddr 297
SetCGRamAddr 297
WriteCmdXLCD 298
WriteDataXLCD 298
11.7 LCD Application Development in C18 299
11.7.1 Us ing the Pro ject Wizard 299
Main Pro gram File 300

Chapter 12 Real-Time Clocks 303

12.1 Measur ing Time 303
12.1.1 Clock Signal Source 303
32 kHz Crystal Cir cuit 304
12.1.2 Programming the Timer1 Clock 305
Set ting Up Timer1 Hard ware 305
Coding the Inter rupt Handler 306
Sam ple Pro gram RTC_18F_Timer1.asm 306
12.2 Real-Time Clock ICs 309
12.2.1 NJU6355 310
12.2.2 6355 Data For mat ting 310
12.2.3 Initial ization and Clock Primitives 311
Reading and Writ ing Clock Data 311
Initialize RTC 314
12.2.4 BCD Conversions 316
12.3 RTC Demonstration Circuit and Program 318
12.3.1 RTC_F18_6355.asm Pro gram 318
Code Details 319
Code List ing 319
12.4 Real-Time Clocks in C18 336
12.4.1 Timer1-Based RTC in C18 336
xiv Table of Contents

Chapter 13 Analog Data and Devices 343

13.1 Operations on Computer Data 343
13.2 18F452 A/D Hardware 343
13.2.1 A/D Mod ule on the 18F452 344
ADCON0 Register 345
ADCON1 Register 347
SLEEP Mode Operation 348
13.2.2 A/D Mod ule Sam ple Circuit and Program 349
Initial ize A/D Module 350
A/D Conversion 351
13.2.3 A2D_Pot2LCD Program 352
13.3 A/D Conversion in C18 365
13.3.1 Conversion Primitives 365
Busy ADC 365
CloseADC 365
ConvertADC 366
OpenADC 366
ReadADC 367
SetChan ADC 367
13.3.2 C_ADConvert.c Pro gram 368
C_ADConvert.c Code List ing 368
13.4 Interfacing with Analog Devices 371
13.4.1 LM 34 Temperature Sen sor 371
13.4.2 LM135 Circuits 372
Calibrating the Sensor 372
13.4.3 C_ADC_LM35.c Pro gram 373

Chapter 14 Operating Systems 377

14.1 Time-Critical Systems 377
14.1.2 Multitasking in Real-Time 378
14.2 RTOS Scope 378
14.2.1 Tasks, Prior ities, and Deadlines 379
14.2.2 Execut ing in Real-Time 381
14.3 RTOS Programming 381
14.3.1 Foreground and Background Tasks 382
Inter rupts in Tasking 382
14.3.2 Task Loops 383
14.3.3 Clock-Tick In ter rupt 383
14.3.4 Inter rupts in Preemptive Multitasking 383
14.4 Constructing the Scheduler 384
14.4.1 Cy clic Scheduling 384
14.4.2 Round-Robin Sched uling 385
14.4.3 Task States and Prior itIzed Scheduling 385
14.5 A Small System Example 386
14.5.1 Task Structure 386
14.5.2 Semaphore 387
14.6 Sample OS Application 388
Table of Contents xv

Appendix A MPLAB C18 Language Tutorial 413

A.1 In This Appendix 413
A.1.1 About Programming 413
A.1.2 Communicating with an Alien Intelli gence 414
A.1.3 Flowcharting 415
A.1.4 C Language Rules 417
Comments 418
Pro gram Header 418
Programming Templates 419
A.2 Structure of a C Program 419
A.2.1 Sample Program C_LEDs_ON 420
Identifiers 420
Reserved Words 421
main() Function 421
A.2.2 Sam ple Pro gram C_LEDs_Flash 422
Expressions and Statements 423
Variables 423
Scope and Lifetime of a Variable 425
Constants 426
Local Functions 427
A.2.3 Coding Style 428
A.3 C Language Data 428
A.3.1 Numeric Data 429
A.3.2 Alphanumeric Data 430
A.3.3 Ar rays of Alphanumeric Data 430
A.3.4 Ar rays of Nu meric Data 431
A.4 Indirection 431
A.4.1 Storage of C Lan guage Variables 432
A.4.2 Address of Operator 432
A.4.3 Indirection Operator 433
A.4.4 Point ers to Array Variables 434
A.4.5 Pointer Arith metic 435
A.5 C Language Operators 436
A.5.1 Operator Action 436
A.5 2 Assignment Operator 437
A.5.3 Arithmetic Operators 438
Remainder Operator 439
A.5.4 Concatenation 439
A.5.5 Incre ment and Dec rement 440
A.5.6 Relational Operators 441
A.5.7 Logical Operators 442
A.5.8 Bitwise Operators 443
AND Operator 445
OR Operator 446
XOR Operator 447
NOT Operator 447
Shift-Left and Shift-Right Operators 448
A.5.9 Compound Assignment Operators 449
A.5.10 Operator Hierarchy 449
Associativity Rules 450
A.6 Directing Program Flow 451
xvi Table of Contents

A.6.1 Decisions Con structs 451

if Con struct 451
Statement Blocks 452
Nested if Construct 452
else Construct 454
Dangling else Case 454
else-if Clause 456
switch Con struct 457
Conditional Expressions 460
A.7 Loops and Program Flow Control 460
A.7.1 Loops and It erations 461
A.7.2 Elements of a Pro gram Loop 461
A.7.3 for Loop 462
Compound Statement in Loops 464
while Loop 464
do-while Loop 465
A.8 Breaking the Flow 466
A.8.1 goto Statement 466
A.8.2 break Statement 467
A.8.3 continue Statement 468
A.9 Functions and Struc tured Programming 469
A.9.1 Modular Construction 469
A.9.2 Structure of a Func tion 470
Function Prototype 470
Function Definition 471
Func tion Call 471
Return Keyword 472
Matching Arguments and Parameters 473
A.10 Visibility of Function Arguments 474
A.10.1 Using Ex ter nal Variables 474
A.10.2 Pass ing Data by Reference 475
Point ers and Func tions 475
Pass ing Ar ray Variables 476
A.10.3 Func tion-Like Macros 477
Macro Ar gument 477
A.11 Structures, Bit Fields, and Unions 478
A.11.1 Structure Declaration 478
Structure Type Dec laration 479
Structure Variable Declaration 479
A.11.2 Access ing Structure Elements 480
Initializing Structure Variables 481
Manipulat ing a Bit Field 482
Type Cast ing 484
A.11.3 Unions 484
A.11.4 Structures and Functions 485
Point ers to Structures 485
Pointer Member Op erator 485
Pass ing Structures to Func tions 486
A.11.5 Structures and Un ions in MPLAB C18 487
Table of Contents xvii

Appendix B Debugging 18F Devices 491

B.1 Art of Debugging 491
B.1.1 Preliminary Debugging 492
B.1.2 De bugging the Logic 492
B.2 Software Debugging 493
B.2.1 Debugger-Less Debugging 493
B.2.2 Code Image Debugging 493
B.2.3 MPLAB SIM Features 494
Run Mode 494
Step Mode 494
Animate 494
Mode Dif ferences 494
Build Configurations 495
Setting Breakpoints 495
B.2.4 PIC 18 Spe cial Simulations 495
Reset Conditions 495
Sleep 495
Watch dog Timer 496
Special Registers 496
B.2.5 PIC 18 Peripherals 496
B.2.6 MPLAB SIM Controls 497
B.2.7 Viewing Commands 498
Dissasembly Listing 498
File Registers 499
Hardware Stack 500
Locals 500
Program Memory 500
Special Function Registers 501
Watch 502
Watch Window in C Language 504
B.2.8 Simulator and Tracing 504
Set ting Up a Trace 505
Trace Menu 506
B.2.9 Stimulus 507
Stimulus Basics 508
Using Stimulus 509
Asynch Tab 510
Message-Based Stimulus 510
Pin/Regis ter Actions Tab 510
Advanced Pin/Regis ter Tab 512
Clock Stimulus Tab 513
Register Injection Tab 514
Register Trace Tab 515
B.3 Hardware Debugging 516
B.3.1 Microchip Hardware Programmers/Debuggers 516
MPLAB ICD2 516
MPLAB ICD3 517
MPLAB ICE 2000 517
MPLAB ICE 4000 518
MPLAB REAL ICE 519
MPLAB PICkit 2 and PICkit 3 519
B.3.2 Us ing Hardware Debuggers 519
xviii Table of Contents

Which Hardware Debugger? 520

ICSP 520
B.3.3 MPLAB ICD2 Debugger Connectiv ity 521
Connection from Mod ule to Target 522
Debug Mode Requirements 523
Debug Mode Preparation 523
Debug Ready State 524
Breadboard Debugging 525
B.4 MPLAB ICD 2 Tutorial 526
B.4.1 Cir cuit Hardware 526
B.4.2 LedFlash_Reloc Program 527
B.4.3 Relocatable Code 527
Header Files 527
Program Memory 527
Configuration Requirements 528
RAM Allocations 528
LedFlash_Reloc.asm Program 529
B.4.4 De bugging Ses sion 531

Appendix C Building Your Own Circuit Boards 533

C.1 Drawing the Circuit Diagram 533
C.2 Printing the PCB Diagram 535
C.3 Transferring the PCB Image 535
C.4 Etching the Board 536
C.5 Finishing the Board 536
C.6 Backside Image 536

Appendix D PIC18 Instruction Set 539

Appendix E Number Systems and Data Encoding 633

E.1 Decimal and Binary Systems 633
E.1.1 Binary Number System 633
E.1.2 Radix or Base of a Num ber Sys tem 634
E.2 Decimal versus Binary Numbers 634
E.2.1 Hexadecimal and Octal 635
E.3 Character Representations 636
E.3.1 ASCII 636
E.3.2 EBCDIC and IBM 638
E.3.3 Unicode 639
E.4 Encoding of Integers 639
E.4.1 Word Size 640
E.4.2 Byte Order ing 641
E.4.3 Sign-Magnitude Representation 642
E.4.4 Radix Complement Representation 643
E.4.5 Simplification of Subtraction 645
E.5 Binary Encoding of Fractional Numbers 646
E.5.1 Fixed-Point Representations 647
E.5.2 Floating-Point Representations 648
Table of Contents xix

E.5.3 Standardized Floating-Point 649

E.5.4 Binary-Coded Decimals (BCD) 650
E.5.5 Float ing-Point BCD 650

Appendix F Basic Electronics 653

F.1 Atom 654
F.2 Isotopes and Ions 654
F.3 Static Elec tric ity 655
F.4 Electrical Charge 656
F.4.1 Volt age 656
F.4.2 Cur rent 656
F.4.3 Power 657
F.4.4 Ohm's Law 657
F.5 Electrical Circuits 658
F.5.1 Types of Circuits 658
F.6 Circuit Elements 660
F.6.1 Resistors 661
F.6.2 Revisit ing Ohm's Law 661
F.6.3 Re sis tors in Series and Parallel 662
F.6.4 Capacitors 664
F.6.5 Capacitors in Series and in Parallel 665
F.6.6 Inductors 666
F.6.7 Transformers 667
F.7 Semiconductors 667
F.7.1 Integrated Circuits 668
F.7.2 Semiconduc tor Electronics 668
F.7.3 P-Type and N-Type Sil icon 669
F.7.4 Di ode 669

Index 671
 Preface

Microcontrollers: High-Performance Systems and Programming can be considered

a con tinuation of and a complement to our previous two titles on the subject of
microcontroller programming. In the present book we fo cus on the line of high-per-
forance microcontrollers offered by Microchip. In addition to their enhanced fea -
tures, extended peripherals, and improved performance, there are several practical
fac tors that make the high-per for mance PIC se ries a better choice than their
mid-range pre deces sors for most sys tems:
• The pos si bil ity of pro gram ming high-per for mance microcontrollers in a
high-level language (C language).
• Source code compatibility with PIC16 microcontrollers, which facilitates code
migration from mid-range to PIC18 devices.
• Pin compatibility of some PIC18 devices with their PIC16 predecessors. This
makes possible the reuse of PIC16 controllers in circuits originally designed for
mid-range hardware. For example, the PIC18F442 and PIC18F452 in 40-pin DIP
configuration are pin-compatible with the popular PIC16F877. Similarly, the
PIC18F242 and PIC18F252, in 28-pin DIP format, are pin compatible with the
PIC16F684.
• Microchip pricing policy makes available the high-performance chips at a lower
cost than their mid-range equivalents. Recently we have priced the 18F452 at
$6.32 while the 16F877 sells from the same source at $6.72.
Expanded functionality, high-level programmability, architectural improvements
that sim plify hard ware im ple men ta tion, code and pin-lay out com pat i bil ity, and
lower cost make it easy to select a high-performance PIC over its mid-range coun-
terpart. One con sideration that is sometimes mentioned in favor of the mid-range
devices is the abundance of pub lished applica tion circuits and code samples. Our
book at tempts to cor rect this. Although it should also be mentioned that some
PIC16 processors with small footprints have no PIC18 equiv alent, which explains
why some mid-range devices continue to hold a share of the microcontroller mar-
ketplace.

Like our preced ing titles in this field, the book is intended as a ref erence and re -
source for en gineers, scientists, and electronics enthusiasts. The book focuses on
the needs of the working professional in the fields of electrical, electronic, com-

xxi
xxii Preface

puter, and software en gineering. In developing the material for this book, we have
adopted the following rules:
1. The use of standard or off-the-shelf components such as input/output devices, in-
tegrated circuits, motors, and programmable microcontrollers, which readers
can easily duplicate in their own circuits.
2. The use of inexpensive or freely available development tools for the design and
prototyping of embedded systems, such as electronic design programs, program-
ming languages and environments, and software utilities for creating printed cir-
cuit boards.
3. Our sample circuits and programs are not copyrighted or patented so that readers
can freely use them in their own applications.
Our book is designed to be func tional and hands-on. The resources furnished to
the reader include sample circuits with their corresponding programs. The circuits
are depicted and labeled clearly, in a way that is easy to follow and reuse. Each cir-
cuit includes a parts list of the resources and components required for its fabrica -
tion. For the most important circuits, we also provide tested PCB files. The sample
programs are matched to the individual circuits but general programming tech-
niques are also discussed in the text. There are appendices with useful information
and the book's online software contains a listing of all the sample programs devel-
oped in the text.

Julio Sanchez

Maria P. Canton
 Chapter 1

Microcontrollers for Embedded Systems

1.1 Embedded Systems

An embedded system is a computer with specific control functions. It can be part of a
larger computer system or a stand-alone device. Most embedded systems must op er-
ate within real-time constraints. Embedded systems contain programmable proces-
sors that are either microcontrollers or dig ital sig nal pro cessors (DSPs). The
embedded system is sometimes a general-purpose device, but more often it is used in
specialized applications such as washing machines, telephones, microwave ovens,
automobiles, and many different types of weapons and military hard ware.

A microcontroller or DSP usually includes a cen tral processor, input and out put
ports, memory for program and data stor age, an in ternal clock, and one or more pe -
ripheral devices such as timers, counters, analog-to-digital converters, serial com-
munica tion facilities, and watch dog circuits. More than two dozen companies in the
United States and abroad manufac ture and mar ket microcontrollers. Mostly they
range from 8- to 32-bit devices. Those at the low end are intended for very simple
circuits and provide limited functions and program space, while the ones at the high
end have many of the fea tures associated with microprocessors. The most popular
microcontrollers include several from Intel (such as the 8051), from Zilog (deriva-
tives of their famous Z-80 microprocessor) from Motorola (such as the 68HC05),
from Atmel (the AVR), the Parallax (the BASIC Stamp), and many from Microchip.
Some of the high-end Microchip microcontrollers and DSPs are the topic of this
book.

1.2 Microchip PIC

The names PIC and PICmicro are trade marks of Microchip Tech nology. Microchip
prefers the latter designation because PIC is a registered trademark in some European
countries. It is usually assumed that PIC stands for Peripheral Interface Controller, al-
though the original acronym was Programmable Interface Controller. More recently,
Microchip has stated that PIC stands for Programmable Intelligent Computer, a much
nicer, albeit not historically true version of the acronym.

1
2 Chapter 1

The original PIC was built to complement a Gen eral Instruments 16-bit CPU des-
ignated the CP-1600. The first 8-bit PIC was developed in 1975 to improve the per-
formance of the CP-1600 by offloading I/O tasks from the CPU. In 1985, General
Instrument spun off its microelectronics division. At that time, the PIC was re-de-
signed with inter nal EPROM to produce a programmable controller. Today, hun-
dreds of ver sions and vari a tions of PIC microcontrollers are avail able from
Microchip. Typical on-board peripherals include input and output ports, serial com-
munication modules, UARTs, and motor control devices. Program memory ranges
from 256 words to 64k words and more. The word size varies from 12 to 14 or 16
bits, depending on the specific PIC family.

1.2.1 PIC Architecture

PIC microcontrollers contain an instructions set that var ies in length from 35 in struc-
tions for the low-end devices to more than 70 for the high end. The ac cumulator, which
is known as the work register in PIC documentation, is part of many instructions be-
cause the low- and mid-range PICs contain no other internal registers accessible to the
programmer. The PICs are programmable in their native Assembly Language. C lan-
guage and BASIC compilers have also been developed. Open-source Pascal, JAL, and
Forth compilers are also available, although not very popular.

It is often mentioned that one of the reasons for the success of the PIC is the sup-
port provided by Microchip. This support includes development software, such as a
professional-quality development environment called MPLAB, which can be down-
loaded free from the company's website (www.microchip.com). The MPLAB pack-
age includes an assembler, a linker, a debugger, and a simulator. Microchip also sells
an in-circuit debugger called MPLAB ICD 2. Other development products intended
for the professional market are also available from Microchip.

In addition to the de velopment software, the Microchip website contains a multi-

tude of free sup port documents, including data sheets, ap plica tion notes, and sam-
ple code. Furthermore, the PIC microcontrollers have gained the support of many
hobbyists, enthusiasts, and entrepreneurs who develop code and support products
and publish their results on the Internet. This community of PIC users is a treasure
trove of information and know-how easily accessible to the be ginner and useful
even to the professional. One such Internet re source is an open-source collection of
PIC tools named GPUTILS, which is distributed under the GNU General Public Li-
cense. GPUTILS includes an assembler and a linker. The software works on Linux,
Mac OS, OS/2, and Windows. Another product, called GPSIM™, is an open source
simulator featuring PIC hardware modules.

1.2.2 Programming the PIC

Stand-alone programming a PIC microcontroller requires the following tools and
components:
• An Assembler or high-level language compiler. The software package usually in-
cludes a debugger, simulator, and other support programs.
• A computer (usually a PC) on which to run the development software.
Microcontrollers for Embedded Systems 3

• A hardware device called a programmer that connects to the computer through

the serial, parallel, or USB line. The PIC is inserted in the programmer and “blown”
by downloading the executable code generated by the development system. The
hardware programmer usually includes the support software.
• A cable or connector for connecting the programmer to the computer.
• A PIC microcontroller.
Alternatively, some PIC microcontrollers can be programmed while installed in
their applica tions boards. Although this option can be very use ful as a production
and distribution tool, for reasons of space it is not discussed in this book.
PIC Programmers
The development system (assembler or compiler) and the programmer driver are the
software components. The computer, programmer, and con nec tors are the hard ware
elements. Figure 6.1 shows a commercial programmer that connects to the USB port
of a PC. The one in the illustration is made by MicroPro.

Figure 1.1 USB PIC programmer made by MicroPro.

Many other programmers are available on the market. Microchip offers several
high-end models with in-circuit serial programming (ICSP) and low-voltage pro -
gramming (LVP) capabilities. These devices allow the PIC to be programmed in the
target circuit. Some PICs can write to their own program memory. This makes possi-
ble the use of so-called bootloaders, which are small resident programs that allow
loading user software over the RS-232 or USB lines. Programmer/debugger combi-
nations are also offered by Microchip and other vendors.
4 Chapter 1

Development Boards
A development board is a demonstration circuit that usually contains an array of con -
nected and connectable com ponents. Their main purpose is as a learning and experi-
ment tool. Like programmers, PIC development boards come in a wide range of prices
and levels of complexity. Most boards target a specific PIC microcontroller or a PIC
family of related devices. Lacking a development board, the other op tion is to build
the circuits oneself, a time-consuming but valuable experience. Figure 1.2 shows the
LAB-X1 development board for the 16F87x PIC family.

Figure 1.2 LAB-X1 development board.

The LAX-X1 board, as well as sev eral other mod els, are prod ucts of
microEngineering Labs, Inc. Development boards from Microchip and other ven -
dors are also available.

1.3 PIC Architecture

PIC microcontrollers are roughly classified by Microchip into three groups: baseline,
mid-range, and high-performance. Figure 1.3 shows the com ponents of each PIC fam -
ily at the time of this writing.
Microcontrollers for Embedded Systems 5

Microchip PIC and dsPIC Families

MPLAB DEVELOPMENT ENVIRONMENT
Baseline family
Mid-range family
High-performance family

PIC10 PIC12 PIC16 PIC18 PIC24F PIC24H dsPIC30 dsPIC32 PIC32

8-bit 16-bit 32-bit
Assembly Language MPLAB C Compiler programmable
programmable

Figure 1.3 Microchip PIC and dsPIC families.

Within each of the groups the PIC are classified based on the first two digits of
the PIC's family type. However, the sub-classification is not very strict, as there is
some overlap. In fact, we find PICs with 16X designations that belong to the base -
line family and others that be long to the mid-range group. In the fol lowing sub-sec-
tions we describe the basic charac teristics of the var ious sub-groups of the three
major PIC families with 8-bit architectures.Table 1.1 shows the principal hardware
characteristics of each of the four 8-bit PIC families
Table 1.1
8-bit PIC Architec tures Compar ison Chart
BASELINE MID-RANGE ENHANCED PIC18

Pin Count 6-40 8-64 8-64 18-100

In ter rupts No Sin gle in ter rupt Sin gle in ter rupt Mul ti ple
Con text saved In ter rupts
Con text saved
Per for mance 5 MIPS 5 MIPS 8 MIPS Up to 16 MIPS
In struc tions 33, 12-bit 35, 14-bit 49, 14-bit 83, 16-bit
Pro gram Mem ory Up to 3 KB Up to 14 KB Up to 28 KB Up to 128 KB
Data Mem ory 138 Bytes 368 Bytes 1,5 KB 4 KB
Hard ware Stack 2 level 8 level 16 level 32 level
To tal Num ber
of Devices 16 58 29 193
Fam i lies PIC10 PIC12 PIC12FXXX PIC18
PIC12 PIC16 PIC16F1XX
PIC14
PIC16

1.3.1 Baseline PIC Family

This group includes members of the PIC10, PIC12, PIC14, and PIC16 families. The de-
vices in the baseline group have 12-bit program words and are supplied in 6- to 28-pin
packages. The microcontrollers in the baseline group are described as being suited for
6 Chapter 1

battery-operated applications because they have low power requirements. The typi-
cal member of the base line group has a low pin count, flash program memory, and low
power requirements. The following types are in the Baseline group:
• PIC10 devices
• PIC12 devices
• PIC14 devices
• Some PIC16 devices
We present a short summary of the func tionality and hardware types of the base-
line PICs in the sec tions that follow, although these de vices are not cov ered in this
book.

PIC10 devices
The PIC10 devices are low-cost, 8-bit, flash-based CMOS microcontrollers. They use
33 single-word, single-cycle instructions (except for program branches, which take
two cycles. The instructions are 12-bits wide. The PIC10 devices feature power-on re-
set, an internal oscillator mode which saves hav ing to use ports for an external oscilla-
tor. They have a power-saving SLEEP mode, A Watch dog Timer, and optional code
protection.

The recommended applications of the PIC10 family range from personal care ap-
pliances and security systems to low-power remote transmitters and receivers. The
PICs of this family have a small footprint and are manufac tured in formats suitable
for both through hole or surface mount technologies. Table 1.2 lists the charac teris-
tics of the PIC10F devices.
Table 1.2
PIC10F Devices
10F200 10F202 10F204 10F206

Clock:
Max i mum Fre quency
of Op era tion (MHz) 4 4 4 4
Mem ory:
Flash Program
Mem ory 256 512 256 512
Data Mem ory (bytes) 16 24 16 24
Pe riph er als:
Timer Mod ule(s) TMR0 TMR0 TMR0 TMR0
Wake-up from Sleep Yes Yes Yes Yes
Com para tors 0 0 1 1
Fea tures:
I/O Pins 3 3 3 3
In put Only Pins 1 1 1 1
In ter nal Pull-ups es Yes Yes Yes
In-Cir cuit Se rial
Pro gram ming Yes Yes Yes Yes
In struc tions 33 33 33 33
Pack ages: --------------------------------- 6-pin SOT-23 -------------------------------
----------------------------------- 8-pin PDIP --------------------------------
Microcontrollers for Embedded Systems 7

Two other PICs of this series are the 10F220 and the 10F222. These versions in-
clude four I/O pins and two analog-to-digital converter channels. Program memory
is 256 words on the 10F220 and 512 in the 10F222. Data memory is 16 bytes on the
F220 and 23 in the F222.

PIC12 Devices
The PIC12C5XX fam ily are 8-bit, fully static, EEPROM/EPROM/ROM-based CMOS
microcontrollers. The devices use RISC architecture and have 33 single-word, sin-
gle-cycle instructions (except for program branches that take two cycles). Like the
PIC10 family, the PIC12C5XX chips have power-on reset , device reset, and an internal
timer. Four oscillator options can be selected, including a port-saving internal oscilla-
tor and a low-power oscillator. These devices can also operate in SLEEP mode and
have watchdog timer and code pro tec tion features.

The PIC12C5XX devices are recommended for applications ranging from per-
sonal care appliances, security systems, and low-power remote transmitters and re-
ceivers. The internal EEPROM memory makes possible the storage of user-defined
codes and passwords as well as appliance setting and receiver frequencies. The var-
ious packages allow through-hole or surface mount ing tech nologies. Table 1.3 lists
the characteristics of some selected members of this PIC family.
Table 1.3
PIC 12CXXX and 12CEXXX Devices

12C508(A) 12C518 12CE519 12C671 12CE674

12C509A 12C672
12CR509A 12C673
Clock:
Max i mum
Fre quency
of Op era tion
(MHz) 4 4 4 10 10
Mem ory:
EPROM
Pro gram
Mem ory
(bytes) 25/41/41 25 41 128 128
Pe riph er als:
EEPROM
Data Mem ory
(bytes) — 16 16 0/0/16 16
Timer
Mod ule(s) TMR0 TMR0 TMR0 TMR0 TMR0
A/D Converter
(8-bit)
Chan nels — — — 4 4
Fea tures:
Interrupt
Sources — — — 4 4
I/O Pins 5 5 5 5 5
Input Pins 1 1 1 1 1
(continues)
8 Chapter 1

Table 1.3
PIC 12CXXX and 12CEXXX Devices (continued)

12C508(A) 12C518 12CE519 12C671 12CE674

12C509A 12C672
12CR509A 12C673
Inter nal
Pull-ups Yes/Yes/No Yes Yes Yes Yes
In-Circuit
Serial
Programming Yes/No Yes Yes Yes Yes
Number of
Instructions 33 33 33 35 35
Packages 8-pin DIP 8-pin DIP 8-pin DIP 8-pin DIP 8-pin DIP
SOIC JW,SOIC JW. SOIC SOIC JW

Two other members of the PIC12 family are the 12F510 and the 16F506. In most
respects these devices are similar to the ones previously described, except that the
12F510 and 16F506 both have flash program memory. Table 1.4 lists the most impor-
tant features of these two PICs.
Table 1.4
PIC12F510 and 12F675

12F629 12F675
Clock:
Maximum Frequency of Operation (MHz) 20 20
Memory:
Flash Program Memory 1024 1024
Data Memory (SRAM bytes) 64 64
Peripherals:
Timers 8/16 bits 1/1 1/1
Wake-up from Sleep on Pin Change Yes Yes
Features:
I/O Pins 6 6
Analog comparator module Yes Yes
Analog-to-digital converter No 10-bit
In-Circuit Serial Programming Yes Yes
Enhanced Timer1 module Yes Yes
Interrupt capability Yes Yes
Number of Instructions 35 35
Relative addressing Yes Yes
Packages 8-pin PDIP, 8-pin PDIP
SOIC, SOIC,
DFN-S DFN-S

Two other members of the PIC12F are the 12F629 and 12F675. The only differ-
ence between these two devices is that the 12F675 has a 10-bit analog-to-digital con-
verter while the 629 has not A/D converter. Table 1.5 lists some important features
of both PICs.
Microcontrollers for Embedded Systems 9

Table 1.5
PIC12F629 and 12F675
12F629 12F675
Clock:
Maximum Frequency of Operation (MHz) 20 20

Memory:
Flash Program Memory 1024 1024
Data Mem ory (SRAM bytes) 64 64

Peripherals:
Tim ers 8/16 bits 1/1 1/1
Wake-up from Sleep on Pin Change Yes Yes

Features:
I/O pins 6 6
Analog comparator module Yes Yes
Analog-to-digital converter No 10-bit
In-cir cuit serial programming Yes Yes
Enhanced Timer1 mod ule Yes Yes
Inter rupt capability Yes Yes
Number of instructions 35 35
Relative addressing Yes Yes
Packages 8-pin PDIP 8-pin PDIP
SOIC SOIC
DFN-S DFN-S

Several members of the PIC12 family, 12F635, 12F636, 12F639, and 12F683, are
equipped with special power-management features (called nanowatt technology by
Microchip). These devices were especially designed for systems that require ex-
tended battery life.

PIC14 Devices
The single member of this family is the PIC14000, which is built with CMOS tech nol-
ogy. This makes the PIUC14000 fully static and gives it industrial temperature range.
The 14000 is recommended for battery chargers, power supply controllers, power
management system controllers, HVAC controllers, and for sensing and data acquisi-
tion applications.1.3.2

1.3.3 Mid-range PIC Family

The mid-range PICs includes members of the PIC12 and PIC16 groups as well as the
PIC 18 group. According to Microchip the mid-range PICs all have 14-bit program
words with either flash or OTP program memory. Those with flash program memory
also have EEPROM data memory and support interrupts. Some members of the
mid-range group have USB, I2C, LCD, USART, and A/D converters. Implementations
range form 8 to 64 pins.

PIC16 Devices
This is by far the largest mid–range PIC group. Currently over 80 versions of the PIC16
are listed in production by Microchip. Although we do not cover the mid-range devices
 10 Chapter 1

in this book, we have selected a few of its most prominent members of the PIC16 fam-
ily to list their most important fea tures. These are found in Table 1.6.
Table 1.6
PIC16 Devices
16C432 16C58 16C770 16F54 16F84A 16F946
Clock:

Maximum Frequency MHz 20 40 20 20 20 20

Memory:
Program memory type OTP OTP OTP Flash Flash Flash
K-bytes 3.5 3 3.5 0.75 1.75 14
K-words 2 2 2 0.5 1 8
Data EEPROM 0 0 0 0 64 256

Peripherals:
I/O channels 12 12 16 12 13 53
ADC channels 0 0 6 0 0 8
Comparators 0 0 0 0 0 2
Timers 1/8-bit 1/8-bit 2/8-bit 1/8-bit 1/8-bit 2/8-bit
1/16-bit 1/16-bit
Watchdog timer Yes Yes Yes Yes Yes Yes

Features:
ICSP Yes No Yes No Yes Yes
ICD No No No No 0 1
Pin count 20 18 20 18 18 64
Communications - - MPC/SPI - - AUSART
Packages 20/CERDIP, 18/CERDIP 20/CERDIP 18/PDIP 18/PDIp 64/TQFP
20/SSOP 18/PDIP 20/PDIP 18/SOIC 18/SOIC
208mil 18/SOIC 20/SOIC 300mil 300mil
300mil 300mil

Microchip documentation refers to an enhanced mid-range family composed of

PIC12FXXX and PIC16F1XX devices. These devices maintain compatibility with the
previous members of the mid-range family while providing additional performance.
Their most important new features include multiple interrupts, fourteen additional
instructions, up to 28 KB program memory, and additional peripheral modules.

1.3.3 High-Performance PICs and DSPs

The high-performance PICs belong to the PIC18 and PIC32 groups. The motiva tion for
expanding the PIC arquitecture and modifying the core of the mid-range PICs relate to
the following limita tions:
• Small-size stack
• Single interrupt vector
• Limited instruction set
• Small memory size
• Limited number of peripherals
• No high-level language programmability
The devices in the PIC16 group have 16-bit program words, flash program mem-
ory, a linear memory space of up to 2 Mbytes, as well as protocol-based communica-
tions facilities. They all support internal and external interrupts and a much larger
instruction set than members of the baseline and mid-range families. The PIC18
family is also a large one, with over seventy different variations currently in produc-
Microcontrollers for Embedded Systems 11

tion. These devices are furnished in 18 to 80 pin packages. Microchip describes the
PICs in this family as high-performance with integrated A/D converters.
Digital Signal Processor
The notion of digital signal processing starts with the conversion of analog signal in-
formation such as voice, image, temperature, or pressure primitive data to digital val-
ues that can be stored and manipulated by a com puting device. Convert ing the data
from its primitive analog form to a digital format makes it much easier to analyze, dis-
play, store, process, or convert the data to another format. Digital signal processing is
based on the fact that com puting and data pro cessing operations are easier to perform
on digital data than on raw analog signals.

The concept of digital signal processing can be illustrated by means of a satel-

lite-based Earth imagining system (such as the Landsat EROS) shown in Figure 1.4.
data storage

digitizer and
transmitter

sensor

optical
system
scanning
mirror

image data
processing

scan line

scanning
direction
receiving image
station

Figure 1.4 Schematic of a space-borne imaging system.

The optical-mechanical instrument onboard a spacecraft, shown in Figure 1.4,

consists of several subsystems. The scanning mirror collects the radiation, which is
imaged by an optical system onto a sensor device. The sensor performs an ana-
log-to-dig ital conversion and places the digital values in a temporary storage struc-
ture. During its orbit, the satellite reaches a location in space from which it can
communicate with an Earth receiving station. At this time, the transmitter and sup-
port circuitry send the digital data to the receiving station. The receiving station
12 Chapter 1

processes this data and formats it into an image. In this scheme, digital signal pro-
cessing can take place as the image data is sensed by the instrument and tempo-
rarily stored on board the satellite, or when the raw data received by the Earth
station is con verted into an image that can be manipulated, viewed, stored, or
re-processed.
Analog-to-Digital
Conversion from analog-to-digital form and vice versa are not formally operations of a
DSP. However, these conversions are so often required during signal processing that
most DSP devices include the analog-to-digital and digital-to-analog conversion hard-
ware.

Analog-to-digital conversion is usually performed by sampling the signal at uni-

form time intervals and using the sampled value as representative of the region be-
tween the intervals. Figure 1.5 shows an example of analog-to-digital conversion by
sampling.

sampling periods
1 2 3 4 5 6 7 8 9 10 11 12 13

80
voltage of analog signal

70

60

50

40

30

20 analog signal
10

0
15 20 28 37 12 14 35 78 69 63 85 57 28
sampled digital values

Figure 1.5 Analog-to-digital conversion by sampling.

In Figure 1.5 we see that the sampled values are actually an approximation of the
analog curve, as the variations between each interval are lost in the conversion pro-
cess. Therefore, the more sampling periods, the more accurate the approximation.
On the other hand, too small a sampling rate tends to re duce the sig nificance of the
data by producing repeated values in the digital record.
 Chapter 2

PIC18 Architecture

2.1 PIC18 Family Overview

The PIC18 family was designed to provide ease of use (programmable in C), high per-
formance, and effortless integration with previous 8-bit families. In addition to the
standard modules found in the PIC16 and previous families, the PIC18 includes sev-
eral advanced pe ripherals, such as CAN, USB, Ethernet, LCD and CTMU. Its principal
features are
• Nanowatt technology ensures low power consumption
• 83 instructions (16-bit wide)
• C language optimized
• Up to 2 MB addressable program memory
• 4KB maximum RAM
• 32-level hardware stack
• 8-bit file select register
• Integrated 8x8 hardware multiplier
The performance of the PIC18 series is the highest in the Microchip 8-bit archi-
tecture. Figure 2.1 is a block diagram of the PIC18 architecture.

CPU Internal oscillator

16-bit instructions (up to 64 MHz)
83 instructions
12-bit file select registers
Interrupt context saving
Data EEPROM
Program Memory
(up to 2 MB)

16-level stack Data memory

Program counter (up to 4 KB)
Reset capability Enhanced indirect
addressing
Peripheral expansion
support

I/O and PERIPHERAL MODULES

ADC, CAN, EUSART, LCD, EEPROM, CCPWM, etc.

Figure 2.1 Block diagram of PIC18 architecture.

13
14 Chapter 2

Although the PIC16 series has been very successful in the microcontroller mar-
ketplace, it also suffers from limitations and constraints. Perhaps the most signifi-
cant limitation is that the devices of the PIC16 family can only be programmed in
Assembly language. Other limitations result from the device's RISC design. For ex-
ample, the absence of certain types of opcodes, such as the Branch instruction,
make it nec essary to combine a skip opcode followed by a goto op eration in order
to provide a con ditional, targeted jump. Other limitations relate to the hard ware it-
self: small stack and a single interrupt vector. As the complexity, memory size, and
the number of pe ripheral modules increased, the limitations of the PIC16 series
became more evident.

In the PIC18 series, Microchip reconsidered its PIC16 de sign rules and produced
a completely new style microcontroller, with a much more complex core, while lim-
iting the changes to the pe ripheral modules. The degree of change can be deduced
from the ex pansion of the instruction set from 35 14-bit to 83 16-bit operation codes.
Memory has gone from 14 to 128 KB; the stack from 8 levels to 32 levels. These
changes made it possible to optimize the PIC18 series for C language programming.

2.1.1 PIC18FXX2 Group

At the present time, Microchip lists 193 different devices in the PIC18 family. These de-
vices are available with pin counts from 28 to 100 and in the SOIC, DIP, PLCC, SPDIP,
QFN, SSOP, TQFP, QFN, and LQFP pack ages. For con sistency with the tutorial nature
of this book, we have selected the PIC18F4X2 group with identical DIP and SOIC
pinouts. Figure 2.2 shows the pin diagram for the PIC18F4X2 devices.

1 40
MCLR/VPP RB7/PGD
2 39
RAO/ANO RB6/PGC
3 38
RA1/AN1 RB5/PGM
4 37
RA2/AN2A/REF- RB4
5 36
RA3/AN3A/REF+ RB3/CCP2*
6 35
RA4/TOCKI RB2/INT2
7 34
RA5/AN4/SS/LVDIN RB1/INT1
8 33
RE0/RD/AN5 RBO/INTO
9
18F442 32
RE1/WR/AN6 Vdd
10 31
RE2/CS/AN7 Vss
11 30
Vdd 18F452 RD7/PSP7
12 29
Vss RD6/PSP6
13 28
OSC1/CLKI RD5/PSP5
14 27
OSC2/CLKO/RA6 RD4/PSP4
15 26
RCO/T1OSO/TICK1 RC7/RX/DT
16 25
RC1/T1OSI/CCP2 RC6/TX/CK
17 24
RC2/CCP1 RC5/SDO
18 23
RC3/SCK/SCL RC4/SDI/SDA
19 22
RDO/PSPO RD3/PSP3
20 21
RD1/PSP1 RD2/PSP2

40-PIN DIP FORMAT

Figure 2.2 Pin diagram for PIC18F4X2 devices.

PIC18 Architec ture 15

For learning and experimentation the devices in DIP packages are more conve-
nient because they can be easily inserted in the ZIF (zero insertion force) sockets
found in most programming devices, development boards, and bread boards. The de-
vices in Figure 1.1 and Figure 1.2 are so equipped. A PLCC (plastic leaded chip car-
rier) package with 44 pins is also available for 18F442 and 18F452 devices. We do
not cover this option.

2.1.2 PIC18FXX2 Device Group Overview

These devices come in 28-pin and 40-pin packages, as well as in a 44-pin PLCC package
previously mentioned. The 28-pin devices do not have a Parallel Slave Port (PSP).
Also, the number of analog-to-digital (A/D) converter input chan nels is reduced to 5.
An overview of features is shown in Table 2.1
Table 2.1
Principal Features of Devices in the PIC18FXX2 Family
FEATURES PIC18F242 PIC18F252 PIC18F442 PIC18F452

Operating Fre quency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz

Pro gram Mem ory
(Bytes) 16K 32K 16K 32K
Pro gram Mem ory
(In struc tions) 8192 16384 8192 16384
Data Mem ory
(Bytes) 768 1536 768 1536
Data EEPROM
Mem ory (Bytes) 256 256 256 256
In terrupt Sources 17 17 18 18
I/O Ports A, B, C A, B, C A, B, C, D, E A, B, C, D, E
Tim ers 4 4 4 4
Cap ture/Cornpare
/PWM Modules 2 2 2 2
Se rial Com mu ni ca tions
------------------------- MSSP ------------------------------------------
Ad dressable
USART
Paral lel Communications
- - PSP PSP
10-bit An a log-to-
Dig i tal Mod ule 5 channels 5 channels 8 channels 8 channels
RESETS (and Delays)
---------------------------- POR, BOR, Re set -------------------------------
In struc tion, Stack Full,
Stack Underflow,
(PWRT, OST)
Pro gram ma ble Low
Volt age De tect Yes Yes Yes Yes
Pro gram ma ble
Brown-out Reset Yes Yes Yes Yes
In struc tion Set 75 In struc tions 75 In struc tions 75 In struc tions 75 In struc tions
Packages 28-pin DIP 28-pin DIP 40-pin DIP 40-pin DIP QFP
28-pin SOIC 28-pin SOIC PLCC 44-pin PLCC 44-pin
SOIC SOIC SOIC SOIC
16 Chapter 2

From Table 2.1 the following general features of the PIC18FXX2 devices can be
deduced:
1. Operating frequency is 40 MHz for all devices. They all have a 75 opcode instruc-
tion set.
2. Program memory ranges from 16K (8,192 instructions) in the PIC18F2X2 devices
to 32K (16,384 instructions) in the PIC18F4X2 devices.
3. Data memory ranges for 768 to 1,536 bytes.
4. Data EEPROM is 256 bytes in all devices.
5. The PIC18F2X2 devices have three I/O poerts (A, B, and C) and the PIC18F4X2 de-
vices have five ports (A, B, C, D, and E).
6. All devices have four timers, two Capture/Compare/PWM modules, MSSP and
adressable USART for serial communications and 10-bit analog-to-digital mod-
ules.
7. Only PIC18F4X2 devices have a parallel port.

2.1.3 PIC18F4X2 Block Diagram

The block diagram of the 18F4X2 microcontrollers, which correspond to the 40-pin
devices of Figure 2.2, is shown in Figure 2.3.
Data memory
Program memory address
address

CPU
oscillators

ports
internal modules

Figure 2.3 PIC18F4X2 block diagram.

PIC18 Architec ture 17

2.1.4 Central Processing Unit

In Figure 2.3 the dashed rectangle labeled CPU (central processing unit) contains the
8-bit Arithmetic Logic Unit, the Working register la beled WREG, and the 8-bit-by-8-bit
hardware multiplier, described later in this chapter. The CPU receives the instruction
from program memory according to the value in the Instruction register and the action
in the Instruction Decode and Control block. An interrupt mechanism with several
sources (not shown in Figure 2.3) is also part of the PIC18FXX2 hardware.
The Status Register
The Sta tus register, not shown in Figure 2.3, is part of the CPU and holds the individual
status bits that reflect the op erating condition of the individual elements of the de vice.
Figure 2.4 shows the bit structure of the Status register.

bits: 7 6 5 4 3 2 1 0

- - - N OV Z DC C

bit 4 N: Negative bit

1 = Arithmetic result is negative
0 = Arithmetic result is positive
bit 3 OV: Overflow bit
1 = Overflow in signed arithmetic
0 = No overflow occurred
bit2 Z: Zero bit
1 = The result of an operation is zero
0 = The result of an operation is not zero
bit 1 DC: Digit carry/borrow bit for ADDWF, ADDLW, SUBLW,
and SUBWF instructions. For borrow the polarity
is reversed.
1 = A carry-out from the 4th bit of the result
0 = No carry-out from the 4th bit of the result
For rotate instructions (RRF and RLF) this bit
is loaded with either bit 4 or bit 3 of the
source register.
bit 0 C: Carry/borrow bit for ADDWF, ADDLW, SUBLW, and
SUBWF instructions. For borrow the polarity
is reversed.
1 = A carry-out from the most significant bit
0 = No carry-out from the most significant bit
For rotate instructions (RRF and RLF) this bit
is loaded with either bit 4 or bit 3 of the
source register.

Figure 2.4 Status register bitmap.

Program Counter Register

The 21-bit wide Program Counter register specifies the address of the next instruction
to be ex ecuted. The reg ister mapping of the Program Counter register is shown in Fig-
ure 2.5.
18 Chapter 2

Bits 20 15 7 0

PCU PCH PCL

Always 0

Figure 2.5 Register map of the Program Counter.

As shown in Figure 2.5, the low byte of the ad dress is stored in the PCL register,
which is readable and writeable. The high byte is stored in the PCH register. The up-
per byte is in the PCU register, which contains bits <20:16>. The PCH and PCU regis-
ters are not di rectly read able or writeable. Up dates to the PCH reg is ter are
performed through the PCLATH register. Updates to the PCU register are performed
through the PCLATU register.

The Program Counter addresses byte units in program memory. In order to pre -
vent the Pro gram Counter from becoming misaligned with word instructions, the
LSB of PCL is fixed to a value of '0' (see Figure 2.5). The Program Counter incre -
ments by 2 to the ad dress of the next se quen tial in struc tions in the program
memory.

The CALL, RCALL, GOTO, and program branch instructions write to the Program
Counter directly. In these instructions, the contents of PCLATH and PCLATU are not
transferred to the pro gram counter. The contents of PCLATH and PCLATU are trans-
ferred to the Pro gram Counter by an operation that writes PCL. Similarly, the upper
2 bytes of the Program Counter will be transferred to PCLATH and PCLATU by an
operation that reads PCL.

Hardware Multiplier
All PIC18FXX2 devices contain an 8 x 8 hardware multiplier in the CPU. Because mul-
tiplication is a hardware operation it completes in a single instruction cycle. Hard-
ware multiplica tion is unsigned and produces a 16-bit re sult that is stored in a 16-bit
product reg ister pair labeled PRODH (high byte) and PRODL (low byte).

Hardware multiplication has the following advantages:

• Higher computational performance
• Smaller code size of multiplication algorithms
The performance increase allows the device to be used in applications previously re-
served for Digital Signal Processors.

Interrupts
PIC18FXX2 devices support multiple interrupt sources and an interrupt priority
mechanism that allows each interrupt source to be as signed a high or low priority
level. The high-prior ity interrupt vector is at OOOOO8H and the low-priority interrupt
vector is at 000018H. High-priority interrupts override any low-priority interrupts that
may be in progress. Ten registers are related to interrupt operation:
PIC18 Architec ture 19

• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2

Each interrupt source (except INTO) has three control bits:

• A Flag bit indicates that an interrupt event has occurred.
• An Enable bit allows program execution to branch to the interrupt vector address
when the flag bit is set.
• A Priority bit to select high-priority or low priority for an interrupt source.

Interrupt priority is enabled by setting the IPEN bit {mapped to the RCON<7>
bit}. When interrupt priority is enabled, there are 2 bits that enable interrupts glob-
ally. Setting the GIEH bit (1NTCON<7>) enables all interrupts that have the priority
bit set. Setting the GIEL bit (INTCON<6>) enables all interrupts that have the prior-
ity bit cleared. When the interrupt flag, the en able bit, and the ap propriate global in-
ter rupt en able bit are set, the in ter rupt will vec tor to ad dress OOOOO8h or
000018H, de pending on the priority level. Individual in ter rupts can be dis abled
through their corresponding enable bits.

When the IPEN bit is cleared (default state), the interrupt priority feature is dis-
abled and the interrupt mechanism is compatible with PIC mid-range devices. In
this compatibility mode, the interrupt priority bits for each source have no effect
and all interrupts branch to address OOOOO8H.

When an interrupt is handled, the Global Interrupt Enable bit is cleared to disable
further interrupts. The return address is pushed onto the stack and the Pro gram
Counter is loaded with the interrupt vec tor address, which can be OOOOO8H or
000018H. In the Interrupt Service Routine, the source or sources of the interrupt can
be de termined by testing the interrupt flag bits. To avoid recursive interrupts, these
bits must be cleared in software be fore re-enabling interrupts. The “return from in-
terrupt“ instruction, RETFIE, exits the interrupt routine and sets the GIE bit {GIEH
or GIEL if priority levels are used), which re-enables interrupts.

Sev eral ex ter nal in ter rupts are also sup ported, such as the INT pins or the
PORTB input change interrupt. In these cases, the interrupt latency will be three to
four instruction cycles. Interrupts and interrupt programming are the subject of
Chapter 8.

2.1.5 Special CPU Features

Sev eral CPU features are intended for the following purposes:
20 Chapter 2

• Mmaximize system reliability

• Minimize cost through the elimination of external components
• Provide power-saving operating modes
• Offer code protection

These special features are re lated to the fol lowing functions and components:

• SLEEP mode
• Code protection
• ID locations
• In-circuit serial programming
• SLEEP mode

SLEEP mode is designed to offer a very low current mode during which the de-
vice is in a power-down state. The ap plica tion can wakeup from SLEEP through the
following mechanisms:

1. External RESET
2. Watchdog Timer Wake-up
3. An interrupt

The Watch dog Timer is a free running on-chip RC oscillator, that does not re quire
any external components. This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the
OSC1/CLKI and OSC2/CLKO/ RA6 pins of the device has been stopped, for example,
by ex ecution of a SLEEP instruction.

Watchdog Timer
A Watchdog Timer time-out (WDT) generates a device RESET. If the device is in
SLEEP mode, a WDT causes the de vice to wakeup and continue in normal operation
(Watchdog Timer Wake-up). If the WDT is enabled, software ex ecution may not dis-
able this function. When the WDTEN configuration bit is cleared, the SWDTEN bit en-
ables/disables the operation of the WDT. Values for the WDT postscaler may be
assigned using the configuration bits.

The CLRWDT and SLEEP instructions clear the WDT and the postscaler (if as-
signed to the WDT) and prevent it from timing out and generating a device RESET
condition. When a CLRWDT instruction is executed and the postscaler is assigned
to the WDT, the postscaler count will be cleared, but the postscaler assignment is
not changed.

The WDT has a postscaler field that can extend the WDT Reset pe riod. The
postscaler is selected by the value written to 3 bits in the CONFIG2H register during
device programming.
PIC18 Architec ture 21

Wake-Up by Interrupt

When global interrupts are disabled (the GIE bit cleared) and any interrupt source has
both its interrupt enable bit and interrupt flag bit set, then one of the following will oc-
cur:

When an interrupt occurs before the ex ecution of a SLEEP instruction, then the
SLEEP instruction becomes a NOP. In this case, the WDT and WDT postscaler will
not be cleared, the TO bit will not be set, and PD bits will not be cleared.

If the interrupt condition occurs during or after the ex ecution of a SLEEP instruc-
tion, then the de vice will immediately wakeup from SLEEP. In this case, the SLEEP
instruction will be completely executed be fore the wake-up. Therefore, the WDT
and WDT postscaler will be cleared, the TO bit will be set, and the PD bit will be
cleared.

Even if the flag bits were checked before executing a SLEEP instruction, it may
be possible for these bits to set be fore the SLEEP instruction completes. Code can
test the PD bit in order to de termine whether a SLEEP instruction executed. If the
PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT
is cleared, a CLRWDT instruction should be executed be fore a SLEEP instruction.

Low Voltage Detection

For many applications it is desirable to be able to detect a drop in device voltage below
a certain limit. In this case, the application can define a low voltage window in which it
can per form housekeep ing tasks before the volt age drops be low its defined operating
range. The Low Voltage Detect feature of the PIC18FXX2 devices can be used for this
purpose. For example, a voltage trip point for the de vice can be spec ified so that when
this point is reached, an interrupt flag is set. The program will then branch to the inter-
rupt's vector address and the interrupt handler software can take the cor responding
action. Because the Low Voltage Detect circuitry is completely under software con-
trol, it can be “turned off” at any time, thus saving power.

Implementing Low Voltage Detect requires setting up a comparator that reads the
reference voltage and compares it against the preset trip-point. This trip-point volt-
age is software programmable to any one of sixteen values by means of the 4 bits la-
beled LVDL3:LVDLO. When the device voltage becomes lower than the preselected
trip-point, the LVDIF bit is set and an interrupt is generated.

Device Configuration

Several device configurations can be selected by programming the configuration bits.

These bits are mapped, starting at program memory address 300000H. Note that this
address is located in the configuration memory space (300000H to 3F0000H), which is
only accessed using table read and ta ble write operations. When the configuration bits
are programmed, they will read as '0; when left unprogrammed they will read as '1'.
22 Chapter 2

MPLAB development tools provide an __CONFIG directive, together with a set of

device-specific operands, that simplify selecting and setting the desired configura-
tion bits. This topic is explored in the book's chapters related to programming.

2.2 Memory Organization

Devices of the PIC18FXX2 family contain three independent memory blocks:
• Program Memory
• Data Memory
• Data EEPROM
Because the device uses a separate buss, the CPU can concurrently access the
data and pro gram memory blocks.

2.2.1 Program Memory

The Program Counter register is 21 bit wide and therefore capable of addressing a
maximum of 2-Mbyte program memory space. Accessing a location between the phys-
ically implemented memory and the 2-Mbyte maximum address will read all zeroes.
The PIC18F242 and PIC18F442 devices can store up to 8K of single-word instructions.
The PIC18F252 and PIC18F452 devices can store up to 16K of single-word instruc-
tions. The RESET vector address is at OOOOH and the interrupt vector addresses are
at 0008H and 0018H. Figure 2.6 shows the memory map for the PIC18FXX2 family.

PC bits <20:0> PC bits <20:0>

Stack Level 1 Stack Level 1

. .
. .
. .
. .

Stack Level 31 Stack Level 31

RESET Vector 0000H RESET Vector 0000H

High Priority Interrupt Vector 0008H High Priority Interrupt Vector 0008H

Low Priority Interrupt Vector 0018H Low Priority Interrupt Vector 0018H

On-Chip On-Chip
Program Memory Program Memory

3FFFH
4000H

7FFFH
8000H
Read '0'

Read '0'

1FFFFFH 1FFFFFH
200000H 200000H

PIC18F442/242 PIC18F452/252
Figure 2.6 Program memory map for the PIC18FXX2 family.
Discovering Diverse Content Through
Random Scribd Documents
 MALURUS ELEGANS, Gould.
Graceful Wren.

Malurus elegans, Gould, Birds of Australia, Part I. Aug. 1837.

Djur-jeel-ya, Aborigines of the lowland districts of Western
Australia.

This is not only the largest species of the genus yet discovered, but
may be considered as one of the most beautiful and elegant of its
race: the delicate verditer-blue of the centre of the back, and the
larger size and more spatulate form of its tail-feathers, at once
distinguish it from Malurus Lamberti, the species to which it is most
nearly allied. It is an inhabitant of the western coast of Australia; all
the specimens I possess were collected at Swan River, where it is
tolerably abundant. Mr. Gilbert states, that although in its economy
it very closely resembles M. splendens, it nevertheless differs from
that species in the nature of the localities it frequents, which are
usually swampy situations, while M. splendens is more generally
spread over all parts of the country. It is also said to differ slightly in
its song, in commencing with one distinct note and then singing
precisely like the former.
The nest, which is neither characterized by neatness nor
compactness, is dome-shaped, with a hole in the side for an entrance,
and is generally formed of the thin paper-like bark of the Tea-tree
(Melaleuca), and lined with feathers: it is also usually suspended to
the foliage of this tree, and occasionally to that of other shrubs which
grow in its favourite localities. The eggs are four in number, of a
delicate flesh-white freckled with spots of reddish brown, which are
much thicker at the larger end; they are about eight lines long and six
lines broad. The breeding-season commences in September and
continues during the three following months.
The food consists of insects.
The males are subject to the same law relative to the seasonal
change of plumage as the Malurus cyaneus, and the other members
of the group.
The male has the forehead, ear-coverts, sides of the face and
occiput rich verditer-blue; centre of the back light verditer-blue;
scapularies chestnut; throat, chest, back of the neck and rump deep
velvety black, the throat in certain lights tinged with blue; wings
brown; abdomen and under tail-coverts huffy white; tail dull bluish
green, crossed by numerous indistinct bars, seen only in some
positions, and very slightly tipped with white; bill black; eyes and
feet blackish brown.
The female has all the upper surface and wings brown; throat and
under surface buff-white; tail as in the male, but more dull, and
devoid of the white at the extremity of the feathers; bill dull reddish
brown, lighter beneath; space between the bill and eyes reddish
brown; legs brown.
The figures are of the natural size, on the Isopogon alternatus.
 MALURUS
PULCHERRIMUS:
Gould.

J. Gould
and H. C.
Richter del
et lith.
Hullmandel
& Walton
Imp.
 MALURUS PULCHERRIMUS, Gould.
Beautiful Wren.

Malurus pulcherrimus, Gould in Proc. of Zool. Soc., Part XII. p.

106.

A more beautiful bird than the present species, which must be

regarded as the representative in Western Australia of the Malurus
Lamberti, can scarcely be imagined. It is moreover an evidence that
this hitherto unexplored portion of the country is not less rich in
interesting productions than are those parts which have been much
longer known to us.
The Malurus pulcherrimus is very nearly allied to the M.
Lamberti, but is of a larger size, and also differs from that species in
having the throat and breast of a rich deep blue instead of black.
For a knowledge of this species I am indebted to the researches of
Mr. Gilbert, who informs me that “it appears to be exclusively
confined to the thickets of the interior of Western Australia; in habits
and manners it greatly resembles the other members of the genus,
but its nest is somewhat smaller than that of either of them. A nest
found on the 28th of October, in the vicinity of the Wongan Hills,
was placed on the upper branches of a species of Hakea about four
feet from the ground; it contained two newly-laid eggs, which
resembled those of the other species of the genus, but had the
blotches very much larger.”
Crown of the head and a broad band across the centre of the back
rich glossy violet-blue; space surrounding the eye and the ear-coverts
verditer-blue; throat intense indigo-blue, bounded below by an
indistinct band of black; lores, collar surrounding the back of the
neck, and the lower part of the back, deep velvety black; scapularies
chestnut; wings brown; tail dull greenish blue, indistinctly barred
with a darker tint and slightly tipped with white; abdomen and under
tail-coverts white; bill and feet black; irides dark brown.
The figures represent two males and a female of the natural size.
MALURUS LAMBERTI:
Vig. & Horsf.

J. & E.
Gould delt.
C.
Hullmandel
Imp.
 MALURUS LAMBERTI, Vig. & Horsf.
Lambert’s Wren.

Malurus Lamberti, Vig. & Horsf. in Linn. Trans., vol. xv. p. 221.—
Jard. and Selb., Ill. Orn., vol. ii. pl. 72. fig. 2.—Gould, Syn.
Birds of Australia, Part I.
Superb Warbler, White’s Journ., pl. in p. 256, low. fig.—Phillips,
Voy., pl. in p. 157, male.
Variegated Warbler, Lewin, Birds of New Holl., pl. xv.

Although far less common and much more local than M. cyaneus,
this species ranges over a greater extent of country, being an
inhabitant of most parts of New South Wales, the interior in the
neighbourhood of the Namoi and the north-west coast, whence I
received several specimens, forming part of an interesting collection
kindly sent me by Mr. Dring. I found it tolerably abundant on the
Namoi, where it was sometimes associated with its congener M.
cyaneus.
In New South Wales the neighbourhood of Botany Bay is one of its
most favourite resorts, and it is occasionally seen near Sydney, and
even in the small gardens within the town. A beautiful specimen in
the Museum of this place was killed on the lawn in front of that
establishment, which is situated within the precincts of the town,
and surrounded on all sides by houses. It does not inhabit Van
Diemen’s Land, nor did I observe it in South Australia, or hear of its
ever having been seen there, neither have I received it from the
colony of Swan River.
Lambert’s Superb Warbler is a species with which we have been
long acquainted, being figured in the early voyages to New South
Wales as a variety of Malurus cyaneus; but the only species with
which it at all assimilates in the disposition and colour of its
markings is the M. elegans of Western Australia, of which it forms a
beautiful analogue on the eastern coast.
This is one of the few common birds of Australia of which I was
not able to find the nest; but its changes of plumage, nidification, the
number and colour of its eggs, are doubtless very similar to those of
the other members of its family. Its food consists of insects of various
kinds, which are sought for on the ground, over which it runs with
great facility.
The male has the forehead, ear-coverts, sides of the head and
occiput and centre of the back beautiful violet-blue; throat, breast,
crescent across the upper part of the back and rump black;
scapularies chestnut; wings brown; abdomen white, tinged with
brown on the flanks; tail dull greenish blue, indistinctly barred with a
darker tint, and lightly tipped with white; bill black; eyes and feet
dark brown.
The female has the body dull brown; the throat and under surface
much paler; tail-feathers as in the male, but less bright; bill and
space round the eye reddish brown; feet brown.
The Plate represents a male and female of the natural size.
 MALURUS
LEUCOPTERUS: Quoy
& Gaim.

J. & E.
Gould delt.
C.
Hullmandel
Imp.
 MALURUS LEUCOPTERUS, Quoy & Gaim.?
White-winged Wren.

Malurus leucopterus, Quoy et Gaim. Zool. de l’Uranie, p. 108. pl.

23. fig. 2.?—Vig. & Horsf. in Linn. Trans., vol. xv. p. 222.
Amytis leucopterus, Less. Traité d’Orn., p. 454.

I regret that I have not been able to clear up the doubt which exists
in my mind, whether the present beautiful bird is or is not distinct
from the one figured by Messrs. Quoy and Gaimard in the “Voyage
de l’Uranie,” since on applying at the Museum of the Jardin des
Plantes, for the purpose of examining the original specimen, it could
not be found: the figure above-quoted, if intended for the present
bird, is by no means correct, and it is, moreover, said to be from Dirk
Hatich’s Island, on the western coast, a locality very distant from
those in which I found the bird here represented; a circumstance
which strengthens my belief that they may be distinct: besides which,
the bird I have figured is supposed to be exclusively an inhabitant of
the interior; I never even observed it between the mountain ranges
and the coast; it is therefore scarcely probable that it should inhabit
an island like that of Dirk Hatich.
It was tolerably abundant in the patches of low scrub and grassy
beds, here and there scattered over the plains which stretch out to
the northward of the Liverpool range, and it was equally plentiful on
the Lower Namoi: that it extends as far as South Australia, is proved
by my having received its nest and eggs from that part of the
continent.
It was usually seen either in pairs or in small troops, and evinced
so much shyness of disposition as to render the acquisition of
specimens a task of no little difficulty, particularly of the full-
plumaged male, who appeared to be conscious that the display of his
gorgeously-coloured dress might lead to his detection. Its powers of
flight are not great, but this is fully compensated for by the
extraordinary manner in which it threads the bushes, and passes
over the surface of the ground in a series of hopping bounds,
whereby it readily eludes pursuit. The most successful mode of
obtaining it is to ascertain the precise spot in which it is located, to
approach it cautiously, and to remain silent for a short time, when
the male will soon show himself by hopping out from the bush; the
restless nature of his disposition not admitting of his remaining long
concealed.
The beautifully contrasted colours of blue and white, represented
in our Plate, is a merely seasonal dress assumed in spring, and
continued throughout the breeding-season, which commences in
August and terminates in January; before and after this season male
birds may be seen in every stage of colouring, from plain uniform
brown to that of the perfect livery.
The nest is composed of grasses, rather large and dome-shaped,
with a hole near the top for an entrance. The one sent me from South
Australia contained two eggs, one of which was the Bronze Cuckoo’s,
thus showing that this little bird is also the foster-parent of those
birds. The number of eggs laid by the Malurus leucopterus is in all
probability four; the one I possess is flesh-white, finely freckled with
reddish brown, forming a zone at the larger end, and is eight lines
long by six lines broad.
The male has the whole of the head, body above and beneath, and
the tail beautiful deep blue; scapularies, wing-coverts and tertiaries
snow-white; primaries brown, with their external edges silvery
green; bill black; feet brown; eyes dark brown.
The female has the crown of the head, and all the upper surface
and flanks brown; throat and abdomen white, faintly washed with
brown; external edges of the primaries and tail pale greenish blue;
bill reddish brown.
The Plate represents the male and female of the natural size; the
Plant is the Brunonia Australis.
 MALURUS
MELANOCEPHALUS:
Vig. & Horsf.

J. & E.
Gould delt.
C.
Hullmandel
Imp.
 MALURUS MELANOCEPHALUS, Vig. &
Horsf.
Black-headed Wren.

Scarlet-lacked Warbler, Lewin, Birds of New Holl., pl. xiv.

Malurus melanocephalus, Vig. & Horsf. in Linn. Trans., vol. xv.
p. 222.
Malurus Brownii, Jard. and Selb. Ill. Orn., vol. ii. pl. 72. fig. 1.

In their “Illustrations of Ornithology,” Sir William Jardine and Mr.

Selby have in a very laudable manner endeavoured to clear up what
they considered some confusion respecting the present and the
preceding species, M. Brownii. These gentlemen have, however,
fallen into error in considering the two birds as identical, whereas
they are, in fact, totally distinct.
I have never seen the Black-headed Wren from any other locality
than New South Wales, and I am consequently led to believe that the
south-eastern portion of Australia is its peculiar and limited habitat.
It is a local species, not being generally diffused over the face of the
country, like several other members of the group, but confined to
grassy ravines and gullies, particularly those that lead down from the
mountain ranges. I obtained several pairs of adult birds in very fine
plumage in the valleys under the Liverpool range, all of which I
discovered among the high grasses which there abound; but as the
period of my visit was that of their breeding-season, I never observed
more than a pair together, each pair being always stationed at some
distance from the other, and in such parts of the gullies as were
studded with small clumps of scrubby trees.
 The Black-headed Wren has many actions in common with the M.
cyaneus, and like that species carries its tail erect: it also frequently
perches on a stem of the most prominent grasses, where it displays
its richly-coloured back, and pours forth its simple song. I did not
succeed in finding the nest, although I knew they were breeding
around me: it was probably placed among the grasses, but was so
artfully concealed that it completely baffled my efforts at finding it.
One might suppose the greater development of feather on the back
of this species to have been given it as a defence against the damp
and dense grasses of the ravines, among which it usually resides; but
from the circumstance of the female not possessing this character of
plumage, and the rich garb being only seasonal in the male, this
supposition falls to the ground. In their winter dress the sexes very
nearly resemble each other; but the males may always be
distinguished by the black colouring of the bill and tail-feathers. The
young male of the year has the tail-feathers brown, like the females,
and it is a curious fact, that at this age these feathers are much longer
than in the adult.
The flight of this species is feeble and not protracted; but, on the
contrary, its powers of running and creeping are very considerable.
The breeding-season probably commences in September and
continues until January; its food is insects of various kinds.
The male has the head, all the under surface, wing-coverts, upper
tail-coverts and tail deep velvety black; back of the neck, scapularies
and remainder of the upper surface rich orange-scarlet; bill black;
eyes blackish brown; feet fleshy brown.
Female brown above, paler beneath; bill brown; base of the under
mandible reddish brown; feet flesh-brown.
The Plate represents male and female in the summer plumage, and
a young male in change, on one of the native grasses of New South
Wales.
MALURUS BROWNII:
Vig. & Horsf.

J. & E.
Gould delt.
C.
Hullmandel
Imp.
 MALURUS BROWNII, Vig. & Horsf.
Brown’s Wren.

Malurus Brownii, Vig. & Horsf. in Linn. Trans., vol. xv. p. 223.
Malurus cruentatus, Gould in Proc. of Zool. Soc., Part VII. p. 143.

Among the species of which I sent home characters from New

South Wales, for publication in the Proceedings of the Zoological
Society, was the present pretty bird, to which I gave the specific
name of cruentatus; upon comparison, however, of my specimens
with the Malurus Brownii in the Linnean Society’s Collection, I find
they are identical, consequently my name must sink into a synonym.
Mr. Brown, who was the donor of the Linnean Society’s specimen,
obtained his bird near Broad Sound, on the eastern coast; while
those from which my description was taken were procured on the
north-west, and formed part of the collection placed at my disposal
by the officers of the Beagle. It differs from Malurus melanocephalus
in the more intense and deep blood-red of the back, and, as Messrs.
Vigors and Horsfield justly observe, it is much less in size.
Of its habits and economy, or the situations to which it gives
preference, no information has yet been obtained; but we may
reasonably suppose, that two species so nearly resembling each other
in structure and colour as M. Brownii and M. melanocephalus do
not greatly differ in their habits.
I have lately received an account of its being common at Port
Essington; and, as I have above stated, it is an inhabitant of the
eastern and north-western coasts; we may consequently conclude
that its range extends over the whole of the northern parts of the
Australian continent.
 The male in summer has the head, neck, wings, all the under
surface and tail black; primaries and secondaries brown; back and
shoulders fine crimson; bill black; legs fleshy brown.
The female is uniform light brown, the abdomen inclining to
white; bill and feet light brown.
The Plate represents a male and female, on the Bæckia linifolia.
 AMYTIS TEXTILIS:
Lefs:

J. & E.
Gould delt.
C.
Hullmandel
Imp.
 AMYTIS TEXTILIS.
Textile Wren.

Malurus textilis, Quoy et Gaim. Zool de l’Uranie, p. 107. pl. 23.

fig. 1.

The birds figured in this and the following Plate differ from each
other considerably in plumage, as well as in the structure of the bill,
that organ in the present bird being shorter and more robust than in
Amytis striatus.
Of the Textile Wren I killed and dissected many examples, but of
the following I only procured a single specimen, and never met with
it but in this one instance. I have considered it necessary to state this,
as it would have been more satisfactory to me to have had further
proofs from actual dissection and comparison, of their being really
distinct, although I have little doubt that such is the case. The bird
figured in the “Voyage de l’Uranie,” is doubtless referable to the one
represented on the opposite Plate, while that figured by M. Lesson in
the Atlas to his “Traité d’Ornithologie,” and which seems to have
been the subject from which he took his generic characters and
description, as clearly belongs to A. striatus.
The only place in which I observed the Textile Wren was the plains
bordering the Lower Namoi; and that its range extends far to the
northward and westward is certain, from the fact of the specimen
figured in the “Voyage” above-quoted having been procured on the
north-west coast.
In the various positions it assumes, in the elevated carriage of its
tail, and in its whole economy, it bears a close resemblance to the
true Maluri: like them also it wanders about in small troops of four
or six in number, always keeping within a short distance, and
returning towards the close of the day to its accustomed haunts. On
the Lower Namoi, where it is very abundant, it is found in all those
parts of the plains that are studded with scrubs and clumps of a low
shrub-like tree, resembling the Barilla of the coast, through and
among which it creeps with astonishing rapidity; indeed, its mode of
progression on the ground is such as no description can convey an
accurate conception of, and must be seen to be understood: I cannot
perhaps compare it with anything, unless with the motion of an
India-rubber ball when thrown forcibly along the ground. While
stealing from bush to bush, with this rapid movement, its head low
and tail perfectly erect, it presents an exceedingly droll appearance.
Like many others of its family, it seldom employs the power of flight.
Its food is insects of various kinds.
Of its nidification I have nothing to communicate: it doubtless
builds a dome-shaped nest, and in all probability lays four spotted
eggs; but to these points I would call the attention of those who are
favourably situated for observing them, as also to confirm or refute
the opinion of this and the following bird being distinct.
All the upper surface dark brown, each feather with a narrow
stripe of white down the centre; under surface the same, but much
paler; flanks and under surface of the shoulder rust-red; tail dark
brown, indistinctly barred with a still darker hue and edged with pale
brown; irides reddish hazel; base of lower mandible bluish horn-
colour; remainder of the bill black; feet flesh-brown.
The male I dissected was destitute of the rusty red colouring on the
flanks and under surface of the shoulder.
The Plate represents a male and female of the natural size.
 AMYTIS STRIATUS:
Gould.

J. & E.
Gould delt.
C.
Hullmandel
Imp.
 AMYTIS STRIATUS.
Striated Wren.

Amytis textilis, Less. Traité d’Orn., p. 454. pl. 67. fig. 2.

Dasyornis striatus, Gould in Proc. of Zool. Soc., Part VII. p. 143.

The only specimen I procured of this little bird in a recent state,

was shot while I was traversing the Lower Namoi; it appeared to give
preference to a loose sandy soil studded with high rank grass, which,
growing in tufts, left the interspaces quite bare: through the natural
labyrinth thus formed the Striated Wren ran with amazing rapidity,
and it was only by forcing it to take wing that I succeeded in killing
the one I obtained, which on dissection proved to be a male, and
which served for the upper figure in my Plate: the other figure is
supposed to represent the female; but as this can only be ascertained
by the internal examination of a recent specimen, and no
opportunity for so doing has yet occurred, this point must, for the
present, remain undecided. All the specimens I have seen from New
South Wales were in the red state of plumage, which goes far towards
proving that this bird is really distinct from Amytis textilis.
Nothing has yet been ascertained respecting its nidification: its
food, like that of the Textile Wren, consists of insects of various
kinds.
Upper surface fine rusty red, each feather with a line of buffy white
bounded on each side by black down the centre; line beneath the eye
black; ear-coverts black, striated with white; wings and tail brown,
margined with light reddish brown; base of the primaries rust-red,
forming a conspicuous patch; chin and throat white; feathers of the
chest buffy white, with two lines of brown, one down each side the
stem; under surface rust-red, some of the feathers with a stripe of
white down the centre; tail dark brown, indistinctly barred with a
still darker tint, margined with lighter brown; irides hazel; bill dark
horn-colour; feet brownish lead-colour.
The Plate represents a male and female of the natural size.
AMYTIS MACROURUS:
Gould.

J. Gould
and H. C.
Richter del
et lith.
Hullmandel
& Walton
Imp.
 AMYTIS MACROURUS, Gould.
Large-tailed Wren.

Amytis macrourus, Gould in Proc. of Zool. Soc., Jan. 27, 1847.

Nyern-de and Jee-ra, Aborigines of the interior of Western
Australia.

The present is the first species of the genus that has been
discovered in Western Australia; the two examples in my own
collection are all that I have yet seen; these were shot in the interior
by Mr. Gilbert, who states that “it inhabits the thickets, and is almost
always on the ground in families of from four to seven in number: it
carries its tail more erect than any other bird I have seen, and
certainly no bird runs or rather hops over the surface of the ground
with greater rapidity.”
It is evidently the representative of the Amytis textilis of the
eastern coast, to which it is very nearly allied, but from which, as well
as from the A. striatus, it may at once be distinguished by its more
robust form, and by the much greater length and size of its tail.
All the upper surface brown, each feather with a narrow stripe of
white down the centre; under surface the same, but much paler;
under surface of the shoulder pale rusty red; tail brown, margined
with pale brown; irides hazel; base of the lower mandible horn-
colour, remainder of the bill black; feet flesh-brown.
The figures are of the natural size.
 STIPITURUS
MALACHURUS: Lefs.

J. & E.
Gould delt.
C.
Hullmandel
Imp.
 STIPITURUS MALACHURUS, Less.
Emu Wren.

Muscicapa malachura, Lath. Ind. Orn. Supp., pl. lii.—Shaw, Gen.

Zool., vol. x. p. 407.
Soft-tailed Flycatcher, Linn. Trans., vol. iv. p. 242. pl. 21.—Lath.
Gen. Syn. Supp., vol. ii. p. 224.
Malurus malachurus, Vig. & Horsf. in Linn. Trans., vol. xv. p.
224.
Stipiturus malachurus, Less. Traité d’Orn., p. 415.
Soft-tailed Warbler, Lath. Gen. Hist., vol. vii. p. 123.
Waw-gul-jelly, Aborigines of New South Wales.
Djur-jeel-ya, Aborigines of the lowlands of Western Australia.

This curious little bird has a wide distribution; since it inhabits the
whole of the southern portion of Australia, from Moreton Bay on the
east to Swan River on the west, including Tasmania. Among the
places where it is most numerous in the latter country, are the
swampy grounds in the neighbourhood of Recherche Bay in
D’Entrecasteaux Channel, the meadows at New Norfolk, Circular
Head, and Flinder’s Island in Bass’s Straits; on the continent of
Australia, Botany Bay, and indeed all portions of the country having
a similar character are favoured with its presence.
In its actions it bears a close resemblance to the true Maluri,
among which it has been associated, but, as the nature of its plumage
would lead us to expect, it resorts to situations of a totally different
character; for while the more open forest is the favourite resort of the
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