UNIT – 4 : INTERFACING WITH I/O DEVICES

Introduction:
Any application of Microprocessor Based system requires the transfer of data
between external circuitry to the Microprocessor and Microprocessor to the
External circuitry. User can give information (i.e., input) to the Microprocessor
using keyboard and user can see the result or output information from the
Microprocessor with the help of display.
Hence, Interfacing is used to exchange information between two different
applications/devices.
Interface is the path for communication between two components.
Interfacing is of two types –
Memory interfacing and I/O interfacing.

Memory Interfacing:
When we are executing any instruction, we need the microprocessor to access the
memory for reading instruction codes and the data stored in the memory. For this,
both the memory and the microprocessor require some signals to read from and
write to registers. The interfacing process includes some key factors to match with
the memory requirements and microprocessor signals. The interfacing circuit
therefore should be designed in such a way that it matches the memory signal
requirements with the signals of the microprocessor.

IO Interfacing:
There are various communication devices like the keyboard, mouse, printer, etc.
So, we need to interface the keyboard and other devices with the microprocessor
by using latches and buffers. This type of interfacing is known as I/O interfacing.
Block Diagram of Memory and I/O Interfacing:

8085 Interfacing Pins:

Following is the list of 8085 pins used for interfacing with other devices –
 A15 - A8 (Higher Address Bus)
 AD7 - AD0(Lower Address/Data Bus)
 ALE
 RD
 WR
 READY

Ways of Communication − Microprocessor with the Outside World?

There are two ways of communication in which the microprocessor can connect
with the outside world -
1. Serial Communication Interface − In this type of communication, the
interface gets a single byte of data from the microprocessor and sends it bit by bit
to the other system serially and vice-a-versa.
2. Parallel Communication Interface − In this type of communication, the
interface gets a byte of data from the microprocessor and sends it bit by bit to the
other systems in simultaneous (or) parallel fashion and vice-a-versa.
Ports: Data transfer is done with the help of I/O ports.
Input Port:
It is used to read data from the input device such as keyboard. The simplest form
of input port is a buffer. The input device is connected to the microprocessor
through buffer as shown in the Fig. 4.28. This buffer is a tri-state buffer and its
output is available only when enable signal is active.
When microprocessor wants to read data from the input device (keyboard), the
control signals from the microprocessor activates the buffer by asserting enable
input of the buffer. Once the buffer is enabled, data from the input device is
available on the data bus. Microprocessor reads this data by initiating read
command.

Output Port:
It is used to send data to the output device such as display from the
microprocessor. The simplest form of output port is a latch. The output device is
connected to the microprocessor through latch as shown in the Fig. 4.29.
When microprocessor wants to send data to the output device, it puts the data on
the data bus and activates the clock signal of the latch, latching the data from the
data bus at the output of latch. It is then available at the output of latch for the
output device.

Interfacing of I/O Devices:

 I/O ports are the communication channel of the microprocessor with the
external devices.
 Input port - read data from keyboard, mouse etc.
 Output port - send data to output devices (CRT display)

Steps in Interfacing an I/O device:

→ Connect the data bus of the microprocessor to the data bus of the I/0 port
→ Derive a device address pulse by decoding the required address of the device
and use it as chip select.
→ Use a suitable control signal i.e. -
Connect IORD to RD input of the device. Or
Connect IOWR to WR input of the device.

Methods of Interfacing I/O devices:

1. Memory-mapped I/O
2. I/O-mapped I/O (Isolated I/O mapping)

1. Memory-mapped I/O: In memory-mapped I/O, the I/O devices are mapped

to specific memory addresses. This means that the microprocessor can access I/O
devices using the same instructions that it uses to access memory.

2. I/O mapped I/O: In I/O mapped I/O, the I/O devices are accessed using
separate I/O ports. This means that the microprocessor needs to use special
instructions to access I/O devices.
Basis for Memory mapped I/O I/O mapped I/O
Comparison
Basic I/O devices are treated as I/O devices are treated as
memory. I/O devices.
Allotted address 16-bit (A0 – A15) 8-bit (A0 – A7)
size
Data transfer Same for memory and I/O Different for memory and
instructions devices. I/O devices.
Cycles involved Memory read and memory I/O read and I/O write
write
Interfacing of Large (around 64K) Comparatively small
I/O ports (around 256)
Control signal No separate control signal is Special control signals are
needed for I/O devices. used for I/O devices.
Efficiency Less Comparatively more
Decoder More decoder hardware Less decoder hardware
hardware required. required.
IO/M’ During memory read or During I/O read and I/O
memory write operations, write operation, IO/M’ is
IO/M’ is kept low. kept high.
Data movement Between registers and ports. Between accumulator and
ports.
Logical Simple Complex
approach
Usability In small systems where In systems that need large
memory requirement is less. memory space.
Speed of Slow Comparatively fast
operation
Example of LDA ****H IN ****H
instruction STA ****H OUT ****H
MOV A, M
Interrupts in 8085:
Whenever more than one I/O device is connected to a microprocessor-based
system, any one of the I/O devices may ask for service at any time. There are two
methods by which the microprocessor can service these I/O devices –
1. Polling Routine and 2. Interrupts
1. Polling Routine:
The Polling routine is a simple program that keeps a check on the occurrences of
interrupts.
The polling routine will first transfer the status of the I/O port to the accumulator
and then checks the content of the accumulator to determine if the service request
bit is set.
If the bit is set then the I/O port service routine is called.
2. Interrupts:
An interrupt is an external asynchronous input that informs the microprocessor to
complete the instruction that is currently executing and fetch a new routine in
order to offer service to the I/O device.
Once the I/O device is serviced, the microprocessor will continue with the
execution of its normal program.

Basic Definitions of Interrupts:

1. Interrupts: It is a mechanism by which an I/O device (hardware interrupts) or
an instruction (software interrupts) can suspend the normal execution of the
processor and get itself serviced.
2. Interrupt Service routine (ISR): A small program or a routine that when
executed services the corresponding interrupting source is called an ISR.
3. Vectored/Non-vectored Interrupts: If the ISR address of an interrupt is to be
taken from the interrupting source itself, it is called a non-vectored interrupt, else
it is a vectored interrupt.
4. Maskable/Non-maskable Interrupt: In cases where an interrupt is masked,
the microprocessor will not respond to the interrupt even is the interrupt is
activated. The interrupt which can be masked under the software control is called
as maskable Interrupt. The interrupts which cannot be masked under the software
control are called non-maskable interrupts.
Types of Interrupts in 8085
There are two types of interrupts in the 8085 microprocessor. They are:
1. Hardware Interrupts:
 The peripheral device activates the interrupt by activating the respective
pin.
 In response to the interrupting request, the microprocessor completes the
current instruction execution in the main program and transfers program
control to the interrupt service routine.
 In the ISR routine, the task is completed. The task may be to read data, write
data, upload the status, update the counter, etc.
 After completing the task, the program control is transferred back to the
main program.
 These types of interrupts where the microprocessor pins are used to receive
interrupt requests are called Hardware Interrupts.
 The 8085 Microprocessor has five hardware interrupts.
1. TRAP
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR

2. Software Interrupts:
 In the case of software interrupts, the cause of the interrupt is the execution
of the instruction.
 The 8085 microprocessor has eight instructions. These eight instructions
are RST 0 to RST 7.
 Such interrupts are called software interrupts.
 They allow microprocessors to transfer program control from the main
program to the subroutine program.
 After completing the subroutine program. the program control returns back
to the main program.
Hardware Interrupts in 8085:
1. TRAP :
 It is a non-maskable, edge and level-triggered interrupt.
 It is unaffected by any mask or interrupt enable.
 The TRAP signal must make a LOW to HIGH transition and remain HIGH
until acknowledge. This avoids false triggering due to noise or glitches.
 It has the highest priority among all interrupts.
 This interrupt transfers the microprocessor’s control to location 0024H.
 Application: It is used for emergency purposes like power failure, parity
error checker, smoke detector, etc.
2. RST 7.5 :
 It is a maskable, edge-triggered interrupt request input line. This interrupt
is triggered at the rising edge of the signal.
 It has the highest priority among all maskable interrupts and the second
priority among all interrupts.
 The interrupt vector location for this interrupt is 003CH.
3. RST 6.5 and RST 5.5 :
 These are level-triggered, maskable interrupt request input lines.
 RST 6.5 transfer the microprocessor’s control to location 0034H while
RST 5.5 transfer the microprocessor’s control to location 002CH.
4. INTR :
 It is a level triggered, maskable interrupt request input line.
 This interrupt works in conjunction with RST N or CALL instruction.
 The INTR logic consists of an INTE flip-flop, OR gate, and inverter. The
INTR pin is logically ANDed with the output of the INTE flip-flop.
Software Interrupts in 8085:
 The 8085 microprocessor has eight instructions from RST 0 to RST 7.
 These instructions allow the transfer of program control from the main
program to predefined service routine addresses.
 A predefined service routine is also referred to as ISR.
 After completing the ISR program control is transferred back to the main
program.
 8085 microprocessor provides eight software interrupts RST 0 to RST 7;
These instructions are used to call interrupt service routine.
 Format of RST N Instruction OPCODE is as follows:

 The vector locations, for RST N instruction, are as follows:

  The difference between two successive locations is only 8 bytes. Hence
jump instructions must be stored in the corresponding location to transfer
the microprocessors’ control to the user-defined ISR address.
 Software interrupts are not used to handle asynchronous events. They are
used to call software routines like single steps, breakpoints, etc.

Comparison of Hardware interrupts and Software interrupts:

Sr. Software Interrupt Hardware Interrupt
No

1. It is a synchronous event. It is an asynchronous event.

2. This interrupt is requested by executing This interrupt is requested by an

instruction. external device on a pin.

3. PC in incremented. PC is not incremented.

4. The microprocessor does not execute any The microprocessor executes

interrupt acknowledge cycle to either interrupt acknowledge cycle
acknowledge this interrupt. The bus or idle machine cycle to
microprocessor executes a normal acknowledge this interrupt.
instruction cycle.

5. It cannot be ignored or masked. It can be masked except for

TRAP.

6. It has the highest priority among all The priority is lower than that of a
interrupts. software interrupt.

7. It does not affect interrupt control logic. It affects interrupt control logic.

8. It is not used to interface peripherals that It is used to interface peripherals

means it does not improve the throughput in interrupt-driven I/O. It
of the system. It is used in program improves the throughput of the
debugging. system.
Masking or unmasking of Interrupts in 8085:
For masking/unmasking of interrupts, there are four instructions:
1. EI 2. DI 3.RIM 4.SIM
1. EI : Enable Interrupt
 This instruction s used to enable all maskable interrupts. i.e. interrupts RST
7.5, RST 6.5, RST 5.5 and INTR can be enabled/activated using the EI
instruction.
 Whenever an interrupt is acknowledged, the interrupt enable flip-flop will
reset and all the interrupts ae disabled.
 If the interrupts are to be enabled, then the EI instruction is to be executed
within the ISR.
2. DI : Disable Interrupt
 This instruction resets the interrupt enable flip-flop i.e it can be used to
disable RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.
3. SIM : Set Interrupt Mask
 This instruction is used to enable/disable the RST 7.5, RST 6.5 and RST
5.5 interrupts.
 This instruction does not affect on the TRAP and INTR inputs.
 It can also be used for serial data transmission.
 It transfer the control word from accumulator to the interrupt control logic,
and the serial control logic.
 So, it is essential to load the control word into the accumulator before the
execution of SIM instruction.
  Bits D7 and D6 are serial port control. The SDE is enable bit used to
enable/disable serial output data. If D6 bit is enables, D7 bit is transferred
to SOD pin.
 Bit D4 is R 7.5 part of interrupt control logic. It is used to reset R 7.5 flip-
flop regardless of RST 7.5 masking.
 Bits D3 and D0 are part of interrupt control logic. These bits are used to
mask RST 5.5, RST 6.5 and RST 7.5 interrupts.
 The MSE bit is master control over M 7.5, M 6.5 and M 5.5 bits. If MSE
= 0, the M bits have no effect, but if MSE=1, the M bits decides mask or
unmask of respective interrupts.
4. RIM : Read Interrupt Mask
 This instruction is used to check the status of all pending and maskable
interrupts.
 It can also transfer serial data bit from the serial input data line to the D7
bit of the accumulator.
 This instruction transfer the contents of the interrupt control logic and
serial control logic to the accumulator. Hence accumulator is loaded with
the status fprate after execution of the RIM instruction.
 At a time, there can be more than one interrupt request may occur. In such
cases if the priority of interrupts is higher than they are serviced.
 The programmer can monitor the status of these pending interrupts using
RIM instruction.

RIM Formate
  Bit D7 is status of SID pin on serial port. When RIM instruction is executed
the logic level of SID pin is copied at bit D7.
 Bits D6, D5 and D4 are status of pending interrupts.
 Bits D3 to D0 are status of interrupt enable flip-flop, mask 7.5, mask 6.5
and mask 5.5. When RIM instruction is executed the status of masking is
loaded at bit D3 to D0.

Programmable Interrupt Controller 8259A:

For applications where we require multiple interrupt sources, we need to use
external devices called a programmable interrupt controllers (PIC).
By connecting PIC to the microprocessor we can increase the interrupt handling
capacity of the microprocessor.
8259A programmable interrupt controller is the commonly used priority interrupt
controller.
Features of 8259A PIC:
 It is an LSI chip that manages 8 levels of interrupts i.e., it is used to implement
8 level interrupt system.
 It can be cascaded in a master-slave configuration to handle up to 64 levels of
interrupts.
 It can identify the interrupting device.
 It can resolve the priority of interrupt requests i.e.; it does not require any extra
 It can be operated in various priority modes such as fixed priority and rotating
priority.
 The interrupt requests are individually maskable.
 It provides an 8-bit vector number as interrupt information.
 It does not require a clock signal.
 It can be used in polled as well as interrupt modes.
 The starting address of the vector number is programmable.
 It can be used in buffered mode. (Buffered mode is applicable for
multiprocessor systems).
Block Diagram of 8259A PIC:

(1) Data Bus Buffer: It is used to transfer data between the microprocessor and
internal bus.
(2) Read/Write control logic: It sets the direction of the data bus buffer. It controls
all internal read/write operations. It contains initialization and operation
command registers.
(3) Cascaded buffer and comparator: In master mode, it functions as a cascaded
buffer. The cascaded buffer outputs slave identification number on cascade lines.
In slave mode, it functions as a comparator. The comparator reads slave
identification numbers from cascade lines and compares this number with its
internal identification number. In buffered mode, it generates an EN signal.
(4) Control Logic: It generates an INT signal. In response to the INTA signal, it
releases a three-byte CALL address or a one-byte vector number. It controls
read/write control logic, cascade buffer/comparator, in-service register, priority
resolver, and IRR.
(5) Interrupt request register (IRR): It is used to store all pending interrupt
requests. Each bit of this register s set at the rising edge or at the high level of the
corresponding interrupt request line. The microprocessor can read the contents of
this register by issuing appropriate command words.
(6) In-service register (InSR): It is used to store all interrupt levels currently
being serviced. Each bit of this register is set by priority resolver and reset by the
End of the interrupt command word. The microprocessor can read the contents of
this register by issuing appropriate command words.
(7) Priority resolver: It determines the priorities of the bit set in the IRR. To make
a decision, the priority resolver looks at the ISR. If the higher priority bit in the
InSR is set then it ignores the new request. If the priority resolver finds that the
new interrupt has a higher priority than the highest priority interrupts currently
being serviced and the new interrupt is not in service, then it will set the
appropriate bit in the InSR and send the INT signal to the interrupt request.
(8) Interrupt mask register (IMR): It is a programmable register. It is used to
mask unwanted interrupt requests, by writing appropriate command words. The
microprocessor can read the contents of this register without issuing any
command word.

Pin Configuration of 8259A PIC:

Symbol Description

It is an active low-control input line. It is used to write data into

D0-D7
registers. it is connected to IOWR or MEMWR of the system bus.

It is an active low-control input line. It is used to read the contents

RD of the internal registers. it is connected to IOR or MEMR of the
system bus.
Symbol Description

It is an interrupt acknowledge input line. This signal is generated by

the microprocessor. The 8259A accepts two INTA pulses to release
WR
a one-byte vector number. The 8259 A does not work
without INTA pulses in vectored mode.

It is an address input line. it is used to select the appropriate control

A0 register. It is connected to one of the address lines of the system
address bus.

It is an active low-chip select input line. it is used to select the 8259

CS
A chip. This signal is generated by the address decoder.

These are bi-directional 3-bit cascade lines. These lines are used in
CAS0- cascade mode only. In master mode, these lines function as output
CAS2 lines. In this mode, the pIC places a 3-bit slave identification
number on cascade lines.

It is an active low bi-directional control line. In nonbuffered mode,

it functions as SP input line. In this mode, SP is used to distinguish
SP/ EN
between master and slave PICs. In buffered mode, it functions as
an EN output line. In this mode, it is used to enable data buffers.

It is an interrupt output line. it goes high whenever a valid interrupt

INT request is activated. It must be connected to the INTR input of the
microprocessor.

It is an interrupt acknowledge input line. This signal is generated by

the microprocessor. The 8259A accepts two INTA pulses to release
INTA
one-byte vector number. The 8259 A does not work
without INTA pulses in vectored mode.

These are asynchronous interrupt request input lines. These signals

are generated by peripherals. They can be used whether in edge-
IR0-IR7
triggered or level-triggered mode. The IR input should make low to
high transition n level as well as edge-triggered mode.
Priority Modes of 8259A:
The various priority modes of 8259A are:
1. Fully nested mode
2. Special fully nested mode
3. Rotating Priority mode
 The rotating priority mode can be set as:
1. Automatic rotation
2. Specific rotation
4. Special masked Mode

Operating Modes of 8259A:

8259 has two operating modes:
1. Interrupt drive: In this mode, 8259 Interrupts the processor with the INT pin
whenever it gets an interrupt.
2. Polled Mode: In this mode, the INT output is not used. The microprocessor
checks the status of the interrupt request by issuing the poll command.

Programmable Peripheral Interface 8255A:

The 8255A is a general purpose programmable I/O device designed to transfer
the data from I/O to interrupt I/O under certain conditions as required. It can be
used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be
configured as per the requirement.
Ports of 8255A:
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT
C upper (PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT
A and upper PORT C. Group B includes PORT B and lower PORT C. These two
groups can be programmed in three different modes, i.e. the first mode is named
as mode 0, the second mode is named as Mode 1 and the third mode is named as
Mode 2.

Operating Modes:
8255A has three different operating modes −
 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C
as two 4-bit ports. Each port can be programmed in either input mode or
output mode where outputs are latched and inputs are not latched. Ports do
not have interrupt capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can
be configured as either input or output ports. Each port uses three lines
from port C as handshake signals. Inputs and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port
and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port
C as handshake signals for data transfer. The remaining three signals from
Port C can be used either as simple I/O or as handshake for port B.

Features of 8255A:
The prominent features of 8255A are as follows −
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.
8255 Architecture:

Pin Diagram of 8255A:

Now let us discuss the functional description of the pins in 8255A -

Data Bus Buffer: It is a tri-state 8-bit buffer, which is used to interface the
microprocessor to the system data bus. Data is transmitted or received by the
buffer as per the instructions by the CPU. Control words and status information
is also transferred using this bus.
Read/Write Control Logic: This block is responsible for controlling the
internal/external transfer of data/control/status word. It accepts the input from the
CPU address and control buses, and in turn issues command to both the control
groups.
CS: It stands for Chip Select. A LOW on this input selects the chip and enables
the communication between the 8255A and the CPU. It is connected to the
decoded address, and A0 & A1 are connected to the microprocessor address lines.
Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

WR: It stands for write. This control signal enables the write operation. When
this signal goes low, the microprocessor writes into a selected I/O port or control
register.
RESET: This is an active high signal. It clears the control register and sets all
ports in the input mode.
RD: It stands for Read. This control signal enables the Read operation. When the
signal is low, the microprocessor reads the data from the selected I/O port of the
8255.
A0 and A1 : These input signals work with RD, WR, and one of the control signal.
Following is the table showing their various signals with their result.
 A1 A0 RD WR CS Result

Input Operation
0 0 0 1 0
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

8257 (DMA Controller):

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at
the fastest rate. It allows the device to transfer the data directly to/from memory
without any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address
and control bus, so the device is free to transfer data directly to/from the memory.
The DMA data transfer is initiated only after receiving HLDA signal from the
CPU.
How DMA Operations are Performed?
Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the
memory, the device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for
the CPU to assert the HLDA.
  Then the microprocessor tri-states all the data bus, address bus, and control
bus. The CPU leaves the control over bus and acknowledges the HOLD
request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.
Features of 8257:
 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer
operations.
 It generates MARK signal to the peripheral device that 128 bytes have been
transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.
8257 Architecture:
Data Bus Buffer: It is a tri-state, bi-directional, eight bit buffer which interfaces
the 8257 to the system data bus. In the slave mode, it is used to transfer data
between microprocessor and internal registers of 8257. In master mode, it is used
to send higher byte address (A8-A15) on the data bus.
Read/Write logic: When the CPU is programming or reading one of the internal
registers of 8257 Pin Diagram (i.e, when the 8257 is in the slave mode), the
Read/Write logic accepts the I/O Read (IOR) or I/O Write (IOW) signal, decodes
the the least significant four addiess bits (A0 – A3) and either writes the contents
of the data bus into the addressed register (if IOW is low) or places the contents
of the addressed register onto the data bus (if IOR is low).
During DMA cycles (i.e. when the 8257 is in the master mode) the Read/Write
logic generates the I/O read and memory write (DMA write cycle ) or I/O write
and memory read (DMA read cycle) signals which control the data transfer
between peripheral and memory device.
8257 DMA Controller Operating Modes: The 8257 Pin Diagram provides four
identical channels, labeled CH0 to CH3. Each channel has two sixteen bit
registers:
1. A DMA address register, and
2. A terminal count register.
DMA address register : Fig. 14.63 shows the format of DMA address register.
It specifies the address of the first memory location to be accessed. It is necessary
to load valid memory address in the DMA address register before channel is
enabled.

Terminal Count Register : Fig. 14.64 shows the format of Terminal Count
register.
Note : N is number of bytes to be transferred.
The value loaded into the low order 14 bits (C13 — C0) of the terminal count
register specifies the number of DMA cycles minus one before the terminal count
(TC) output is activated. Therefore, for N number of desired DMA cycles it is
necessary to load the value N-1 into the low order 14-bits of the terminal count
register. The most significant 2 bits of the terminal count register specifies the
type of DMA operation to be performed. It is necessary to load count for DMA
cycles and operational code for valid DMA cycle in the terminal count register
before channel is enabled.

Control logic:
It controls the sequence of operations during all DMA cycles (DMA read, DMA
write, DMA verify) by generating the appiopriate control signals and the 16-bit
address that specifies the memory location to be accessed. It consists of mode set
register and status register. Mode set register is programmed by the CPU to
configure 8257 whereas the status register is read by CPU to check which
channels have reached a terminal count condition and status of update flag.
Mode Set Register:
Fig. 14.65 gives the format of mode set register. Least significant four bits of
mode set register, when set, enable each of the four DMA channels. Most
significant four bits allow four different options for the 8257 Pin Diagram.
It is normally programmed by the CPU after initializing the DMA address
registers and terminal count registers. It is cleared by the RESET input, thus
disabling all options, inhibiting all channels, and preventing bus conflicts on
power-up.

Status Register:
Fig. 14.66 shows the status register format. As said earlier, it indicates which
channels have reached a terminal count condition and includes the update flag
described previously.
The TC status bit, if one, indicates terminal count has been reached for that
channel. TC bit remains set until the status register is read or the 8257 is reset.
The update flag, however, is not affected by a status read operation.
The update flag bit, if one, indicates CPU that 8257 is executing update cycle. In
update cycle 8257 loads parameters in channel 3 to channel 2.
Priority Resolver:
It resolves the peripherals requests. It can be programmed to work in two modes,
either in fixed mode or rotating priority mode.

8257 DMA Controller Pin Description:

DB0 − DB7: These bidirectional data lines connect the system bus to the DMA
controller's internal data bus. In Slave mode, It carries command words to 8257
and status words from 8257. These lines are utilized in master mode to send the
higher address byte of the produced address to the latch. This address is then
locked using the ADSTB signal.
A0 - A3: These are the four least significant address lines. They function as an
input in the slave mode, selecting one of the registers to be read or written. They
are the four least important memory address output lines generated by 8257 in
master mode.
A4 - A7: In the master mode, this is the upper nibble of the lower byte address
created via DMA.
DREQ0 − DREQ3: Peripheral devices utilize these four individual channel
DMA request inputs to access DMA services. When the fixed priority mode is
selected, DRQ0 is given the highest priority, and DRQ3 is given the lowest.
DACK0 - DACK3: These are the active-low DMA acknowledgment lines, which
notify the requesting peripheral of the CPU's status of their request. These lines
can also serve as beacon lines for the devices that want them.
IOR: It is an active-low bidirectional tri-state input line that the CPU uses in
Slave mode to access the internal registers of the 8257. It is used in the master
mode to read data from peripheral devices during a memory write cycle.
IOW: It is an active low bi-directional tri-state line that loads the data bus
contents into the 8-bit mode register or upper/lower byte of a 16-bit DMA address
register or terminal count register.
CLK: The internal operation of the 8257 requires a clock frequency signal.
RESET: This signal RESETS the DMA controller by turning off all DMA
channels.
CS: It is a select chip line. It permits read/write operations to and from 8257 in
Slave mode. It prevents read/write operations to/from 8257 while in master mode.
READY: It is an active-high asynchronous input signal that inserts wait states to
make DMA ready.
HRQ: This signal is used to receive the output device's hold request signal. In
slave mode, it is linked to DRQ input line 8257. In Master mode, it is coupled to
the CPU's HOLD input.
HLDA: When set to 1, the hold acknowledgment signal informs the DMA
controller that the CPU has granted the bus to the requesting peripheral.
MEMR: During DMA read cycles, the low memory read signal is utilized to read
data from the designated memory locations.
MEMW: During a DMA write operation, the active-low three-state signal is
utilized to write data to the specified memory region.
ADST: This signal transforms the DMA controller's upper byte of the memory
address into latches.
AEN: This signal is used to turn off the address/data bus.
TC: It is an abbreviation for 'Terminal Count,' representing the current DMA
cycle to the current peripheral devices.
MARK: The mark will be triggered every 128 cycles or integral multiples of 128
from the start. It denotes that the current DMA cycle is the 128th since the last
MARK output to the specified peripheral device.
Vcc: It is the power signal that is necessary for the circuit to function.
Control word format:

8253/8254 (Programmable Interval Timer):

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
microprocessors to perform timing and counting functions using three 16-bit
registers. Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT”
output. To operate a counter, a 16-bit count is loaded in its register. On command,
it begins to decrement the count until it reaches 0, then it generates a pulse that
can be used to interrupt the CPU.
Difference between 8253 and 8254:

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter Reads and writes of the same counter
cannot be interleaved. can be interleaved.

Features of 8253/54:
The most prominent features of 8253/54 are as follows −
 It has three independent 16-bit down counters.
 It can handle inputs from DC to 10 MHz.
 These three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which
allows the user to check the count value, the programmed mode, the current
mode, and the current status of the counter.
8253/54 Architecture:
1. Dats Bus Buffer:
 It is tristate, bidirectional 8-bit data bus buffer.
 It is used to interface 8254 data bus with system data bus.
 It is internally connected to internal data bus and its outer pins D0-D7 are
connected to system data bus. The direction of data buffer is decided by
read and write control signals.
2. Read/Write Logic:
 This block accepts inputs from system control bus and address bus.
 In I/O mapped I/O, the signals ‾RD and ‾WR are connected
to ‾IOR and ‾IOW.
 In memory mapped I/O ‾RD and ‾WR, are connected
to ‾MEMR and ‾MEMW.
 A0 and A1 are directly connected to address lines A0 and A1.
 ‾CS is connected to address decoder.
 The 8254 operation/selection is enables/disabled by ‾CS signal. A0,
A1 selects a specific part ‾WR, ‾RD decides writing data to 8254 or reading
data from 8254.
 The control word registers and the counters are selected according to the
signals on line A0 and A1.
A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control word register
3. Control Word Register:
 This register of 8254 programmable interval timer gets selected when A0=1
and A1=1.
 It is used to specify the BCD or binary counter to be used, its mode of
operation and the data transfer to be used i.e read or write the data bytes.
  If the CPU performs a write operation, the data is stored in the control word
register and is preffered to as control word. It is used to define counter
operation.
 The data can only be written into control word register, no read operation
is allowed. Status inforamtion is available with the help of read back
command.
 Following table shows the result for various control inputs –

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

4. Counters:
 There are three independent, 16-bit down counters.
 They can be programmed separately through control word register to
decide mode of counter.
 Each counter is having 2 inputs viz. CLK and GATE.
 CLK is used as an input to counnter and GATE is used to control the
counter.
 The counters give output on OUT pin.
 The loaded count value in counter will be decremented by counter at each
clock input pulse. The programmer can read counter without disturbing
counter operation.
Control Word Register Formate of 8254:

 The control word register bits, SC1 and SC0, select the control word register
for counter and used to initialize the counters.
 A0 and A1 selects counters, but they used to read/load counters by
microprocessor.
 The bits RL0 and RL1 are used to read/load, data bytes i.e LSB byte, MSB
byte or both LSB and MSB bytes.
 The bits M2, M1 and M0 decides the mode of operation for selected counter,
Mode0- Mode5.
 The bit, BCD, decides the mode of counting i.e BCD counter or binary
counter.

Operating Modes of 8254:

Mode 0 ─ Interrupt on Terminal Count
 It is used to generate an interrupt to the microprocessor after a certain
interval.
 Initially the output is low after the mode is set. The output remains LOW
after the count value is loaded into the counter.
  The process of decrementing the counter continues till the terminal count
is reached, i.e., the count become zero and the output goes HIGH and will
remain high until it reloads a new count.
 The GATE signal is high for normal counting. When GATE goes low,
counting is terminated and the current count is latched till the GATE goes
high again.
Mode 1 – Programmable One Shot
 It can be used as a mono stable multi-vibrator.
 The gate input is used as a trigger input in this mode.
 The output remains high until the count is loaded and a trigger is applied.
Mode 2 – Rate Generator
 The output is normally high after initialization.
 Whenever the count becomes zero, another low pulse is generated at the
output and the counter will be reloaded.
Mode 3 – Square Wave Generator
 This mode is similar to Mode 2 except the output remains low for half of
the timer period and high for the other half of the period.
Mode 4 − Software Triggered Mode
 In this mode, the output will remain high until the timer has counted to
zero, at which point the output will pulse low and then go high again.
 The count is latched when the GATE signal goes LOW.
 On the terminal count, the output goes low for one clock cycle then goes
HIGH. This low pulse can be used as a strobe.
Mode 5 – Hardware Triggered Mode
 This mode generates a strobe in response to an externally generated signal.
 This mode is similar to mode 4 except that the counting is initiated by a
signal at the gate input, which means it is hardware triggered instead of
software triggered.
 After it is initialized, the output goes high.
 When the terminal count is reached, the output goes low for one clock
cycle.
 Pin Configuration of 8254:

Symbol Name Function

These are 8-bit bidirectional data bus lines, connected to the

D7 – D0 Data Bus
system data bus for data transfer between 8085 and 8254.

This is an active low input signal, used to select the 8254 IC.
Chip
CS If ‾CS = 0 then 8254 will be active and take part in data transfer
Select
from/to 8085 otherwise 8254 will be in de-active state.

This is an active low input signal, used in coordination with A0,

‾RD Read
A1 to send data from appropriate counter to data lines D7 – D0.

This is an active low input signal, used in coordination with A0,

‾RD Write
A1 to load counters or to initialize counters.

Address These are input address lines used to distinguish different parts of
A0 – A 1
Lines 8254 such as counter 0, counter1, counter 2, control word register.

Clock These are clock inputs to 3 independent counters. The pulse

CLK0-2
Input applied at these pins will be counted by the respective counter.

These are active high, input signals used to allow external

Gate
GATE0-2 hardware to control the respective counter. The function of gate
Control
input is dependent on the operating mode.

These Lines are active high, output lines. The output is dependent
OUT0-2 Output
on operating modes.