1.

Number Conversion
2. Determine 1’s and 2’s complement.

3. Determine 10’s and 9’s complement.

 For 9’s Complement

4. Ex-1
 Ex-2 Explain the Boolean Function F= xy+x’z in a Product of Maxterms.

5. Simplify the Boolean function in a mimimum no. of literals.

Remember Me:
6. Find the complement of given Boolean function

7. Draw the following Boolean function using AOI logic

F1=xyz’, F2=x+y’z, F3=x’y’z+x’yz+xy’, F4=xy’+x’z
8. Draw the following Boolean function using NAND logic
Remember Me:

Ex-1 Represent in NAND Logic : F= (CD+E)(A+B’)

 Ex-2 Represent in NOR Logic : F= (AB+E) (C+D)

9. Simplify the following Boolean function using K-Map.

Ex-1

Ex-2

Ex-3
Ex-4

Ex-5

Ex-6

Ex-7
Ex-8

Ex-9

Ex-10
Ex-11

Ex-12

Ex-13
 Ex-14 Don’t Care Example

10.

Ans:
Remember Me: We can verify our answer by implement the same example using k-map which
is not compulsory for exam.
11. Explain Half adder and Full Adder.
Half Adder:

Full Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of
three inputs and two outputs. Two of the input variables, denoted by x and y , represent the two
significant bits to be added. The third input, z, represents the carry from the previous lower
significant position. Two outputs are necessary because the arithmetic sum of three binary digits
ranges in value from 0 to 3, and binary representation of 2 or 3 needs two bits. The two outputs
are designated by the symbols S for sum and C for carry.
12. Draw Full Adder circuit using two Half adder

13. Design a full adder circuit using decoder and Multiplexer.

 Full Adder using Multiplexer

14. Design 4 bit parallel adder.

15. Design a BCD adder.
BCD binary numbers represent Decimal digits 0 to 9.
A 4-bit BCD code is used to represent the ten numbers 0 to 9.
Since the 4-bit Code allows 16 possibilities, therefore the first 10 4-bit combinations are
considered to be valid BCD combinations. The latter six combinations are invalid and do not
occur.
BCD Code has applications in Decimal Number display Systems such as Counters and Digital
Clocks. BCD Numbers can be added together using BCD Addition. BCD Addition is similar to
normal Binary Addition except for the case when sum of two BCD digits exceeds 9 or a Carry is
generated. When the Sum of two BCD numbers exceeds 9 or a Carry is generated a 6 is added to
convert the invalid number into a valid number. The carry generated by adding a 6 to the
invalid BDC digit is passed on to the next BCD digit.
Addition of two BCD digits requires two 4-bit Parallel Adder Circuits. One 4-bit Parallel Adder
adds the two BCD digits.
16. Design 4-bit magnitude comparator in detail.
17. Design BCD to excess – 3 code converter.
18. Draw the logic diagram of 3 to 8 line decoder. Explain its operation with truth table.

19. Design 4-to-16 Decoder from two 3-to-8 Decoders.

20. What is encoder? With logic circuit and truth table explain the working of Octal to binary
Encoder.

21. What is Multiplexer? With logic circuit and function table explain the working of 4 to 1
multiplexer.
22. Ex-1 Implement combinational logic using 8:1line MUX for
F( A,B,C,D) = Σm( 0,2,4,5,7,9,12,15)
Here Maximum minterm value is m15. So total values are 16.
Here we have to take 16/2=>8:1 Multiplexer.
Ex-2 Implement combinational logic using MUX for
F( A,B,C) = Σm( 1,2,4,7)

Ex-3 Implement combinational logic using 8:1line MUX for

F( A,B,C,D) = Σm( 0,1,3,5,7,11,13,14,15)
23. Explain Demultiplexer.

24. Explain RS flip flop.

Explain JK Flip flop.
Explain T flip flop.
Explain D Flip flop.
RS flip Flop.
JK Flip Flop.
 T Flip Flop.

D Flip Flop.

25. Explain Master Slave Flip Flop.

Master Slave flip flop are the cascaded combination of two flip-flops among which the first is
designated as master flip-flop while the next is called slave flip-flop (Figure 1). Here the master
flip-flop is triggered by the external clock pulse train while the slave is activated at its inversion
i.e. if the master is positive edge-triggered, then the slave is negative-edge triggered and vice-
versa.
Using SR Flip Flop:

Using JK Flip Flop:

Working
When Clk=1, the master J-K flip flop gets disabled. The Clk input of the master input will be the opposite
of the slave input. So the master flip flop output will be recognized by the slave flip flop only when the
 Clk value becomes 0. Thus, when the clock pulse males a transition from 1 to 0, the locked outputs of the
master flip flop are fed through to the inputs of the slave flip-flop making this flip flop edge or pulse-
triggered. To understand better take a look at the timing diagram illustrated below.

26. Ex-1 Implement T flip flop using D flip flop.

Ex-2 Implement D flip flop using RS flip flop.
Ex-3 Implement JK flip flop using RS flip flop.
Example 1: Implement T flip flop using D flip flop. OR
Convert a D-FF to a T-FF:

We need to design the circuit to generate the triggering signal D as a function of T and

Q: . Consider the excitation table:

Treating as a function of and current FF state , we have

Example 2: Implement D flip flop using RS flip flop. OR
Convert a RS-FF to a D-FF:

We need to design the circuit to generate the triggering signals S and R as functions

of and . Consider the excitation table:

The desired signal and can be obtained as functions of and current FF

state from the Karnaugh maps:

Example 3: Implement JK flip flop using RS flip flop. OR

Convert a RS-FF to a JK-FF.

We need to design the circuit to generate the triggering signals S and R as functions

of , and . Consider the excitation table:

 The desired signal and as functions of , and current FF state can be
obtained from the Karnaugh maps:

27. Synchronous Counter

Remember Me:

Ex-1 Design 3bit synchronous up counter

Design and explain 3 bit down counter using T flip flop.
Ex: Design Synchronous BCD counter.
28. Ex-1 Design a counter with the following binary sequence: (With Lockout)
0, 1, 3, 7, 6, 4 and repeat. Use T flipflop.
Ex-2 Design a counter with the following binary sequence: (Without Lockout/ Avoid Lockout )
0, 1, 3, 7, 6, 4 and repeat. Use T flipflop.
Ex-3 Design a counter with the following binary sequence: (With Lockout)
0, 4, 2, 1, 6 and repeat. Use JK flipflop.

Remember Me:
Ex-1 Design a counter with the following binary sequence: (With Lockout)
0, 1, 3, 7, 6, 4 and repeat. Use T flipflop.

Ex-2 Design a counter with the following binary sequence: (Without Lockout/ Avoid Lockout )
0, 1, 3, 7, 6, 4 and repeat. Use T flipflop.

Ex-3 Design a counter with the following binary sequence: (With Lockout)
0, 4, 2, 1, 6 and repeat. Use JK flipflop.
29. Asynchronous Counter

Explain the working of 3 bit asynchronous counter.

C – Condition

E- Timing Diagram

Ex: Design 3 bit ripple Down counter. (asynchronous)

Ex: Explain the working of 4 bit asynchronous counter.

State Diagram

State Table
 State Equations

Logic Diagram

Timing Diagram

30. Explain Ring Counter

Explain Ring Counter
State Table

Ex: Explain Johnson Counters.

31. Explain Register.

Explain shift Register

32. Ex-1 Explain in detail bidirectional shit register.
Ex-2 Write a short note on four bit Universal Shift Register. OR Explain in detail bidirectional
shit register with parallel load.
Ex-1 Explain in detail bidirectional shit register.
With neat sketch design 4-bit bidirectional shift register and explain working of it in detail.

Ex-2 Write a short note on four bit Universal Shift Register. OR Explain in detail bidirectional
shit register with parallel load.

With necessary sketch explain Bidirectional Shift Register with parallel load.
Operations Table
S1 S0 Operation
0 0 Shift Right
0 1 Parallel Load
1 0 No load
1 1 Shift Left
33. List out Application of Shift Register and also find No. of Flip Flops required to build
following Shift Register.

34. Explain SM(State Machine) or Explain FSM(Finite Sate Machine) OR

Explain SM with its advantage, disadvantage and classification.
35. Define: state table, state equation, state diagram, input & output equations.
State Equation:
 I/O Equation- Basic Input Output Equation y=AB+BC’
36. Explain Melay machine & Moore machine.
Moore Machine
 CLC1-Combinational Logic Circuit-1, CLC2-Combinational Logic Circuit-2, ME- Memory
Element

Mealy Machine:

CLC1-Combinational Logic Circuit-1, CLC2-Combinational Logic Circuit-2, ME- Memory

Element

Note: Above contents only enough for 4 marks if question is for 7 marks include this also:
 Mealy Machine:

Moore Machine

37. General State machine Architecture.

Note: Write some contents from Q-34.
38. Explain Asynchronous Circuit.
An asynchronous circuit, or self-timed circuit, is a sequential digital logic circuit which is
not governed by a clock circuit or global clock signal. Instead they often use signals that
indicate completion of instructions and operations, specified by simple data transfer
protocols. This type is contrasted with a synchronous circuit in which changes to the
signal values in the circuit are triggered by repetitive pulses called a clock signal. Most
digital devices today use synchronous circuits. However asynchronous circuits have the
potential to be faster, and may also have advantages in lower power consumption, lower
electromagnetic interference, and better modularity in large systems. Asynchronous
circuits are an active area of research in digital logic design.

ADVANTAGES OF ASYNCHRONOUS CIRCUITS

 No clock skew (clock signal arrives at different time)
 Lower power (Synchronous : clock signal must be present every time and
everywhere.
 Average-case performance VS worstcase performance
 Easing of global timing issues
 Partial optimization
 Better external input handling
DRAWBACKS
 More difficult to design
 Concerns for hazards and glitches
 Unsure about faster performance
WHY ASYNCHRONOUS CIRCUITS?
 Used when speed of operation is important :Response quickly without waiting for a
clock pulse
 Used in small independent systems :Only a few components are required
 Used when the input signals may change independently of internal clock :Asynchronous
in nature
 Used in the communication between two units that have their own independent clocks
:Must be done in an asynchronous fashion
Mode of Operation:
Fundamental mode:
No simultaneous changes of two or more variables.
The time between two input changes must be longer than the time it takes the circuit to a stable
state The input signals change one at a time and only when the circuit is in a stable condition
Fundamental Mode
Pulse Mode:
The inputs and outputs are represented by pulses.
Only one input is allowed to have pulse present at any time.
Similar to synchronous sequential circuits except without a clock signal.
39.
40. Explain the Fundamental Mode Model of Asynchronous State Machine with suitable
example.
Note: Explain contents from Q-38(Asynchronous Circuit)

41. Analyze the following circuit and design State table and State Diagram.
OR
Analyze the various steps in the analysis of synchronous sequential circuit with
 suitable example.

42. Design Sequential circuit with 2 D Filp-Flop. A ,B, Input X , Input Y is specified by
the following Equation
A(t+1)=AX+BX
B(t+1)=A’X
Y=(A+B)X’
Draw Logic Diagram, State Table & State Diagram.
43.

44. Sequence Detector

Ex-1 Design State Table & State Diagram for Moore sequence detector to detect a sequence ----
110-
Ex-2 Design Moore sequence detector to detect a sequence ----101-using DF/F
Ex-1 Design State Table & State Diagram for Moore sequence detector to detect a sequence ----
110-

Ex-2 Design Moore sequence detector to detect a sequence ----101-using DF/F

 A sequence detector is a sequential state machine. In a Moore machine, output depends only on
the present state and not dependent on the input (x). Hence in the diagram, the output is written
with the states.
 The state diagram of a moore machine for a 101 detector is:

 The state table for the above diagram:

 Four states will require two flip flops. Consider two D flip flops. Their excitation table is shown
below.
 Excitation table:
  K-maps to determine inputs to D Flip flop:

 Circuit diagram for the sequence detector:

45. Write short note on: Read Only Memory (ROM)

ROM is a device that includes both the decoder and OR gates within a single IC package. ROM
consists of n inputs and m outputs.

o ROMs are integrated circuits that contain data and most often cannot be
altered.
o There are some types that can be somewhat modified that include
programmable ROM (PROM), erasable programmable ROM (EPROM),
electrically erasable programmable ROM (EEPROM) and Flash, which is a
 type of EEPROM.
o PROM is a type of ROM that can be programmed only once by a special
device and uses high voltages.
o EPROM can be rewritten using UV radiation
o EEPROM can be rewritten electrically and such devices do not require to
be removed from the computer.
o Flash drives are modern version of EEPROM and fastest to erase and
rewrite.
o Some other common types of ROM are CD-ROM, CD-R and CD-RW
which is used to store media and music files.
o In earliest stages, magnetic tapes were used as memory and with the
semiconductor revolution memory elements were also developed based on
semiconductors.
1. ROM: Read Only Memory
o ROM is only programmable once.
o For example, it could be programmed at the factory where they make the
chip. And indeed, it’s usually used in firmly hardcoded chips made by the
company.
o ROM is not "programmed at the factory” in the same sense that you imply or
even “programmed once”.
o It is programmed never.
o The data is hard-coded into the chip itself.
o Once the chip wafer is manufactured, that is it, it can never be changed, only
tested before it goes out.
o The ones and zeros are hard-coded connections to +V and ground.“

ROM PROM Board

2. PROM: Programmable Read Only Memory

o This is similar to ROM except that you, the consumer, can program it.
 o You can buy a blank chip and have a PROM programmer program it with
your stuff.
o But, once you program it, you can never change it.
o This is an example of a PROM programmer and you can just plug it into a port
on your computer as a peripheral.

3. EPROM: Erasable Programmable Read Only Memory

o So the cool this about this one is that you can rewrite this type of memory.
o To erase a previous program though, you need to set it under some form of
UV light for a specified amount of time before being able to rewrite it.
o You can see the window there that allows the UV light to get through and
erase the memory for you to rewrite.
o A company may use EPROM over ROM anytime they need something
different for each device, like a serial number. PROM is the older technology
while both PROM and EPROM are nonvolatile memory devices.
o PROMs can be programmed only once while EPROMs are reusable and can be
programmed multiple times.
o The process in the programming of PROMS is irreversible; hence the memory
is permanent. In EPROMs memory can be erased by exposure to UV light.

EPROM EEPROM

4. EEPROM: Electrically Erasable Programmable Read Only Memory

o So this one is the one that most people these days probably use.
o Essentially, it can be written, erased, rewritten electronically.
o No need for a fancy UV light thing.

Comparison chart
46. Design 32 × 4 ROM.
Remember Me: To Design ROM/PROM we have to use OR Gates and Decoder.

47. Implement the following using ROM. OR Implement the following using PROM.
F1 (A,B,C) = Σ (1,3,4,6)
F2 (A,B,C) = Σ (2,4,5,7)
F3(A,B,C) = Σ (0,1,5,7)
F4 (A,B,C) = Σ (1,2,3,4)
48. Implement the following two Boolean functions with a PLA

F1 (A,B,C) = Σ (1,3,5)
F2 (A,B,C) = Σ (5,6,7)

Step 1: Represent functions into reduced form.

Step 2: There is no any common term in F1 & F2. So we have to find F1’ & F2’.
Step 3: Here There is no any common term in F1’ & F2’. So we have to choose other
pair.

Here we found common term in F1’ & F2. So we will use it

PLA Program Table

49. A combinational circuit is defined by functions:
F1(A,B,C) = ∑(3, 5, 6, 7)
F2(A,B,C) = ∑(0, 2, 4, 7)
Implement the circuit with PLA having three inputs, four product term and two outputs

50. REALIZATION OF A COMBINATIONAL CIRCUIT USING PAL

Consider the following Boolean functions given in sum of minterms.

W (A,B,C,D) = Σ (2,12,13)
X (A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15)
Y (A,B,C,D) = Σ (0,2,3,4,5,6,7,8,10,11,15)
Z (A,B,C,D) = Σ (1,2,8,12,13)

Use K-map for Simplification:

Simplify the four functions to a minimum number of terms result in the following Boolean
functions
W=ABC’+A’B’CD’
X=A+BCD
Y=A’B+CD+B’D’
Z=ABC’+A’B’CD’+AC’D’+A’B’C’D=W+AC’D’+A’B’C’D.

The function for z has four product terms. The logical sum of two of these terms is equal to w. By
using w, it is possible to reduce the number of terms for z from four to three.

The PAL Programming Table is shown below:

Table : PAL Programming Table

51. Compare TTL, ECL, & CMOS logic families.
In computer engineering, a logic family may refer to one of two related concepts. A
logic family of monolithic digital integrated circuit devices is a group of electronic logic
gates constructed using one of several different designs, usually with compatible logic
levels and power supply characteristics within a family.

We have to mainly Study:

 Transistor-Transistor Logic(TTL),
 Emitter-Coupled Logic(ECL),
 MOSFET Logic,
IC Family Comparison:

Specification TTL CMOS ECL

Acronyms Transistor- (Complementary metal– Emitter-
Transistor oxide–semiconductor Coupled
Logic(TTL) logic). Logic (ECL)
Power High Lower High then
Consumption CMOS but
less then TTL
Power Dissipation Good lowest power dissipation Poor
Bipolar /Unipolar Bipolar Unipolar Bipolar
Design Using Bipolar Junction Field Effect Transistors Bipolar
BJT/FET Transistors (BJT) (FET) Junction
Transistors
(BJT)
Allow Higher Low High Low
Density of Logic
Function
IC Transistor Good Excellent Poor
Packaging Density
Propagation Delay 5 ns (TTL-ALS) 5 ns (CMOS-ACT) Lowest
0.75 ns (ECL
100k)
Basic Gate NAND NAND/NOR OR/NOR
Fan-out to other Good (10) Excellent Excellent (25)
chips in family (Highest fan out among
all logic families) (>50)
Noise immunity Good Excellent noise immunity Poor
Noise Margin Good Good OK
Durability High Low Low
Easily Destroy by static
 electricity
Required Extreme No No Yes
care in wiring
Suitable for Battery No Yes (Most) Yes
Operated Devices
Switching Speed Fast Slow High
52. Explain the digital IC Parameters.
 Fan In:
The fan-in defined as the maximum number of inputs that a logic gate can accept.
If number of input exceeds, the output will be undefined or incorrect.

 Fan Out:
The fan-out is defined as the maximum number of inputs (load) that can be
connected to the output of a gate without degrading the normal operation. Fan
Out is calculated from the amount of current available in the output of a gate and
the amount of current needed in each input of the connecting gate.

 Power Dissipation
It is the power consumed by the gate which must be available from the power
Supply.

 Noise:
Stray electric and magnetic fields can induce voltages on the connecting wires
between logic circuits, These unwanted, spurious signals are called noise

 Noise Immunity:
Circuit’s ability to tolerate noise without causing spurious changes in the output
voltage.

 Noise Margin:
It is the noise voltage which may be present without impairing (damage) the
proper operation of the circuit.

Quantitative measure of noise immunity is called Noise Margin.

o High-state noise margin : VNH = VOH (min) - VIH (min)

o Low-state noise margin : VNL = VIL (max) - VOL (max)
  Propagation Delay
It is the average transition delay time for the signal to propagate from input to
output when the signal changes in value.

53. Explain FPGA.

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a
customer or a designer after manufacturing – hence "field-programmable".
The FPGA configuration is generally specified using a hardware description language (HDL),
similar to that used for an application-specific integrated circuit (ASIC).
FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable
interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-
wired in different configurations.
The FPGA industry sprouted from programmable read-only memory (PROM) and
programmable logic devices (PLDs). PROMs and PLDs both had the option of being
programmed in batches in a factory or in the field (field-programmable).
A field-programmable gate array (FPGA) is an integrated circuit (IC) that can be programmed in
the field after manufacture. FPGAs are similar in principle to, but have vastly wider potential
application than, programmable read-only memory (PROM) chips. FPGAs are used by engineers
in the design of specialized ICs that can later be produced hard-wired in large quantities for
distribution to computer manufacturers and end users. Ultimately, FPGAs might allow
computer users to tailor microprocessors to meet their own individual needs.

Application:
 An FPGA can be used to solve any problem which is computable. This is trivially proven
by the fact FPGA can be used to implement a soft microprocessor, such as the Xilinx
MicroBlaze or Altera Nios II.
 Specific applications of FPGAs include digital signal processing, software-defined radio,
ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography,
bioinformatics, computer hardware emulation, radio astronomy, metal detection
and a growing range of other areas.
 Common FPGA Applications: Aerospace and Defense, Medical Electronics, Data Center,
Scientific Instruments, Video & Image Processing and Wireless Communications.