Design of Two Stage OTA

Md. Iqbal Bahar Chowdhury

March 6, 2024

Contents
1 Design formulae of OTA: 2
1.1 Calculation of CC : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Calculation of Currents: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Driver MOSFETs, M1 and M3 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Load MOSFETs, M2 and M4 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 Current-Source MOSFETs, M5 and M6 : . . . . . . . . . . . . . . . . . . . . . . . 3
1.6 Second Stage MOSFETs, M7 and M8 : . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Summary of Formulae 6

3 Pole Splitting 7

4 gm /ID Method for Single-stage OTA 8

4.1 For PMOS Driver MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 For NMOS Load MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 For Current source MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1
1 Design formulae of OTA:

Figure 1: OTA

• Driver MOSFETs (M1 , M3 ) of first stage are NMOS

• Load MOSFETs (M2 , M4 ) of first stage are PMOS

• Driver MOSFET (M7 ) of second stage is PMOS
• Load MOSFET (M8 ) of second stage is NMOS

• Current-Source and its associated MOSFETs (M6 , M5 ) are NMOS

1.1 Calculation of CC :
Calculation of CC is required for two-stage OTA, not for the single-stage.
CL
CC > (1)
10 × tan(84.290 − P M )

1.2 Calculation of Currents:

I5 = I6 = CC × Slew Rate , for 2-stage OTA (2)

= CL × Slew Rate , for 1-stage OTA (3)
I5
I1 = I2 = I3 = I4 = (4)
2

1.3 Driver MOSFETs, M1 and M3 :

gm1 = 2π × GBW × CC (5)

2
 
W gm1
= (6)
L 1,3 2I1 µn COX

2
1.4 Load MOSFETs, M2 and M4 :
Let, VD1 is the drain node of the M1 MOSFET. Then =>

VD1 = VDD − VDS2

= VDD − VGS2 , as the drain and the gate of M3 are shorted

From the drain current equation =>

s
2I2
VGS2 = W

+ |Vt2 |
µp COX L 2

The M1 MOSFET is in saturation, if and only if

VD1,min = ICM R+ − Vt1,min

where ICM R+ is the maximum VGS that can be applied to M1 to keep it in saturation. Therefor,
we can write
"s #
+ 2I2
ICM R − Vt1,min = VDD − − |Vt3 |max
µp COX W


L 2 max

Finally, the aspect ratio of M2,4 can be obtained from-

 
W 2I2
= (7)
L 2,4 µp COX V02

where V0 can be expressed as-

V0 = VDD − ICM R+ + Vt1,min − |Vt3 |max (8)

1.5 Current-Source MOSFETs, M5 and M6 :

The M5 MOSFET is in saturation, if and only if

VD5,min = ICM R− − VGS1,max

where ICM R− is the minimum VGS that can be applied to M1 to keep M5 in saturation.
VD5,min is also termed as VDS5,sat . Now, VGS1 can be expressed as-
s
2I1
VGS1 =
+ Vt1
µn COX W L) 1

Therefore, VDS5,sat can be written as

s
− 2I1
VDS5,sat = ICM R −
− Vt1.max (9)
µn COX W L) 1

Finally, the aspect ratio of M5,6 can be obtained from-

 
W 2I5
= 2 (10)
L 5,6 µn COX (VDS5,sat )

3
1.6 Second Stage MOSFETs, M7 and M8 :
Since M2 and M4 are connected as current-mirror arrangement
VGS4 = VGS3 = VDS3
Moreover, the aspect ratios of both M2 and M4 are same i.e
   
W W
=
L 2 L 4
and currents, I2 = I4 . Hence, it can safely assumed that
VGS4 = VDS4
Since, from Figure (1)
VDS4 = VGS7
it can be concluded that-
VGS7 = VGS3 = VGS4 (11)
Now, from MOSFETs M4 and M7 , we can write -
 
W
gm7 = µp COX (VGS7 − VT h7 ) (12)
L
 7
W
gm4 = µp COX (VGS4 − VT h4 ) (13)
L 4
and
 
W 2
I7 = µp COX (VGS7 − VT h7 ) (14)
L 7
 
W 2
I4 = µp COX (VGS4 − VT h4 ) (15)
L 4
Using the Eqn. (11) and remembering that VT h for M4 and M7 are same, it can be inferred that
-
W


gm7 L 7
= W

(16)
gm4 L 4
W


I7 L 7
= W

(17)
I4 L 4

Addition of CC between the gate and drain of M7 introduces a ’zero’ (Z0 ) in the OTA (as it
offers a parallel path for the signal to go to the output), the value of which can be expressed as
gm7
Z0 = (18)
2πCC
≥ 10 × GBW (19)
and hence,
gm7 ≥ 2π × 10 × GBW × CC (20)
≥ 10 × gm1 , Using Eqn. (29) (21)
Finally, gm4 and gm7 can be calculated as-
 
W
gm4 = µp COX (VGS4 − VT h4 ) (22)
L 4
gm7 = 10 × gm1 (23)

4
The aspect ratio of M7 can be calculated as-
   
W gm7 W
= × (24)
L 7 gm4 L 4

Since M8 is biased with M5 MOSFET using current mirror arrangement, the aspect ratio of M8
can be calculated as-
   
W I8 W
= ×
L 8 I5 L 5
 
I4 I8 W
= × ×
I5 I4 L
 5
I4 I7 W
= × ×
I5 I4 L 5
W

 
1 L 7 W
= × W
×
2 L 4
L 5

where,
I4 1
=
I5 2
gm7
I8 = I7 = × I4
gm4
W


L 7
I7 = W

× I4
L 4

5
2 Summary of Formulae
1. Currents and CC

I5 = I6 = CC × Slew Rate
I5
I1 = I2 = I3 = I4 =
2
CL
CC >
10 × tan(84.290 − P M )

2. For driver MOSFETs (M1 and M3 )

gm1 = 2π × GBW × CC
2
 
W gm1
=
L 1,3 2I1 µn COX

3. For load MOSFETs (M2 and M4 )

V0 = VDD − ICM R+ + Vt1,min − |Vt3 |max

 
W 2I2
=
L 2,4 µp COX V02

4. For current-source MOSFETs (M5 and M6 )

s
− 2I1
VDS5,sat = ICM R −
− Vt1.max
µn COX W L) 1
 
W 2I5
= 2
L 5,6 µn COX (VDS5,sat )

5. Driver MOSFET of the second stage (M7 )

s  
W
gm4 = 2I4 µp COX
L 4
gm7 = 10 × gm1
    
W gm7 W
=
L 7 gm4 L 4

6. Load MOSFET of the second stage (M8 )

W
   

 
W I4 WL 7
= × W


L 8 I5 L 5
L 4
W

 
1 L 7 W
= × W
×
2 L 4
L 5

6
3 Pole Splitting
Let us assume a two-stage OTA with n number of cascodes in the first stage. The pole at the
output of the first stage without CC can be expressed as
1
p1,old =  
n 1
2π (gm r0 ) r02 ||r04 || gm7 [CGS7 + CGB7 + (1 + AV 2 )CGD7 ]
1
≈  
n 1
2π (gm r0 ) r02 ||r04 || gm7 (1 + AV 2 ) CGD7

Here, AV 2 (the gain of the second stage ) ≫ 10 and hence,

(1 + AV 2 )CGD7 ≫ CGS7 + CGB7

The pole at the output of the first stage with CC can be expressed as
1
p1,new =  
n 1
2π (gm r0 ) r02 ||r04 || gm7 [CGS7 + CGB7 + (1 + AV 2 )(CGD7 + CC )]
1
≈  
n 1
2π (gm r0 ) r02 ||r04 || gm7 (1 + AV 2 ) CC

Here, AV 2 (the gain of the second stage ) ≫ 10 and CC ≫ CGD7 and hence,

(1 + AV 2 )CC ≫ CGS7 + CGB7 + (1 + AV 2 )CGD7

Therefore, the ratio of the poles are

p1,old CC
= ≫1
p1,new CGD7

This means that the p1,new is greatly shifted to the left from the p1,old .
The pole at the output of the second stage without CC can be expressed as
1
p2,old ≈
2π (r07 ||r08 ) CL

Here, CL ≫ the sum of all parasitic capacitances present at the output of the second stage.
The pole at the output of the second stage with CC can be expressed as
1
p2,old ≈
2π (r07 ||r08 ) (CL + CC )

Here, CC is added according to the Miller’s theorem. Therefore, the ratio of the poles are
p2,old CL + CC CL
= =1+ →1
p2,new CC CC

Since CC → CL , the ratio is slightly higher than unity. This means that the p2,new is slightly
shifted to the left from the p2,old .
Combining the findings mentioned above it can be concluded that the addition of CC greatly
shifted the pole p1 than the pole p2 . In other words, CC splits the poles futher away. This event
is called ‘Pole Splitting’.

7
4 gm /ID Method for Single-stage OTA
4.1 For PMOS Driver MOSFETs
• Required Specs: GBW, CL , Slew rate and Avdc (dB).
• Formulae:
ID1,2 = CL × Slew Rate
gm1,2 = 2π × GBW × CL
 
gm1,2
gds1,2 < 0.5 Avdc (dB)
10 20
NB : Avdc → not in dB
: factor 0.5 is used, as gds1,2 =gds3,4

• Steps:
   
gm gm
1. Calculate ID and gds .
1,2 1,2
2. Choose L from the gm /gds Vs. gm /ID chart for which the calculated values of gm /gds
and gm /ID closely match.
3. Choose ID /W and then calculate W from the ID /W Vs. gm /ID chart of the
driver MOS for the chosen L and calculated ID .

4.2 For NMOS Load MOSFETs

• Required Specs: Minimum input voltage (Vin,min ) and Total Integrated Noise
(Vn,rmsn ).
• Assume large value of gm /ID for load MOS i.e. smaller and close to gm /ID for driver MOS,
where
1. gds3,4 = gds1,2 .
2. ID3,4 = ID1,2 .
• Obtain L
 
gm
1. Calculate gm3,4 and gds .
3,4
2. Choose L from the gm /gds Vs. gm /ID chart of the load MOS for which the
calculated values of gm /gds and gm /ID closely match.
• Calculate minimum gm /ID of load MOS.
1. Use VGS Vs. gm /ID and Vdsat Vs. gm /ID charts of driver MOS to calculate
VGS3,4 using following formula.
|VGS3,4 | ≤ Vin,min + |VGS1,2 | − |Vdsat,2 | (25)
2. Estimate gm /ID from the VGS Vs. gm /ID chart of the load MOS. This is the
minimum value of gm /ID for the load MOS.
• Use γP Vs. gm /ID of driver PMOS and γN Vs. gm /ID of load NMOS to calculate
the maximum gm /ID of the load MOS using following formula.
!
2
20Vn,rms CL − γP
gm3,4 ≤ gm1,2 (26)
γN

• If the assumed gm /ID (usually a large value) is greater than the maximum gm /ID , then
assume a smaller value and repeat the whole process.
• Finally, choose ID /W and then calculate W from the ID /W Vs. gm /ID chart of the
load MOS for the chosen L and calculated ID .

8
4.3 For Current source MOSFETs
• Required Specs: VDD , Maximum input voltage (Vin,max ), Avdc (dB) and CMRR
(dB).
• Assume large value of gm /ID for current source MOS i.e. smaller and close to gm /ID for
driver MOS, where ID5,6 = 2× ID1,2 .
• Calculate gds5,6 using following formula

2gm1,2
gds5,6 < gm1,2 (27)
gm3,4
Avdc (dB)−CM RR(dB) −1
10 20

1. gds3,4 = gds1,2 .
2. ID3,4 = ID1,2 .
• Obtain L
 
gm
1. Calculate gm5,6 and gds .
5,6
2. Choose L from the gm /gds Vs. gm /ID chart of the current source MOS for
which the calculated values of gm /gds and gm /ID closely match.

• Calculate minimum gm /ID of current source MOS.

1. Use VGS Vs. gm /ID of driver MOS to calculate Vdsat5,6 using following formula.

|Vdsat5,6 | < VDD − |VGS1,2 | − Vin,max (28)

2. Estimate gm /ID from the Vdsat Vs. gm /ID chart of the current source MOS.
This is the minimum value of gm /ID for the current source MOS.
3. Use a larger value of gm /ID to ensure the saturation operation of current source MOS.
• Finally, choose ID /W and then calculate W from the ID /W Vs. gm /ID chart of the
current source MOS for the chosen L and calculated ID .

Pdiss
I = CL × Slew Rate =
VDD
gm1,2 = 2π × GBW × CL
gm1,2
Avdc = with gds2 = gds4
gds2 + gds4
Vin,min ≥ − |VGS1,2 | + |Vdsat,2 | + |VGS3,4 |
 
2 kT γef f gm3,4
Vn,rmsn < with γef f = 2 × γP + γN
CL gm1,2
Avdc,CM (dB) = Avdc (dB) − CMRR (dB)
gm1,2
gm3,4
Avdc,CM < 2gm1,2
1 + gds5,6
Vin,max ≤ VDD − |VGS1,2 | − |Vdsat5,6 |