L4
L4
Lecture 4: Processor/Central
Processing Unit (CPU)
http://www.flickr.com/photos/sarahseverson/
Madhusanka Liyanage
School of Computer Science
University College Dublin, Ireland
[email protected]
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Learning Objectives
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How we create Logic Gates and Also
Logic Circuits?
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Transistor
• The basic building block of complex electronic devices
• A semiconductor device for amplifying, controlling, and
generating electrical signals.
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Transistor
• Ideally suited for Binary operation
– Acts as a Switch which is On or
Off
• Combined to implement logic gates
– AND, OR, NOT
• Combined to build higher-level
structures
– E.g. Adder
• Combined to build processor
– more powerful computers
• Huge progress on miniaturisation:
– cheaper, quicker, smaller
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The first working transistor (1947)
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Evolution of the Transistor
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Integrated Circuits (IC)
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Transistor is the building block of modern CPUs
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Transistor size and density
• Manufacturing process
– 10 micrometers (10-6) in 1971
– 800 nm (10-9) in 1987
– 20-28 nm in 2010
– Intel 14nm in 2014
– Nvidia 11nm in 2015
– 3nm in 2022
• Reaching physically possible
limitations using current
technologies?
• Atom size 0.1nm - 0.5nm
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The new 2-nanometer
(nm) tech allows the
company to cram a
staggering 50 billion
transistors onto a chip
the size of a fingernail.
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Moore’s Law
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Components of a Computer System
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Central Processing Unit (CPU)
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But, how this CPU has designed?
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Von Neumann Architecture
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Von Neumann architecture
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Von Neumann architecture: CPU Components
• Memory Unit
– Once a user enters data using input devices, the computer
system stores this data in its memory unit.
– Data will remain here until other components of CPU process it.
– The memory unit uses a set of pre-programmed instructions to
further transmit this data to other parts of the CPU.
• Arithmetic and Logic Unit (ALU)
– Performs arithmetic operations.
– Do basic mathematical calculations like addition, subtraction,
division, multiplication, etc.
– Can even perform logical functions like the comparison of data.
• Control Unit
– The backbone of computers.
– Responsible for coordinating tasks between all components of a
computer system.
– Collects data from input units and sends it to processing units
depending on its nature.
– Also further transmits processed data to output units for users.
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Von Neumann architecture – Registers
• A processor based on Von Neumann
architecture has five special registers
which it uses for processing:
– Program counter (PC) - holds
the memory address of the next
instruction to be fetched from
main memory.
– Memory address register
(MAR) - holds the address of the
current instruction that is to be
fetched from memory, or the
address in memory to which data
is to be transferred.
– Memory buffer register (MBR)
- holds the contents found at the
address held in the MAR, or data
which is to be transferred to main
memory. It is also referred to as
the Memory Data Register (MDR).
– Current Instruction Register
(CIR) - holds the instruction that
is currently being decoded and
executed.
– Accumulator (ACC) - holds the
data being processed and the
results of processing. 25
Von Neumann architecture:
The fetch-execute cycle
• The fetch-execute
cycle (also known as
fetch-decode-execute
cycle) is followed by a
processor to process
an instruction.
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Von Neumann architecture - Key Features
• The key features of Von
Neumann architecture are:
– Data and instructions are
both stored as binary.
– Data and instructions are
both stored in main
memory.
– Instructions are fetched
from memory one at a time
and in order - serially.
– The processor decodes and
executes an instruction,
before cycling around to
fetch the next instruction.
– The cycle continues until no
more instructions are
available.
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Von Neumann architecture: The fetch-execute cycle Example
• The cycle consists of several stages.
1. The memory address held in the
program counter is copied into the
MAR.
2. The address in the program
counter is then incremented -
increased - by one. The program
counter now holds the address of
the next instruction to be fetched.
3. The processor sends a signal along
the address bus to the memory
address held in the MAR.
4. The instruction/data held in that
memory address is sent along the
data bus to the MBR.
• Program counter (PC)
5. The instruction/data held in the
• Memory Address Register (MAR) MBR is copied into the CIR.
Memory Buffer Register (MBR)/ Memory
•
Data Register (MDR) 6. The instruction/data held in the
• Current instruction register (CIR) CIR is decoded and then executed.
• Accumulator (ACC)
Results of processing are stored in
the ACC.
7. The cycle then returns to step one.
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Little Man Computer
• The Little Man Computer (LMC) is
an instructional model of a
computer, created by Dr. Stuart
Madnick in 1965.
• The LMC is generally used to teach
students, because it models a
simple von Neumann architecture
computer—which has all of the
basic features of a modern
computer.
• It can be programmed in machine
code (albeit in decimal rather than
binary) or assembly code.
• The original concept was that
inside the CPU is a tiny man who
runs around executing instructions
encoded in a list.
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Little Man Computer
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Little Man Computer
• Inside the CPU there are:
– 100 Memory locations (numbered 0 to 99), that can each contain a 3 digit
instruction or data (ranging from 000 to 999)
– An Arithmetic Unit to do calculations.
– An Accumulator to store the result of the last operation or
calculation.
– A Program Counter to store the address (in memory) of the next
instruction to do.
– An Instruction Register to hold the top digit of the instruction read
from memory.
– An Address Register to hold the bottom two digits of the instruction
read from memory.
– An Input tray into which a number can be typed when needed.
– An Output area where any numbers output are printed.
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LMC Cycle
• Two stages:
– The fetch portion of the cycle, in which the Little
Man finds out what instruction he is to execute,
– The execute portion of the cycle, in which he
actually performs the work specified in the
instruction
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Little Man Computer : Instruction Set
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LMC – Addition Example (Add Two
Inputs)
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Exercise: Simulate on LMC
http://peterhigginson.co.uk/LMC/
Step 1: Enter
the assembly
code
Step 2:
Assemble Step 3:
into RAM Run
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Real CPU
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Common CPU Components
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Arithmetic Logic Unit (ALU)
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Registers
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Registers
• Different processors have different numbers of
registers for different purposes, but most have some,
or all, of the following:
– Program Counter
– Memory Address Register (MAR)
– Memory Data Register (MDR)
– Current Instruction Register (CIR)
– Accumulator (ACC)
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Cache
• Cache is a small amount of high-speed Random-
Access Memory (RAM) built directly within the
processor.
• It is used to temporarily hold data and
instructions that the processor is likely to reuse.
• This allows for faster processing as the processor
does not have to wait for the data and
instructions to be fetched from the RAM.
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Buses
• A bus is a high-speed internal
connection.
• Buses are used to send control
signals and data between the
processor and other components.
• Three types of bus are used:
– Address bus - carries memory
addresses from the processor to
other components such as primary
memory and input/output devices.
– Data bus - carries the actual data
between the processor and other
components.
– Control bus - carries control
signals from the processor to other
components. E.g. clock's pulses.
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Bus Width and Speed
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Clock
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CPU performance : Clock speed
• Cache is a small
amount of high-speed
Random Access
Memory (RAM) built
directly within the
processor.
• The bigger its cache,
the less time a
processor must wait
for instructions to be
fetched.
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CPU performance: Number of cores
• A processing unit within a CPU
is known as a core.
• Each core is capable of
fetching, decoding and
executing its own instructions.
• The more cores a CPU has,
the greater the number of
instructions it can process in
each space of time.
• Many modern CPUs are dual
(two) or quad (four) core
processors.
• This provides vastly superior
processing power compared to
CPUs with a single core.
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CPU performance: Word Size
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CPU performance: Threads
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Instruction Set Architectures (ISA)
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Machine code
• A computer programming
language consisting of binary
(or hexadecimal) instructions
which a computer can respond
to directly
• The machine language contains
only two symbols 1 & 0
• Usually, assembly code is
converted into executable
machine code
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Instruction Set Architectures (ISA)
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Instruction Format
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Instruction Format - e.g. x86
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Runtime - Speed
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Performance Metrics : Runtime
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What can be done to speed up execution
at ISA Level?
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CISC vs. RISC
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More here: https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/
Summery
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Thank You
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