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Altair_PollEx_2021_Tutorials_SI

The document is an Intellectual Property Rights Notice for Altair Engineering Inc., detailing copyrights, trademarks, and software licenses for various Altair products. It includes information on technical support, training, and usage guidelines for Altair software, emphasizing the protection of intellectual property rights. Additionally, it provides contact details for technical support across different regions.

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Pallavi Jayram
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© © All Rights Reserved
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0% found this document useful (0 votes)
18 views

Altair_PollEx_2021_Tutorials_SI

The document is an Intellectual Property Rights Notice for Altair Engineering Inc., detailing copyrights, trademarks, and software licenses for various Altair products. It includes information on technical support, training, and usage guidelines for Altair software, emphasizing the protection of intellectual property rights. Additionally, it provides contact details for technical support across different regions.

Uploaded by

Pallavi Jayram
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 134

Altair PollEx 2021

SI Tutorials

altair.com
Intellectual Property Rights Notice
Copyrights, Trademarks, Trade Secrets, Patents & Third Party Software Licenses
Altair Engineering Inc. Copyright © 1986-2021. All Rights Reserved.
Copyrights in the below are held by Altair Engineering, Inc., except where otherwise explicitly stated.
This Intellectual Property Rights Notice is exemplary, not exhaustive.

Note: Pre-release versions of Altair software are provided ‘as is’, without warranty of any kind.
Usage of pre-release versions is strictly limited to non-production purposes.

Altair HyperWorks™ - The Platform for Innovation™


Altair AcuConsole™ © 2006-2021

Altair AcuSolve™ © 1997-2021

Altair Activate® © 1989-2021 (formerly solidThinking Activate)


Altair Compose® © 2007-2021 (formerly solidThinking Compose)
Altair ConnectMe™ © 2014-2021
Altair EDEM © 2005-2021 DEM Solutions Ltd, © 2019-2021 Altair Engineering Inc.

Altair ElectroFlo™ © 1992-2021

Altair Embed® © 1989-2021 (formerly solidThinking Embed)


• Altair Embed SE © 1989-2021 (formerly solidThinking Embed SE)
• Altair Embed/Digital Power Designer © 2012-2021
• Altair Embed Viewer © 1996-2021

Altair ESAComp™ © 1992-2021

Altair Feko™ © 1999-2014 Altair Development S.A. (Pty) Ltd., © 2014-2021 Altair Engineering Inc.

Altair Flux™ © 1983-2021

Altair FluxMotor™ © 2017-2021


Altair HyperCrash™ © 2001-2021
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Altair HyperXtrude™ © 1999-2021
Altair Inspire™ © 2009-2021 including Altair Inspire Motion, Altair Inspire Structures, and Altair Inspire
Print3D

Altair Inspire Cast © 2011-2021 (formerly Click2Cast)


Altair Inspire ElectroFlo © 1992-2021

Altair Inspire Extrude Metal © 1996-2021 (formerly Click2Extrude-Metal) Altair


Inspire Extrude Polymer © 1996-2021 (formerly Click2Extrude-Polymer) Altair
Altair PollEx 2021
Intellectual Property Rights Notice p.iii
Inspire Form © 1998-2021 (formerly Click2Form)
Altair Inspire Friction Stir Welding © 1996-2021

Altair Inspire Mold © 2009-2021


Altair Inspire Play © 2009-2021
Altair Inspire PolyFoam © 2009-2021
Altair Inspire Render © 1993-2016 Solid Iris Technologies Software Development One PLLC,
© 2016-2021 Altair Engineering Inc (formerly Thea Studio)
Altair Inspire Resin Transfer Molding © 1990-2021
Altair Inspire Studio © 1993-2021 (formerly ‘Evolve’)
Altair Manufacturing Solver™ © 2011-2021
Altair Material Data Center © 2019-2021

Altair MotionSolve™ © 2002-2021

Altair MotionView™ © 1993-2021

Altair Multiscale Designer™ © 2011-2021

Altair nanoFluidX™ © 2013-2018 Fluidyna GmbH, © 2018-2021 Altair Engineering Inc.

Altair newFASANT © 2010-2021


Altair OptiStruct™ © 1996-2021
Altair PollEx © 2003-2021 Altair
Radioss™ © 1986-2021
Altair Seam™ © 1985-2019 Cambridge Collaborative, Inc., © 2019-2021 Altair Engineering Inc.

Altair SimLab™ © 2004-2021

Altair SimSolid™ © 2015-2021

Altair ultraFluidX™ © 2010-2018 Fluidyna GmbH, © 2018-2021 Altair Engineering Inc.

Altair Virtual Wind Tunnel™ © 2012-2021

Altair WinProp™ © 2000-2021

Altair WRAP © 1998-2021 WRAP International AB, © 2021 Altair Engineering AB

Altair Packaged Solution Offerings (PSOs)


Altair Automated Reporting Director™ © 2008-2021

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Altair Model Mesher Director™ © 2010-2021

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Altair Virtual Gauge Director™ © 2012-2021
Altair Weight Analytics™ © 2013-2021
Altair Weld Certification Director™ © 2014-2021

Proprietary Information of Altair Engineering


Altair PollEx 2021
Intellectual Property Rights Notice p.iv
Altair Multi-Disciplinary Optimization Director™ © 2012-2021

Altair PBSWorks™ - Accelerating Innovation in the Cloud™


Altair PBS Professional® © 1994-2021

Altair Control™ © 2008-2021; (formerly PBS Control)


Altair Access™ © 2008-2021; (formerly PBS Access)
Altair Accelerator™ © 1995-2021; (formerly NetworkComputer)
Altair Accelerator™ Plus© 1995-2021; (formerly WorkloadXelerator)
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Altair Allocator™ © 1995-2021; (formerly LicenseAllocator)
Altair Monitor™ © 1995-2021; (formerly LicenseMonitor)
Altair Hero™ © 1995-2021; (formerly HERO)
Altair Software Asset Optimization (SAO) © 2007-2021

Note:
Compute Manager™ © 2012-2017 is now part of Altair Access Display

Manager™ © 2013-2017 is now part of Altair Access

PBS Application Services™ © 2008-2017 is now part of Altair Access

PBS Analytics™ © 2008-2017 is now part of Altair Control

PBS Desktop™ © 2008-2012 is now part of Altair Access, specifically Altair Access desktop,
which also has Altair Access web and Altair Access mobile

e-Compute™ © 2000-2010 was replaced by “Compute Manager” which is now Altair Access

Altair KnowledgeWorks™
Altair Knowledge Studio® © 1994-2021 Angoss Software Corporation, © 2021 Altair Engineering Inc.

Altair Knowledge Studio for Apache Spark © 1994-2021 Angoss Software Corporation, © 2021 Altair
Engineering Inc.

Altair Knowledge Seeker™ © 1994-2021 Angoss Software Corporation, © 2021 Altair Engineering Inc.

Altair Knowledge Hub™ © 2017-2021 Datawatch Corporation, © 2021 Altair Engineering Inc.

Proprietary Information of Altair Engineering


Altair PollEx 2021
Intellectual Property Rights Notice p.v
Altair Monarch™ © 1996-2021 Datawatch Corporation, © 2021 Altair Engineering Inc. Altair
Monarch Server © 1996-2021 Datawatch Corporation, © 2021 Altair Engineering Inc. Altair
Panopticon™ © 2004-2021 Datawatch Corporation, © 2021 Altair Engineering Inc.
Altair SmartWorks™
Altair SmartCore™ © 2011-2021 Altair Engineering Inc.
Altair SmartEdge™ © 2011-2021 Altair Engineering Inc.
Altair SmartSight™ © 2011-2021 Altair Engineering Inc.

Altair One™ © 1994-2021

Altair intellectual property rights are protected under U.S. and international laws and treaties. Additionally,
Altair software may be protected by patents or other intellectual property rights. All other marks are the
property of their respective owners.

ALTAIR ENGINEERING INC. Proprietary and Confidential. Contains Trade Secret Information.

Not for use or disclosure outside of Altair and its licensed clients. Information contained in Altair
software shall not be decompiled, disassembled, “unlocked”, reverse translated, reverse engineered,
or publicly displayed or publicly performed in any manner. Usage of the software is only as explicitly
permitted in the end user software license agreement. Copyright notice does not imply publication.

Third party software licenses


AcuConsole contains material licensed from Intelligent Light (www.ilight.com) and used by permission.
Software Security Measures:

Altair Engineering Inc. and its subsidiaries and affiliates reserve the right to embed software security
mechanisms in the Software for the purpose of detecting the installation and/or use of illegal copies of the
Software. The Software may collect and transmit non-proprietary data about those illegal copies. Data
collected will not include any customer data created by or used in connection with the Software and will not
be provided to any third party, except as may be required by law or legal process or to enforce our rights
with respect to the use of any illegal copies of the Software. By using the Software, each user consents to
such detection and collection of data, as well as its transmission and use if an illegal copy of the Software
is detected. No steps may be taken to avoid or detect the purpose of any such security mechanisms.

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Technical Support
Altair provides comprehensive software support via web FAQs, tutorials, training classes, telephone, and
e-mail.

Altair One Customer Portal


Altair One (https://altairone.com/) is Altair’s customer portal giving you access to product downloads,
a Knowledge Base, and customer support. We strongly recommend that all users create an Altair One
account and use it as their primary means of requesting technical support.

Once your customer portal account is set up, you can directly get to your support page via this link:
www.altair.com/customer-support/

Altair Training Classes


Altair’s in-person, online, and self-paced trainings provide hands-on introduction to our products, focusing
on overall functionality. Trainings are conducted at our corporate and regional offices or at your facility.

For more information please visit: https://learn.altair.com/

If you are interested in training at your facility, please contact your account manager for more details.
If you do not know who your account manager is, please contact your local support office and they will
connect you with your account manager.

Telephone and E-mail


If you are unable to contact Altair support via the customer portal, you may reach out to technical
support via phone or e-mail. Use the following table as a reference to locate the support office for your
region.

When contacting Altair support, please specify the product and version number you are using along with
a detailed description of the problem. It is beneficial for the support engineer to know what type of
workstation, operating system, RAM, and graphics board you have, so please include that in your
communication.

Location Telephone E-mail

Australia +61 649 413 7981 [email protected]

Brazil +55 113 884 0414 [email protected]

Canada +1 416 447 6463 [email protected]

China +86 400 619 6186 [email protected]

France +33 141 33 0992 [email protected]

Germany +49 703 162 0822 [email protected]


Altair PollEx 2021
Technical Support p.vii
Greece +30 231 047 3311 [email protected]

Location Telephone E-mail

India +91 806 629 4500 [email protected]

+1 800 425 0234 (toll free)

Israel [email protected]

Italy +39 800 905 595 [email protected]

Japan +81 36 225 5830 [email protected]

Malaysia +60 32 742 7890 [email protected]

Mexico +52 555 658 6808 [email protected]

New Zealand +64 9 413 7981 [email protected]

South Africa +27 21 831 1500 [email protected]

South Korea +82 704 050 9200 [email protected]

Spain +34 910 810 080 [email protected]

Sweden +46 46 460 2828 [email protected]

United Kingdom +44 192 646 8600 [email protected]

United States +1 248 614 2425 [email protected]

If your company is being serviced by an Altair partner, you can find that information on our web site at
https://www.altair.com/PartnerSearch/.

See www.altair.com for complete information on Altair, our team, and our products.

Proprietary Information of Altair Engineering


Contents
Intellectual Property Rights Notice .................................................................................... ii

Technical Support ............................................................................................................. vi

Conventions Used in this Guide ........................................................................................ 10

Notice .............................................................................................................................. 11

SECTION1: General Description ....................................................................................... 12

1. Create Design Project ................................................................................................... 13

[Lab.1 Create Project] ..................................................................................................14

SECTION2: Common Setup for SI Analysis ....................................................................... 16

1. Material Libraries.......................................................................................................... 16

[Lab.2 Add new dielectric material FR4.0 and PSR3.0] ......................................................17

2. Stack-up ..................................................................................................................... 20

[Lab.3 Build PCB stack].................................................................................................21

3. Simulation model assign ............................................................................................... 25

[Lab.4 Assigning IBIS model to DDR3 Memory device using Method 2] ...............................30

[Lab.5 Assigning IBIS to Controller] ...............................................................................37

[Lab.6 Assigning Passive Component Data to R and C (Part name base)] ............................38

[Lab.7 Assigning Passive Component Data to Array R and C] .............................................40

4. Nets ........................................................................................................................... 42

[Lab.8 Assigning Net properties for Power] ......................................................................44

[Lab.9 Assigning Net properties for Differential Pair].........................................................46

[Lab.10 Assigning Net properties automatically] ...............................................................48

5. Composite Nets ............................................................................................................ 50

[Lab.11 Making Composite Net] .....................................................................................53

SECTION 3: SI Analysis .................................................................................................... 55

1. Transmission Line Analysis ............................................................................................ 55

[Lab.12 Extracting the transmission line properties of specified Geometry] ..........................57

[Lab.13 Getting Impedance Matching Trace] ....................................................................64


Altair PollEx 2021 Tutorials
SI p.9
2. Network Analysis .......................................................................................................... 65

[Lab.14 Exploring the “Waveform” analysis] ....................................................................68

[Lab.15 Exploring the “Eye Diagram” analysis] ................................................................73

[Lab.16 Exploring the “Network Parameter” analysis] .......................................................75

3. Data Line Analysis ........................................................................................................ 77

[Lab.17 Exploring the “Data Line Analysis” analysis] .........................................................80

4. ADD/CMD/CTRL Line Analysis ........................................................................................ 87

[Lab.18 Exploring the “ADD/CMD/CTRL Line Analysis” analysis] .........................................89

5. Automatic DDR Bus Analysis .......................................................................................... 95

[Lab.19 Exploring the “Automatic DDR Bus Analysis”] .......................................................97

6. Crosstalk Analysis ...................................................................................................... 104

[Lab.20 Exploring the “Crosstalk Analysis”] ................................................................... 105

[Lab.21 Reducing the crosstalk noise by shorten the distance between the signal and ground
plane] ....................................................................................................................... 108

[Lab.22 Extracting “Network Parameter” among coupled net groups] ............................... 110

7. Net Topology Analysis ................................................................................................. 111

[Lab.23 Single-ended topology analysis (Type 5)] .......................................................... 112

[Lab.24 Topology analysis from selected Netlist] ............................................................ 117

SECTION 4: Radiated Emission Analysis ......................................................................... 124

[Lab.25 Exploring the “Radiated Emission Analysis”] ....................................................... 125

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Altair PollEx 2021 Tutorials
SI p.10

Conventions Used in this Guide


This guide uses the following conventions:
Bold All commands from the user interface. Options, menus, buttons, and dialog box names are
Italic bolded, but not italicized.

Example: On the Welcome screen, click Next.


Courier
The path of a program or folder; a web address; a file name or component; text that the
user is expected to enter.

Example: The default path is C:\Program Files\Altair\2020\PollEx

Questions regarding the document may be directed to PollEx team at [email protected].

Proprietary Information of Altair Engineering


Altair PollEx 2021 Tutorials
SI p.11

Notice
This tutorial contains numbers of practical labs helping users to practice the simulation features of PollEx
SI in intuitive manners. Therefore, the demo PCB data file named as SI_Sample.pdbb would be necessary
to execute these labs.

Before starting the labs in Section 2, please execute PollEx PCB program and activate the demo PCB
system by loading SI_Sample.pdbb file using File - Open PDB Binary File menu.

Please Note: If you follow this tutorial, the resulting waveform may differ slightly from the documented
waveform. This can happen when the environments for simulation are different. It is better not to change
the user's current environment, because changing the environment to follow the tutorial affects other
analysis results.
Please Note: After getting download file, uncompressing the file and save them into a certain folder. That
file saving folder would be job folder in this tutorial.

Proprietary Information of Altair Engineering


Altair PollEx 2021 Tutorials
SI p.12

SECTION1: General Description


Signal integrity or SI is a measure of the quality of an electrical signal. In digital electronics, a stream of
binary values is represented by a voltage (or current) waveform. Over short distance and at low bit rates,
a simple conductor can transmit this width enough fidelity. However, at high bit rates and over longer
distance, various effects can degrade the electrical signal to the point where error occur, and the system or
device fails. The purpose of signal integrity tool is the analyzing and mitigating these impairments.

Signal Integrity Analysis menus allow user to validate the design decisions throughout the design process
including the selection of parts, materials and board layer stack-up, placing components on the board, and
routing signal and power/ground nets.

Decades of years ago, the switching rise/fall time of the devices in the components were much larger than
the delays of the interconnections among components. As semiconductor technology brings in ever
increasing speed, the device switching rise/fall times become smaller and smaller. When the rise/fall time
of devices gets close to or smaller than the delay of interconnections, the integrity of the signals gets
degraded. This phenomenon is called the transmission line induced signal degradation or signal integrity
problem. In transmission line-based modeling, we need to model the time-of-flight delay of the
interconnection much more rigorously than the standard lumped circuit analysis. This extra effort is
necessary to account for the electromagnetic field interactions of the transmitted signals as well as time-
of-flight delays among the adjacent wires. In the modeling process, the capacitive and inductive coupling
among wires must be calculated. Furthermore, the impact of per-unit-length voltage and current changes
in time need to be studied.

In signal integrity analysis on individual nets or multiple coupled nets involves generating interconnect
topology description file, running 2-d and 3-d electromagnetic field solvers to analyze traces and vias,
generating SPICE netlist, running SPICE engine, and displaying the simulation results. The simulation results
include the transient waveforms, eye diagrams, and frequency-domain network parameters.

Proprietary Information of Altair Engineering


Altair PollEx 2021 Tutorials
SI p.13
1. Create Design Project

PollEx SI is based on a design project database containing entire data of a PCB design including the
materials, parts, physical layout, analysis models, and analysis result data. With the use of the unified
design project database, this application can be commonly used by multiple engineering disciplines.

File - Save as Project menu is used to create a new PollEx SI project directory from scratch. Upon
selecting the menu, a default design project name, Design_Name, is displayed as shown below.

Users can enter a new project name and select the project folder to put in the design folder. If a PollEx
PCB design project is already existing for the PCB design, instead of creating a new design project,
users can share the PollEx PCB design project by selecting the PollEx PCB design project folder for the
new project name.

When users create a project with entering a design name, design_name.pdbb and related files are
copied into that project directory. Along with progress on design and validation process, additional
folders and files are automatically generated under the project folder. Since PollEx SI finds the
necessary files in the prescribed design folder structure, it is important for users not to delete or move
files in the design folder.

Once the project is created, users should be use design_name.pdbb under project directory.

The project folder and its contents are shared with other PollEx applications such as PollEx PI and
PollEx Thermal.

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Altair PollEx 2021 Tutorials
SI p.14
[Lab.1 Create Project]

• Open the file, C:\Temp\Altair-PollEx\PollExSI\SI_Sample.pdbb using the main menu File -


Open.
• Click File - Save As Project: Save As Project dialog will be displayed.

• Enter a new project name and select the project folder to put in the design folder. Click OK to close
this dialog.
• The project directory is created under design folder, and SI_Sample.pdbb and related files are
copied into project directory.

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Altair PollEx 2021 Tutorials
SI p.15

• lick File - Exit to close this design.

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Altair PollEx 2021 Tutorials
SI p.16

SECTION2: Common Setup for SI Analysis


1. Material Libraries

Built in and user defined material library can be managed using Properties - Material Library menu.
By selecting this menu, Materials dialog will be displayed which allow user can add, modify and remove
certain materials and export the materials data as Material File (*.mtrl) which could be used by import
function.
By double clicking a certain material at Materials dialog or selecting and then clicking Edit(⑤) button,

the material properties can be modified. Clicking the Add Dielectric(③) or Add Conductor (④)
buttons pops up Edit dialog with empty values.

PollEx PCB provides default materials set and user can add or edit material properties.
For conducting material, user should define the electric resistivity, relative magnetic permeability and
thermal conductivity along to x, y and z axis. For dielectric material, dielectric constant, loss tangent
and thermal conductivity along to x, y and z axis would be needed.

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Altair PollEx 2021 Tutorials
SI p.17
[Lab.2 Add new dielectric material FR4.0 and PSR3.0]

• Click File - Open: Open C:\temp\Altair-PollEx\PollExSI\SI_Sample\SI_Sample.pdbb file. (You


should open .pdbb file in the project directory.)
• Click Properties - Material Library: By selecting this menu, Materials dialog will be displayed.

<Add FR4.0>
• Execute Add Dielectric button. By clicking this button, Edit dialog will be displayed.

• Type in FR4.0 at Material name field.


• Type in 0.35 at X, Y, Z field.
• Type in 4.0 at Dielectric Constant field.
• Type in 0.02 at Loss Tangent field. Your settings should now look as follows:

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Altair PollEx 2021 Tutorials
SI p.18

• Click OK to close to close Edit dialog.

<Add PSR3.0> - for solder resist layer


• Execute Add Dielectric menu. By clicking this menu, Edit dialog will be displayed.
• Type in PSR3.0 at Material name field.
• Type in 0.35 at X, Y, Z field.
• Type in 3.0 at Dielectric Constant field.
• Type in 0.02 at Loss Tangent field. Your settings should now look as follows:

• Click OK to close to close Edit dialog.

We can find that FR4.0 and PSR3.0 material is registered as new material with name, FR4.0 and PSR3.0.

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Altair PollEx 2021 Tutorials
SI p.19

• Click OK to close to close Materials dialog.

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Altair PollEx 2021 Tutorials
SI p.20
2. Stack-up

Properties - Layer Stack menu shows PCB’s physical stacked information will be used for Signal
Integrity and Thermal analysis. The stacking order, thicknesses and material properties of metallic and
dielectric layers are core parameters drawing dramatic changes of signal transmission qualities and
thermal distribution over PCB systems. Therefore, precise assignment should be given to Type,
Thickness, Conductor/Dielectric Material and the total thickness should be checked whether it shows
proper value. The value of thickness can be typed in after double clicking the area of numbers assigned.
Other parameters can be defined by clicking button and selecting one of the drop-down values.
Layer Type for power plane should be defined as Power and ground plane as Ground as displayed
below.
User can define PCB trace etching effect(⑤). The value of etching difference can be typed in after
double clicking the area of numbers assigned and the etching surface direction can be defined by clicking
button.
PollEx PCB provides default layer stack set and user can add or edit layer stack by clicking Import(⑥)

or Export(⑦) button. The default layer stack file path is: Installed directory/Data/Layer. User can add,
remove or insert each layer by clicking Add(⑧), Remove(⑨) or Insert(⑩) buttons. By selecting this
menu, Add dialog will be displayed which allow user can set material characteristics. User can export
the stack-up data in Excel formats.

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Altair PollEx 2021 Tutorials
SI p.21
[Lab.3 Build PCB stack]

• Click Properties - Layer Stack: By selecting this menu, Layer Stack dialog will be displayed.

• Execute Import menu. By clicking this menu, Explorer dialog will be displayed.
• Find the directory path in which your own stack-up files in navigation tree section.

We will use “C:\temp\Altair-PollEx\PollExSI\Stackup\StandardStackup.udls file.


(The PollEx also provides default stack-up, the path is: (C:\Temp\Altair-PollEx\PollExSI\Stackup)
• Select StandardStackup.udls for this 6-layer stack-up.

• Click OPEN to open this file and close Explorer dialog. Our stack-up should now look as follows:

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Altair PollEx 2021 Tutorials
SI p.22

<Change Dielectric Constant>


• Click at ① and select FR4.0. This procedure will change the dielectric constant for TOP layer
from 4.5 to 4.0.
• Click at ② and select FR4.0. This procedure will change the dielectric constant for Bottom layer
from 4.5 to 4.0.

<Add Solder resist layer to the Top layer and Bottom Layer>
• Select Top layer and click Insert button. The Add dialog will be displayed.

• Select Dielectric material as PSR3.0.


• Type in 0.02 at Thickness field. Your settings should now look as follows:

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Altair PollEx 2021 Tutorials
SI p.23

• Click OK button to close this window. You will find that new Solder Resist layer is inserted at the
top.

• Select Bottom layer and click Add button. The Add dialog will be displayed.

• Select Dielectric material as PSR3.0.


• Type in 0.02 at Thickness field. Your settings should now look as follows:

• Click OK button to close this window. You will find that new Solder Resist layer is inserted at the
bottom.

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Altair PollEx 2021 Tutorials
SI p.24

• Click Export button to save this stack-up. By clicking this menu, Explorer dialog will be displayed.
• Type StandardStackup_PSR as a new stack-up file name.
• Click OK to close Layer Stack dialog.

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Altair PollEx 2021 Tutorials
SI p.25
3. Simulation model assign

There are two ways to assign the simulation model:

1) Properties - Parts menu:


- Assign the need simulation model separately for each part
2) Properties - Components menu:
- Assign RLC model for passive components for each Reference designator.

Properties - Parts menu show the status of the properties assignment to the parts which are included
in the current PCB system to analyze. The unified parts created by PollEx UPE (Unified Part Editor) can
have versatile information such as electrical buffer model, package thermal parameters, power rail
information and 3D package geometry which needed for electrical, thermal and 2D/3D assembly
analysis (by PollEx DFA and PCB assembly viewer) and it would be stored in specific folders in local
or server system.

There are two ways to assign the part properties:


1) Assign the part properties individually when unified parts are not available.
2) Assign the part(s) properties automatically when unified parts are available.

To open the parts dialog:


Select Properties - Parts menu, Parts Manager dialog will be displayed.

And then some part of properties e.g. Part Name, UPF Name, Footprint, Package, Functional Type,
Passive value, Pin Count, Package/Electrical/Thermal icon and Reference Designation are appeared. The
RLC values of passive component(⑦) will be displayed automatically if they are defined in CAD file.

In the Link(⑫) filed, user can assign the path of Part library directory and MPN Reference file.
The empty Sync(①)column means the part properties are not referencing to any unified part data.
Therefore there is no check marks which are shown at the ⑨⑩⑪ columns when these are properly
assigned. All parts information is assigned (linked) by two methods above will be stored at Parts folder
which exists under project directory.

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Altair PollEx 2021 Tutorials
SI p.26

Part Properties Assignment Method 1:


Assign the part(s) properties automatically when unified parts are available.

To link the unified parts:


• Select Properties - Parts menu, Parts Manager dialog will be displayed.

• Click icon at Part library directory menu, to explore the library path for the unified parts,
select the desired UPFs folder and then click OK.
• Clicking Synchronize (⑭) button will start to assign the part properties.
There are no check marks which are shown at the ⑨⑩⑪ columns.

There will be many iconic marks appeared after the link operation is successfully done at Properties -
Parts dialog.

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• Contents name under UPF Library Part column denotes that UPF file exists under local Parts folder
for those parts.
• Icon under Package column denotes that 3D package geometry is linked with unified part.
• Icon under Electrical column denotes that electrical buffer model is called from unified part.
• Icon under Thermal column denotes that thermal information is called from unified parts.

Part Properties Assignment Method 2:


Assign the part properties individually when unified parts are not available.

When the unified parts are not available, users need to specify the needed part properties separately
for each part depending on the desired analysis type. To do SI Analysis, electrical properties are
essential.

There are three way to invoke the part setup dialog.


1) Double click the highlighted H5TQ4G63AFR(DDR3) part to invoke the Electrical & Thermal
Properties dialog.
2) Click the desired part and press the Edit Elec/Thermal Prop(⑮) button will invoke the same
Electrical & Thermal Properties dialog.
3) Press the Find Part by Reference(ⓑ) button will invoke the Find Part by Reference
Designator dialog. Write the desired reference name and press the OK button, then U204

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component will be highlighted. Double click the highlighted H5TQ4G63AFR(DDR3) part to
invoke the Electrical & Thermal Properties dialog.

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① Device Model File: Specify/register the IC models in the form of IBIS, SPICE, HSPICE, Linear
Device, S-Parameter, Package Parasitic and Y/Z parameters. To register and use the model in
Linear Device form, this model should be prepared using ⑥ Linear Device Modeler menu.

And the model in the form of Package Parasitic, it also should be prepared using ⑤ Package
Pin Parasitic Modeler menu ahead.

② Passive Component Data: Specify the part values in the form of RLC, SPICE and S-Parameter.
③ Power Rails: Specify the property of power rail for Power Integrity Simulation.
④ Package Thermal: Specify the package thermal property for Thermal Analysis.
⑤ Package Pin Parasitic Modeler: Enable to define package pin’s RLC parasitic model having
versatile sections and branches.

⑥ Linear Device Modeler: Enable to define simple linear device model for IC pin which will be
worked as one of the types among Input, Output, IO or Terminator. Depending on the selected
working type of these, user should define the bias and RLC values configuring the circuit topology.

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[Lab.4 Assigning IBIS model to DDR3 Memory device using
Method 2]
• Click Properties - Parts: The Parts dialog will display.
• Sort the result by clicking twice the Pin Count.

The passive component RLC values are automatically extracted from PDBB data, if the value property were
correctly assigned in PDBB database.

• Double click the part H5TQ4G63AFR. The Electrical & Thermal Properties dialog will be
displayed.

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• Click Device Model Files menu. The Device Model Files dialog will be displayed.

• Click Add menu in Device Model Files dialog.

• Click “ ” button to search and select IBIS file for DDR3 Memory device and click Open to open
this file and close this Explorer window.
(C:\temp\Altair-PollEx\PollExSI\Simulation_Model\Memory.ibs)

• Click OK button to close Model Files dialog. The Device Model Files dialog will be displayed again.

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The full location of the IBIS model file assigned to the DDR3 Memory device is shown at Device Model
Files dialog. After selecting the added IBIS file, Display menu allows you to investigate the detailed
electrical properties of the Input/Output buffer models included in IBIS file.

Input buffer models only contain Power_Clamp and Ground_Clamp characteristics. The DC (I-V) properties
of Pull_Up and Pull_Down transistors and AC properties given in Rising/Falling waveforms are just related
to the Output and IO buffer models. Then we can’t find any DC, AC information for Input buffer models.

• Select the 1st line and click Display menu will invoke the IBIS Manager as below. After moving the
Model tab menu, select DQ_DRV_34 (①), then we can find and review the all AC/DC properties by

clicking ③~⑧. By exploring the buffer’s AC/DC characteristics, you can choose the proper buffer
model for SI Analysis.

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• Click Close to close IBIS Manager.


• To close Device Model Files dialog, click OK button.

When the IBIS file contains numbers of different components (IC devices), we need to select one of them.
Pin count can be a good reference to select the right one. In this case the Select Component dialog will
be displayed.

• Select first component, Click OK to close Select Component Manager dialog. The Electrical &
Thermal Properties dialog will be displayed again.

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Now then you can acknowledge that DDR3 device’s part properties are assigned automatically as shown at
Electrical & Thermal Properties dialog below.

By selecting one of the tab menus among Signal Data, Driver/Receiver Model Data, Package Pin
Parasitic Model Data and Attribute, detailed information will be displayed, respectively.

Signal Data tab menu shows basic information such as Signal Name, Pin Type, Pull-down/Pull-up Ref
Signal and Inverted Pin status. Available Pin Type(②) are one of the None, Input, Output, IO,
Terminator, Power, Ground, NoConnect, TDI, TDO, TCK, TMS and TRST.

By selecting Driver/Receiver Model Data tab menu above, we can verify the detailed information related
to I/O buffer assignment for each pin included in the IC part.

Device Model column denoted as IBIS means that the pin’s model is defined from IBIS data is not from
SPICE, HSPICE or Linear Device Model. As column ③, certain pins are allowed to select one from many
available Driver or Receiver models. Please remind that the detailed AC/DC characteristics for each
Driver/Receiver Models can be investigated by Display menu at Device Model Files dialog.

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• Click OK to close Electrical & Thermal Properties dialog. You can see the Electrical icon of
H5TQ4G63AFR device is appeared.

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[Lab.5 Assigning IBIS to Controller]

• Double click the part IC-NXP4330 at the dialog invoked by Properties - Parts menu, and follow
the same procedures to assign IBIS model at Lab4. Assign CPU.ibs to it.

When you click OK button at Device Model Files dialog after defining the location of the IBIS, you have
to select one of proper component considering the pin counts.

• Select first component, Click OK to close Select Component Manager dialog.


• Click OK to close Electrical & Thermal Properties dialog.

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[Lab.6 Assigning Passive Component Data to R and C (Part
name base)]

Assigning the passive component data to discrete components like R, L, C and connector would be quite
quick and easy. Just double click the passive part and assign the proper values over Passive Component
Data dialog depending on the selected Model Type. RLC, SPICE and S-Parameter types are available.

• Double click the part RC1005J000CS at Parts dialog. The Electrical & Thermal Properties Dialog
will be displayed.

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• Click Passive Component Data at Electrical & Thermal Properties dialog. Just leave the Model
Type as RLC and put the Nominal Value and Resistance values and click OK.

• Click OK to close Electrical & Thermal Properties dialog.


• Click Close button at Parts dialog to close it.

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[Lab.7 Assigning Passive Component Data to Array R and
C]

When a passive is array component, you need to define the pin pair configuration.

• Click Properties - Parts: The Parts dialog will display.


• Double click the RA1005J000CS part which has more than two pins at Parts Dialog.
• Select Resistor as a function type, select Chip resistor as a package type.

• Click Passive Component Data at Electrical & Thermal Properties dialog. Just leave the Model
Type as RLC and put the Nominal Value and Resistance values like follows and click Pin Paring
button. The Pin Paring dialog will be open.

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• Repeating the Add function, you can define pin pairs. The specified passive component values will
be assigned separately to these paired pins.

• Click OK button to close Pin Paring Dialog.


• Click OK button to close Passive Component Data Dialog.
• Click OK button to close Electrical & Thermal Properties Dialog.
• Click Close button at Parts dialog to close it.

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4. Nets

Properties - Nets menu will invoke a dialog with default net properties as Single-ended signal for
all nets included in the activated PCB system, by double clicking a net or selecting a net and clicking
the Edit button, user can define or modify the Net Type(②), Voltage(⑤) and electrical
constraints(①). By clicking the Pin list(⑥), user can verify the list of all pins connected to the selected
net.

By clicking the Assign Net Type, user can set net type automatically using net information which
described in IBIS files.
But in this tutorial, we will assign net type manually for training purpose.
By clicking the Find Net Class, user can set net class automatically using net class definition. User can
see and modify current net class definition using Properties-Net Classes menu.

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The net class will be used to properly group DDR bus nets when performing Automatic DDR Bus
Analysis.

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[Lab.8 Assigning Net properties for Power]

• Click Properties - Nets menu. The Nets dialog will be displayed.


• Double click 5VCC net. The Edit dialog will be displayed.

• Select Net Type as Power (①) and type the voltage 5.0 at ②, Click OK.

<Basic parameters in Net Edit dialog>


• Net Type is type of net. Net type could be one of Single-ended signal, Diff Signal +, Diff Signal
–, Analog, Power or Ground.
• Net Class is class of net. User can generate required net class using Properties-Net Class menu.
By using net class assigned to each net, Target nets are automatically grouped when performing net
analysis.

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• Differential Pair – if net type is Diff Signal +, user has to specify the pair net of them.
• Composite Net shows composite net name.
• Voltage is the voltage level of net when the net type is Power or Ground.
• Pin List menu shows the list of net’s composing pins and their pin name and pin type.

<Electrical Constraints in Net Edit dialog>


• Single-Ended Impedance (Ohm) shows required single-ended impedance of signal net.
• Single Imp. Tolerance (%) shows allowable single-ended impedance tolerance.
• Differential Impedance (Ohm) shows required differential mode impedance of differential pair
net.
• Common Impedance (Ohm) shows required common mode impedance of differential pair net.
• Diff Imp. Tolerance (%) shows allowable differential/common mode impedance tolerance.
• Max Crosstalk Jitter (ps) shows the allowable crosstalk jitter.
• Max NE Crosstalk Noise (V) shows the allowable near-end crosstalk noise voltage.
• Max FE Crosstalk Noise (V) shows the allowable far-end crosstalk noise voltage.
• Operating Frequency (MHz) shows the nets’ operating frequency.
• Max Diff Pair Skew (ps) shows the allowable skew between differential pair nets.
• Eye Mask Height (V) shows allowable eye mask height size. “Default” means that use default eye
mask which defined in environment file.
• Eye Mask Top/Bottom Width (%) shows allowable eye mask width ratio of top/bottom point
related to UI time.
• Eye Mask Middle Width (%) shows allowable eye mask width ratio of middle point related to UI
time.

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[Lab.9 Assigning Net properties for Differential Pair]

At Nets dialog: (or properties-Nets menu) There are two ways to assign the net property:

<Way1>
• Double click MCU_ACK net. The Edit dialog will be displayed.
• Change Net Type as Diff Signal +.
• Select the other pair net MCU_ACKB as Diff Signal – using the scroll bar.

• Click OK button to close Edit dialog.

You will find that the MCU_ACK net and MCU_ACKB net are combined as a differential pair net.

<Way2>
• Multi selects MCU_NADQS0 and MCU_PADQS0 at Nets dialog.
• Click mouse right button, select Generate Differential Pair Net in the context menu.

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• The Edit dialog will be displayed. Click OK to close Edit dialog.

• Click OK button to close Nets dialog.

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[Lab.10 Assigning Net properties automatically]
Let’s assign net type.
• Click Properties-Nets menu. The Nets dialog will be displayed.
• Click Assign Net Type menu.

The PollEx SI set the types for all net automatically using net information which described in IBIS files and
property.

Let’s assign net class.


• Click Find Net Class menu.

The PollEx SI set the classes for all net automatically using default net class definition.

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• Click OK button to close Nets dialog.

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5. Composite Nets
When two or more nets are serially connected through passive components such as resistor, electrical
analysis must be made for the entire signal path encompassing the multiple nets connected with these
passive components. These nets are modeled as composite nets in PollEx PCB environment. The
composite nets are automatically generated by PollEx PCB which references the schematic data to
configure it by checking the connectivity of the selected passive components to each net.

In the upper left figure, two nets are connected with the R207 resistor, without composite nets
operation, these two nets might have open terminal for each then electrical simulation results for the
nets wouldn’t be appropriate.

Properties - Composite Nets menu provides versatile ways to manipulate the Composite Nets
generation and manage features with many options and operations illustrated below.

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In Composite Component Area①, user can select components to be used to generate composite net.
Two nets connected with this component are modeled as composite nets.
After selecting composite component, upon clicking Generate Composite Nets⑪ button, the list of
composite nets will be displayed on composite net result display region⑧.

User can remove or edit composite net result by Remove⑫ or Edit⑬ button.
By double clicking one of composite net, the Edit dialog will be displayed. User can change Net Type,
Net Class and Electrical Constraints.

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By clicking Composite Data⑥ field, user can review the composite net connection structure.

By clicking Pin List⑦ field, user can review the component and pin number connected to this composite
net.

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[Lab.11 Making Composite Net]
• Click Properties-Composite Nets menu.
• At composite component section region, check Resistor and Capacitor.
• Click Generate Composite Net.
• Selects Nets to Exclude dialog will be open. User can specify nets that should not be composited
with other nets such as Power and Ground nets.
• Select DCDC_5V and GNDADC nets, click OK and check the listed composited nets.

• If user click Composite Data or Pin List field, user can review composite net structure or pin list.

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If you want to check the total net composition status for the composited nets, use Option - Net 2D/3D
Viewer menu. Select the composite net CN-||MCU_HDMI_HPD||SIGN00248||. The secondly listed
composited net above configured with MCU_HDMI_HPD and SIGN00248 is displayed at the beginning of
this composite net chapter having R85 resistor.

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SECTION 3: SI Analysis
In this section, user can learn how to do versatile SI Analysis for the PCB system which is in Pre-route or
Post-route stages.

1. Transmission Line Analysis


Traces used for routing nets are modeled as transmission lines. Transmission Line Analysis menu is
used to run transmission line analysis to extract parasitic parameters and line characteristics of single
and multi-conductor trace models or to find impedance matching trace configurations in order to
minimize the signal integrity problems.

Creating a transmission line model starts with entering the model name and selecting the analysis type
among Extract Trace Parasitic Parameters and Get Impedance Matching Trace.

Add Conductor menu is used to add conductor or ground traces to the model. For each trace (conductor),
users need to select the conductor type (Conductor or Ground) and signal layer and define the conductor
width and location.
Display Model menu is used to graphically display the transmission line model.
Analysis on the model is performed upon selecting Analyze menu.
Upon completion of the analysis, the analysis results are automatically listed... Display Chart menu
allows users to view each item in a graph.

Getting trace configuration whose characteristic impedance matches the user-defined target impedance
value at the operating frequency starts with selecting the signal type among Single-ended,
Differential narrow, Differential broad, and Shielded.
For single-ended signal trace, users need to select the signal layer and specify the target impedance
to obtain the impedance matching trace width.
For narrow-side differential signal trace pair, users need to select the signal layer and specify the
target differential impedance. Users also need to specify either the trace width or separation between
the trace pair. With known trace width the trace separation value is obtained. On the other hand, with
known trace separation the trace width is obtained.
For broad-side differential signal trace pair, users need to select two adjacent signal layers and
specify the target differential impedance. Assuming the widths of the differential trace pair are identical,

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the trace width is obtained. Shielded signal type represents a signal trace surrounded by ground traces
at both sides.
For the shield signal trace, users are required to select the signal layer and specify the ground trace
width and target impedance. Users also need to specify either the signal trace width or separation
between the signal trace and ground traces. With known signal trace width, the trace separation value
is obtained. On the other hand, with known trace separation the signal trace width is obtained.

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[Lab.12 Extracting the transmission line properties of
specified Geometry]

• Click Properties - Layer Stack: By selecting this menu, Layer Stack dialog will be displayed.
• Execute Import menu. By clicking this menu, Explorer dialog will be displayed.
• Find the directory path in which your own stack-up files in navigation tree section.
(C:\temp\Altair-PollEx\PollExSI\Stackup)
• Select StandardStackup.udls for 6-layer stack-up. Click Open to select this stackup.
• Click OK to close Layer Stack dialog.
• Click File - Save menu to save current environment to PDBB file.

• Click Analysis - Signal Integrity - Transmission Line Analysis menu. Transmission Line
Analysis dialog will be invoked.
• Types in the model name as CLOCK_Diff.
• Click Extract Trace Parasitic Parameters.
• Click Add Conductor. The Conductor Information dialog will be displayed.

• Type in 0.1 at Width and click OK.

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• Click Display Model at the bottom of Transmission Line Analysis dialog. Just verify the stacked
up and trace shape and Close it.

• Click Analyze button. Shortly Transmission Line Analysis-Display Results dialog comes up. The
default properties shown at right side are Char-Impedance. Just switch the property display by
clicking other characteristics.

• Click Close button to close Transmission Line Analysis-Display Results dialog.

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By adding one more line, users can configure and analyze the electrical properties for differential pairs.

• Click Add Conductor.


• Type in 0.1 at Width, 0.2 at X and click OK. (X stands for the center to center distance between two
traces. Then the edge to edge distance between to traces will be 0.1.)

• Click Display Model at the bottom of Transmission Line Analysis dialog. Just verify the stacked
up and trace shape and Close it. (Two traces will be located at the same signal layer numbered as
1 and 2.)

• Click Analyze button. Shortly Transmission Line Analysis-Display Results dialog comes up.
Please note that the default properties shown at right side are Diff-Impedance. Just switch the
property display by clicking other characteristics.

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• Click Close button to close Transmission Line Analysis-Display Results dialog.


• Click Save and check this transmission line model shown at Model Name area of Transmission
Line Analysis dialog.

- To use the saved model later, Click the CLOCK_Diff model at left top of the dialog, and click Copy
button at left bottom of the dialog. Then the parameters defined before will be shown up for further edit
and analyze.

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<Model Routed Trace>


• Click Generate Multiple Models, then Generate Multiple Models dialog displayed.
• Click Model Routed Trace to extract current PCB trace model.
• Click Assign Model Names to assign default model name to extracted trace models.

• Click OK to close this dialog and check these transmission line models shown at Model Name area
of Transmission Line Analysis dialog.

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• Select all the transmission line models and click Run Analysis button to analyze them. Check all
the Impedance and Delay items.

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• Click Close button to close this dialog.

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[Lab.13 Getting Impedance Matching Trace]

• Click Analysis - Signal Integrity - Transmission Line Analysis menu. Transmission Line
Analysis dialog will be invoked.
• Types in the model name as CLOCK_DIFF_100.
• Click Get Impedance Matching Trace.
• Change the Signal type as Differential narrow. (Other available types: Single-ended, Differential
Broad, Shielded)
• Change the Unknown property as Separation.
• Type in 0.1 at Trace width and 100 at Differential impedance and click Analyze.

• Check the calculated Diff-Impedance value at the Transmission Line Analysis-Display Results
dialog. And click Close to close Transmission Line Analysis-Display Result dialog.

When the target impedance 100 is achieved, the center to center distance X will be displayed as below.
(Edge to edge distance will be 0.4. Click Display Model then the structure will be shown.)

• Click Save and Close button to close this dialog.

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2. Network Analysis

Analysis - Signal Integrity - Network Analysis menu enables user to execute three different types
of analysis mentioned above. The output waveform is influenced by the signal delay and reflections of
the selected net(s) but not by the crosstalk from the neighboring nets.

① Select Net: Net for analysis can be selected over Select Net dialog.
② Net Name: all selected net names will be listed.
③ Active Driver: User can specify the active driver pin among the connected pin to this net. The
other pins will be assigned as receiver pin(s) automatically.
④ Initial State: User can specify the initial value of input waveform.
⑤ Pulse Period: User can adjust the driver’s operating frequency/speed by changing this value.
⑥ Input Signal: When double click this Input signal button, user can change the detailed
parameters which can specify the actual shape of the input signal e.g. TD (Time Delay), TR (Rise
Time), TR (Fall Time) and PW (Pulse Width).

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⑦ Device Models: For the selected active driver, actual driver model can be selectable among
many different models in IBIS or Linear device model types. User can use one of available models
considering the output impedance, driving capability measured by output current level and
operating frequencies. These driver’s characteristics lead huge impact on the simulated
waveforms.

⑧ Analysis Type: Just click the one of desired analysis type. And then editable setting parameters
will be shown.
⑨ Simulation time: End time of the SPICE transient analysis.
⑩ Signaling time: Input Signal (⑤) having pulse period as ④ (2ns) will be excited to the net
until the time assigned here.
⑪ Bit pattern style: When user selects the Eye diagram analysis, user can change the random
bit generation algorithms among ABS, random and PRBS.
⑫ Bit pattern length: Total number of random bits will be applied to the net.
⑬ Network Analysis Parameters: Specify the start and end frequencies, total number of
frequency points and the method of sweeping the frequency points.
Linear: Network parameter will be solved for “50” frequency points between 1 MHz ~ 5000
MHz.

Decade: Network parameter will be solved for 150 frequency points, 50 points from 1MHz
~ 10MHz, 10MHz~100MHz and 100MHz~1000MHz respectively.

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⑭ Analyze: Three types of simulation will be started by this button. The desired nets for the
simulation should be checked as ① as below.
⑮ Save: Any nets have been simulated, can be saved and easily selected again when the PCB
reactivated later by saving these nets by this menu. The saved nets will be appeared ② region
as below.

ⓐ Model Name: Model name of the simulated and saved nets will be listed here.

ⓑ Copy: This menu enables the selected net(s) at region ② above will be registered at Select Net
region for analysis.

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[Lab.14 Exploring the “Waveform” analysis]

• Select Analysis - Signal Integrity - Network Analysis menu. The Network Analysis dialog will
be invoked.
• Click Select Net button on the right top of the Network Analysis dialog.
• Select MCU_NADQS0 and MCU_D0 nets and click OK.
• Check the desired net MCU_D0 to analyze as below(①).

• Click at ② and select U204-A2. This change makes the MCU_D0 net will be excited by this
device pin model. U204 is the reference name of a DDR memory device. Then this setting represents
the Data Read mode. When leave ② as U1-F5 as above, the net will be worked as Data Write
mode because the Active Driver is assigned as one of the data pin of the controller device.

• Change the Pulse Period(③) from 2 to 1.25.

• Click Input Signal (④) to verify the device pin model’s switching characteristics.

Total Pulse Period: (1.25) ns = TR (0.1) + 2 * PW (0.525) + TF (0.1).


Please note that TD means it just adds specified time as latency of the excitation. 1.25ns pulse will be
applied just after the TD (ns) pauses.

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• By clicking Define Pulse Data menu, user can specify the switching format as below.

• Click OK to close Input Signal Dialog.

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• Click Device⑤ at Network Analysis dialog, then user can check the connected components and pins
to the selected net through Device Model List dialog below. And if needed, user can change the
actual driver pin model among selectable models.
Just take the DQ_DRV_34 model listed on the top for U204-A2 driver.

• Just take the ODT_120 model for U1-F5 receiver and click OK.

Default signaling time is set by 5ns, then four cycles of the switching signals will be applied during the
SPICE waveform analysis.

• Select Waveform as an Analysis Type field.


• The waveform analysis is ready then click Analyze button at the bottom of the Network Analysis
dialog.

When the waveform analysis is started, electromagnetic simulation will extract the SPICE model for the
selected net. And the excitation source signal will be applied to the net which is specified by the assigned
pin model’s operating characteristics and the values defined at Input Signal and Pulse Period. When the
simulation is done, the “Waveform Viewer” will be displayed as below for exploring the waveforms.

• Click View Option button to invoke View Option Dialog.

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① Waveform display region.


② Result Data: Change the output format from graph to table data.
③ Toggle on and off to display certain desired waveform.
④ Background color can be changed.
⑤ When click X and Y, measure line will be appeared crossing the cursor, moves the mouse to the
desired position to measure and click there. Then the X and Y values will be displayed near the
clicked positions.
⑥ When both X and Y is checked at this Distance menu, the distance value between two measured
points will be displayed.
⑦ Edit the height and width of the eye mask when does the Eye Diagram analysis. After defining
the value, click Check Eye button to see the Eye mask. (Disenabled)
⑧ Simulated waveform can be saved with user specified name for invoking later comparison.
⑨ Open enables display and overlapping multiple waveforms.

• Close View Option dialog.


• Close Waveform Viewer.
• Click Save button to save simulation result.

You will find that those nets are saved into left window.

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[Lab.15 Exploring the “Eye Diagram” analysis]

When you finished the Lab.14, just switching the Analysis Type from Waveform to Eye Diagram
enable the eye analysis.

• Check the desired net MCU_D0 to analyze as below(①).

• Click Input Signal (④) column to open Input Signal dialog.


• Uncheck Define Pulse Data menu, to allow tool control bit stream.

• Click OK to close Input Signal dialog.


• Change the Bit pattern style to PRBS. And Bit pattern length to 2^7.

• Click the Analyze button.

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All 2^7 numbers of random bit will be applied to the net; the detailed bit signal pattern will follow the shape
defined at Input Signal.
When the simulation is done, the Waveform Viewer will be invoked.

• Please select U1_F5(i) as below. And click View Option to open View Option dialog.

• Change the value of the Eye Mask region as below and click Check Eye button. Eye mask will come
up then move the cursor and click where the position you want to check.

• Close Waveform Viewer.

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[Lab.16 Exploring the “Network Parameter” analysis]

• Select the Analysis Type as Network Parameter which enables the S, Y, Z-Parameter extraction
to the selected net(s).

• Just leave the default values for the analysis as below. 300 frequency points will be taken for the
parameter’s extraction.

• Click Analyze button to start analysis.

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① Region to select desired parameter among S, Y and Z.


② Select the value or unit to be displayed.
③ Toggle on and off the waveform. U204_a2::U1_F5 shows the insertion loss between two end
ports at the selected net. (Red colored)
④ Frequency scale: Linear or Log.
⑤ Clicking Result Data will display the parameters in table format.

• By clicking Result Data at the left top of the Waveform Viewer, user can verify the extracted
parameters in table data format.

• Select Port U204_A2::U1_F5 then the appropriate values will be displayed. By selecting one of
Touchstone data format at the bottom left of this dialog, user can export the data in Touchstone and
Excel formats.
• Select DB as Touchstone Data Format.
• Click Export to Touchstone File, save the s-parameter file.
• Click Save and Close button to close all invoked dialog including Network Analysis dialog.
• Click Close button to close Network Analysis dialog.

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3. Data Line Analysis

Analysis - Signal Integrity - Data Line Analysis menu enables user to analyze data byte group nets
in a one operation step.

① Select Strobe signal nets: Strobe signal net for analysis can be selected over Select Net
dialog.
② Select Data signal nets: Corresponding data byte nets for analysis can be selected over Select
Net dialog.
③ Net Name: all selected net names will be listed.
④ Active Driver: User can specify the active driver pin among the connected pin to this net. The
other pins will be assigned as receiver pin(s) automatically. For write cycle analysis select CPU
component as an active driver pin.
⑤ Device Models: For the selected active driver, actual driver model can be selectable among
many different models in IBIS or Linear device model types. User can use one of available models
considering the output impedance, driving capability measured by output current level and
operating frequencies. These driver’s characteristics lead huge impact on the simulated
waveforms.
⑥ Number of random pulses for eye diagram: Means the number of random pulses excited to
the simulating net during the eye diagram analysis.
⑦ Bit pattern style: Select the numerical method among random, ABS (Artificial Bit Stream) and
PRBS (Pseudo Random Bit Stream) for generating the bit sequences. ABS (Artificial Bit Stream)
is a method designed to provide a large pattern of bits to show worst case signal transmission

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quality of the net that would quickly converge the eye diagram. PRBS (Pseudo Random Bit
Stream) is the mostly common method deemed as an industry standard.
⑧ Bit pattern length: if bit pattern style is ABS or PRBS, choose the bit pattern length here.
⑨ Preamble time: Simulation start after this time to wait until status of internal circuit becomes
stable.
⑩ Data rate: Shows DDR operating speed.
⑪ Setup time: Shows required setup time.
⑫ Hold time: Shows required hold time.
⑬ DC threshold: Shows threshold voltage value for hold time measurement.
⑭ AC threshold: Shows threshold voltage value for setup time measurement.
⑮ DQS jitter: Enter system DDR bus jitter value.
ⓐ Import: By clicking Import tab users can choose required DDR operating speed from pre-defined
table. Then the contents field 10~15 will be filled with pre-defined value from JEDEC specification.

ⓑ Run Analysis: Simulation will be started by this button.


ⓒ Show Report: The analysis results can be listed in a table form by clicking Show Report tab.
They can be also shown in MS Excel.

ⓓ Save: Save menu saves the file in Signal_Integrity/Waveform directory under the PCB design
job folder. The model name plus.spe is used for the file name. The saved eye diagram waveform
data can be read into the waveform viewer alone or together with other eye diagram waveform
data.
ⓔ Model Name: Model name of the simulated and saved nets will be listed here.

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ⓕ Copy: This menu enables the selected net(s) at region ⓔ above will be registered at Select
Net region for analysis.

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[Lab.17 Exploring the “Data Line Analysis” analysis]

• Select Analysis - Signal Integrity - Data Line Analysis menu.

There are two way to select required signal nets.

<Way1: Select required nets manually>

• Click Select Strobe signal nets tab on the right top of the Data Line Analysis dialog.
• Select MCU_NADQS0 differential pair nets and click OK.
• Click Select Data signal nets tab on the middle of the Data Line Analysis dialog.
• Select MCU_D0~MCU_D7 data byte nets and click OK.

• Setup for MCU_NADQS0 nets:

• Click at ① and select U1_E4.

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When change ① as U1_E4 as above, the net will be worked as Data Write mode because the Active
Driver is assigned as one of the data pin of the controller device.

• Click Device Models at Data Line Analysis dialog, then user can check the connected components
and pins to the selected net through Device Model List dialog below. And if needed, user can
change the actual driver pin model among selectable models.
• Just take the DDR3_DQS_60ohm model listed on the top for U1 and take the DIN_ODT_OFF for
U204 and click OK.

• Setup for MCU_D0~MCU_D7 nets:

• Click at ① and select U1_F5.

When change ① as U1_F5 as above, the net will be worked as Data Write mode because the Active
Driver is assigned as one of the data pin of the controller device.
The rest of data byte nets driver configuration will be changed automatically with the same configuration
of MCU_D0 net.

• Click Device Models at Data Line Analysis dialog, then user can check the connected components
and pins to the selected net through Device Model List dialog below. And if needed, user can
change the actual driver pin model among selectable models.
• Just take the DDR3_60ohm model listed on the top for U1 and take the DIN_ODT_OFF for U204
and click OK.

The rest of data byte nets driver configuration will be changed automatically with the same configuration
of MCU_D0 net.

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• Set the DQS Jitter value to 50 at Analysis Parameter section.

• Click Import DDR Spec button at Analysis Parameter section, then user can select required DDR
operating speed from pre-defined table. Select DDR3.dls for a DDR Spec name field.

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• Select Data Rate to 1066 for DDR3_1066_AC175 Operation and click OK button.

• The waveform analysis is ready then click Run Analysis button at the bottom of the Data Line
Analysis dialog.

When the data line analysis is started, electromagnetic simulation will extract the SPICE model for the
selected net. And the excitation source signal will be applied to the net which is specified by the assigned
pin model’s operating characteristics. When the simulation is done, the Waveform Viewer will be displayed
as below for exploring the all signals waveforms.

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The eye-mask for DDR3_1066_AC175 operation is also displayed.

① Waveform display region.


② Result Data: Change the output format from graph to table data and can export the data in MS
Excel formats.
③ Toggle on and off to display certain desired waveform.
④ Background color can be changed.
⑤ When click X and Y, measure line will be appeared crossing the cursor, moves the mouse to the
desired position to measure and click there. Then the X and Y values will be displayed near the
clicked positions.
⑥ When both X and Y are checked at this Distance menu, the distance value between two
measured points will be displayed.
⑦ Edit the height and width of the eye mask when does the Eye Diagram” analysis. After defining
the value, click Check Eye button to see the Eye mask.
⑧ Open enables display and overlapping multiple waveforms.
⑨ Simulated waveform can be saved with user specified name for invoking later comparison.
⑩ User can see specific data lines among all data byte lines.
⑪ User can see transient waveform by pressing Display Waveform button.

• Close the Waveform Viewer.


• Click save button to save the result.
• Click close button to close Data Line Analysis dialog.

<Way2: Select required net group automatically>

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• Select Analysis - Signal Integrity - Data Line Analysis menu.


• Click Auto Generation Bytelane button to extract possible byte lane combinations automatically.
The result combination will be displayed into left Model window.

• Just select required combination and click copy button. Then selecte3d combinations will be copied
to right window.

The remaining steps are the same as “Way1” method.

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• Close the Waveform Viewer.


• Click save button to save the result.
• Click close button to close Data Line Analysis dialog.

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4. ADD/CMD/CTRL Line Analysis

Analysis - Signal Integrity - ADD/CMD/CTRL Line Analysis menu enables user to analyze
address/command/control group nets of DDR BUS in a one operation step.

① Select Clock signal nets: Clock signal net for analysis can be selected over Select Net dialog.
② Select Address/Command/Control signal nets: Address/Command/Control nets for
analysis can be selected over Select Net dialog.
③ Net Name: all selected net names will be listed.
④ Active Driver: User can specify the active driver pin among the connected pin to this net. The
other pins will be assigned as receiver pin(s) automatically. Only CPU component can be selected
as an active driver pin.
⑤ Device Models: For the selected active driver, actual driver model can be selectable among
many different models in IBIS or Linear device model types. User can use one of available models
considering the output impedance, driving capability measured by output current level and
operating frequencies. These driver’s characteristics lead huge impact on the simulated
waveforms.
⑥ Number of random pulses for eye diagram: Means the number of random pulses excited to
the simulating net during the eye diagram analysis.
⑦ Bit pattern style: Select the numerical method among random, ABS (Artificial Bit Stream) and
PRBS (Pseudo Random Bit Stream) for generating the bit sequences. ABS (Artificial Bit Stream)
is a method designed to provide a large pattern of bits to show worst case signal transmission
quality of the net that would quickly converge the eye diagram. PRBS (Pseudo Random Bit
Stream) is the mostly common method deemed as an industry standard.
⑧ Bit pattern length: if bit pattern style is ABS or PRBS, choose the bit pattern length here.
⑨ Preamble time: Simulation start after this time to wait until status of internal circuit becomes
stable.

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⑩ Data rate: Shows DDR BUS operating speed.
⑪ Setup time: Shows required setup time.
⑫ Hold time: Shows required hold time.
⑬ DC threshold: Shows threshold voltage value for hold time measurement.
⑭ AC threshold: Shows threshold voltage value for setup time measurement.
⑮ ADD/CMD/CTRL signal mode: Select address bus mode.
ⓐ Import: By clicking Import tab users can choose required DDR operating speed from pre-defined
table. Then the contents field 10~15 will be filled with pre-defined value from JEDEC specification.

ⓑ Run Analysis: Simulation will be started by this button.

ⓒ Show Report: The analysis results can be listed in a table form by clicking Show Report tab.
They can be also shown in MS Excel.

ⓓ Save: Save menu saves the file in Signal_Integrity/Waveform directory under the PCB design
job folder. The model name plus.spe is used for the file name. The saved eye diagram waveform
data can be read into the waveform viewer alone or together with other eye diagram waveform
data.
ⓔ Model Name: Model name of the simulated and saved nets will be listed here.

ⓕ Copy: This menu enables the selected net(s) at region ⓔ above will be registered at Select Net
region for analysis.

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[Lab.18 Exploring the “ADD/CMD/CTRL Line Analysis”
analysis]

• Execute Analysis - Signal Integrity - ADD/CMD/CTRL Line Analysis menu.

There are two way to select required signal nets.

<Way1: Select required nets manually>

• Click Select Clock signal nets tab on the right top of the ADD/CMD/CTRL Line Analysis dialog.
• Select MCU_ACK differential pair nets and click OK.
• Click Select Address/Command/Control signal nets tab on the middle of the ADD/CMD/CTRL
Line Analysis dialog.
• Select MCU_AA0~MCU_AA14 nets and click OK.

• Setup for MCU_ACK nets:

• Click at ① and select U1_L2. Only the CPU can drive clock and control line at DDR bus.
• Click Device Models at ADD/CMD/CTRL Line Analysis dialog, then user can check the connected
components and pins to the selected net through Device Model List dialog below. And if needed,
user can change the actual driver pin model among selectable models.
• Just take the DDR3_DQS_60ohm model listed on the top for U1 and take the CLK for U204/U205
and click OK.

• Setup for MCU_AA0~MCU_AA14 nets:

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• Click at ① and select U1_J6. Only the CPU can drive clock and control line at DDR bus.

The rest of address nets driver configuration will be changed automatically with the same configuration of
MCU_AA0 net.

• Click Device Models at Select Address/Command/Control signal nets dialog, then user can
check the connected components and pins to the selected net through Device Model List dialog
below. And if needed, user can change the actual driver pin model among selectable models.
• Just take the DDR3_60ohm model for U1 and take the INPUT for U204/U205 and click OK. The
rest of address nets driver configuration will be changed automatically with the same configuration
of MCU_AA0 net.

• Set the Clock Jitter value to 50 at Analysis Parameter section.


• Set the ADD/CMD/CTRL signal mode to 1T at Analysis Parameter section.
• Click Import DDR Spec button at Analysis Parameter section, then user can select required DDR
operating speed from pre-defined table. Select DDR3.dls for a DDR Spec name field.

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• Select Data Rate to 1066 for DDR3_1066_AC175 Operation and click OK button.

• The waveform analysis is ready then click Run Analysis button at the bottom of the
ADD/CMD/CTRL Line Analysis dialog.

When the address/command/control line analysis is started, electromagnetic simulation will extract the
SPICE model for the selected net. And the excitation source signal will be applied to the net which is specified
by the assigned pin model’s operating characteristics. When the simulation is done, the Waveform Viewer
will be displayed as below for exploring the all signals waveforms. The eye-mask for DDR3_1066_AC175
operation is also displayed.

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① Waveform display region.


② Result Data: Change the output format from graph to table data and can export the data in MS
Excel formats.
③ Toggle on and off to display certain desired waveform.
④ Background color can be changed.
⑤ When click X and Y, measure line will be appeared crossing the cursor, moves the mouse to the
desired position to measure and click there. Then the X and Y values will be displayed near the
clicked positions.
⑥ When both X and Y are checked at this Distance menu, the distance value between two
measured points will be displayed.
⑦ Edit the height and width of the eye mask when does the Eye Diagram analysis. After defining
the value, click Check Eye button to see the Eye mask.
⑧ Simulated waveform can be saved with user specified name for invoking later comparison.
⑨ Open enables display and overlapping multiple waveforms.
⑩ User can see specific lines among all lines.
⑪ User can see transient waveform by pressing Display Waveform button.

• Close Waveform Viewer.


• Click save to save result.

<Way2: Select required net group automatically>

• Click Auto Generation Bytelane button to extract possible address/control/command line


combinations automatically. The result combination will be displayed into left Model window.

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• Just select required combination and click Copy button. Then selected combinations will be copied
to right window.

The remaining steps are the same as “Way1” method.

• Close the Waveform Viewer.


• Click Save button to save the result.

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• Click Close button to close ADD/CMD/CTRL Line Analysis dialog.

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5. Automatic DDR Bus Analysis

Automatic DDR Bus Analysis menu is used for automatically extracting all data strobe, data, clock,
address, command, and control line nets of DDR (double data rate) memory interfaces including DDR
(DDDR1), DDR3, and DDR3, automatically constructing data line, address line, command line, and
control line analysis models, performing eye diagram analyses on all of the models, and calculating the
setup and hold timing margins of all data, address, command, and control line signals.

Analysis - Signal Integrity - Automatic DDR Bus Analysis menu enables user to analyze
address/command/control group nets of DDR BUS in a one operation step.

Under DDR Bus Nets section③, using net class information, all automatically extracted DQS, DQ, CLK,
ADD, CMD, and CTRL nets are listed. Users should review the extracted net names and make corrections
as needed by adding nets, removing nets, or changing the net types. For DQS and DQ nets correct byte
lane numbers must be assigned.

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When multiple device models are available④, users need to select device models of output and input
pins of DQS+, DQS-, DQ, CLK, and ADD/CMD/CTRL nets, respectively. For the DQS and DQ nets, the
device models must be selected separately for the data write and data read modes.

Prior to running analysis, users can set the analysis control parameters which are identical to those of
Data Line Analysis and ADD/CMD/CTRL Line Analysis.
Users can bring in a DDR spec to use by selecting Import DDR Spec menu⑤.
Users can also generate a new DDR spec in DDR Spec Generator after selecting DDR Spec Generator
menu⑥.

Finally users can select the simulation mode among Typical, Fast, and Slow⑦. The simulation mode is
applied to all device models used for the analysis.

The automatic DDR bus analysis models with analysis results are saved in DDR directory under
Signal_Integrity of the PCB design project folder by selecting Save menu⑧. The model name
plus.DBM is used for the file name.

Upon selecting Run Analysis menu⑨, data line analysis and ADD/CMD/CTRL line analysis models are
automatically constructed and analyses are automatically performed on all of the models.

Show Timing Report menu⑩ allows users to review the timing margins of all DDR bus signals. For
each signal, the report shows the data type, net name, output pin, input pin, timing margin Pass/Fail,
setup margin, and hold margin. The data can be exported to an MS Excel file by selecting Export to
Excel menu.

The analysis results are automatically saved. The eye diagrams and timing margins of individual data
line analysis and ADD/CMD/CTRL line analysis models can be viewed in Data Line Analysis and
ADD/CMD/CTRL Line Analysis, respectively.

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[Lab.19 Exploring the “Automatic DDR Bus Analysis”]

• Select Analysis - Signal Integrity - Automatic DDR Bus Analysis menu. The Select Automatic
DDR Analysis Model dialog will be displayed.

• Click Add to create new model. The Automatic DDR Bus Analysis dialog will be displayed.
• Enter Model name as DDR3_1066_AC175_60ohm_ODT120, then click Reset button.

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Under DDR Bus Nets section, all automatically extracted DQS, DQ, CLK, ADD, CMD, and CTRL nets are
listed.

• Review the extracted net names.


• At the Device Model section, select output and input models as follows:

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• Click Import DDR Spec button at Analysis Parameter section, then select DDR3.dls for a DDR Spec
name field.

• Select Data Rate to 1066 for DDR3_1066_AC175 Operation and click OK button.

• Set the DQS Jitter value to 50 at Analysis Parameter section.


• Set the Clock Jitter value to 50 at Analysis Parameter section.
• Set the ADD/CMD/CTRL signal mode value to 1T at Analysis Parameter section.

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• Set the AC threshold(dvi_AC) enable at Analysis Parameter section.
• Click Save button to save this setup.

• The Automatic DDR Bus Analysis is ready then click Run Analysis button at the bottom of the
Automatic DDR Bus Analysis dialog.

Data line analysis and ADD/CMD/CTRL line analysis models are automatically constructed, and analyses are
automatically performed on all the models.
The analysis results are automatically saved. The eye diagrams and timing margins of individual data line
analysis and ADD/CMD/CTRL line analysis models can be viewed in Data Line Analysis and ADD/CMD/CTRL
Line Analysis, respectively.

The automatic DDR bus analysis models with analysis results are saved in DDR directory under
Signal_Integrity of the PCB design project folder. The DDR3_1066_AC175_60ohm_ODT120.DBM is used for the
file name.

When the automatic DDR Bus analysis is started, all of action button at the bottom of Automatic DDR Bus
Analysis dialog will be invisible, and progress bar will be appeared, and electromagnetic simulation will
extract the SPICE model for the selected net. And the excitation source signal will be applied to the net
which is specified by the assigned pin model’s operating characteristics. When the simulation is done, all of
action buttons at the bottom of Automatic DDR Bus Analysis dialog will be visible again.

• Click Show Timing Report button. The setup and hold margin of all signal will be displayed.

• Click Close to close DDR Analysis Report dialog.


• Click Close to close Automatic DDR Bus Analysis dialog.

<Review data line analysis result>


• Select Analysis - Signal Integrity - Data Line Analysis to review data bus analysis result.
• Select DDR3_1066_AC175_60ohm_ODT120_B0_R1 model, click Copy button.

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• Click Display Eye Diagram button to review Eye Diagram.

• Click Close to close Waveform Viewer dialog.

• Click Show Report button to review timing margin.

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• Click Close to close this dialog.

<Review Address, Command and Control line analysis result>

• Select Analysis - Signal Integrity - ADD/CMD/CNTR Line Analysis to review ADD/CMD/CTRL


line analysis result.
• Select DDR3_1066_AC175_60ohm_ODT120_ADDRESS1 model, click Copy button.

• Click Display Eye Diagram button to review Eye Diagram. And close it.

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• Click Show Report button to review timing margin. And close it.

• Close ADD/CMD/CTRL Line Analysis dialog.

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6. Crosstalk Analysis

Analysis - Signal Integrity - Crosstalk Analysis enables user to execute waveform and network
parameter analysis for the selected net(s) considering the coupling effects by neighboring nets.
When user specifies the victim net, the strongly coupled nets are automatically screened through
whole PCB layers. And the coupling parasitic will be extracted and configured as SPICE circuit for the
crosstalk analysis.

When select Analysis - Signal Integrity - Crosstalk Analysis menu, Crosstalk Analysis dialog
will be invoked as below.

① Find Coupling: Extract and display the detailed coupling information e.g. coupled length,
coupled net numbers and mostly coupled net to each net.
② Coupled Length: This column shows the total coupled length of each net to other neighboring
nets which meet the coupling check criteria displayed at the boxed area.
③ Number of Coupled: Shows the coupled nets number.
④ Most Coupled Net:
⑤ Net Name:
⑥ Display/Analyze Coupling: For user selected net, shows more detailed coupling information
and provides options and menus for crosstalk analysis.

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[Lab.20 Exploring the “Crosstalk Analysis”]

• Click Properties -Layer Stack: By selecting this menu, Layer Stack dialog will be displayed.
• Execute Import menu. By clicking this menu, Explorer dialog will be displayed.
• Find the directory path in which your own stack-up files in navigation tree section. (C:\temp\Altair-
PollEx\PollExSI\Stackup)
• Select StandardStackup2.udls for 6-layer stack-up.
• Close Layer Stack dialog.

• Select Analysis - Signal Integrity - Crosstalk Analysis menu.


• Click Find Coupling button.
• Select MCU_AA3 net.

• Click Display/Analyze Coupling button. The Display/Analyze Coupling dialog will be displayed.

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① The region shows the names of all coupled nets. Total 5 aggressor nets listed together with the
victim MCU_AA3 net because Max number of adjacent traces to couple is set to 5.
② Display region shows detailed coupling topologies.
③ Toggled as V will be displayed at region ②.
④ Aggressor Net: Many fractal segments can be listed at this column coupled to the victim
MCU_AA3 net.
⑤ Separation: Aggressor net MCU_AA0 can have different separations to the victim depending
on the locations.
⑥ Victim Layer: With ⑦, two columns show where the coupled traces, one is victim and the other
is aggressor, are routed.
⑧ Coupled Length: Shows the coupled length for the fractal coupled segments.
⑨ Analysis Type: Waveform and Network Parameter extraction are possible.
⑩ Active Driver Pins & Device Models:
⑪ Run Analysis: Click this button to start crosstalk analysis.

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• Click Active Driver Pins & Device Models button then its dialog is invoked. User can define
whether the excitation signal is applied or not for each aggressor nets here.
• By changing the Active Driver Pin assignment as None for MCU_AA3 net. The Net will not be
excited. Just do the crosstalk analysis with all aggressor nets are excited. User can change the Input
Signal shapes and Device Models by clicking these for the desired net.
• Just click OK.

• Click Run Analysis button to start crosstalk analysis. Waveform Viewer will be invoked.
• Click V at ① will hide all waveforms.
• Then click ②, for just display the victim net’s coupled noise waveform. (Near End Crosstalk)
• Using the measure function, you can find the peak to peak coupled NEXT noise level reaching to
about 0.52V and FEXT noise level reaching to about 0.58V.

• Close all Crosstalk Analysis related dialogs

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[Lab.21 Reducing the crosstalk noise by shorten the
distance between the signal and ground plane]

There are many way to reduce crosstalk noise.


1) Reduce coupling length
2) Increase the separation between the two nets
3) Reduce the height of the signal line and reference plane.
We will apply method 3).

• Click Properties - Layer Stack menu and change the thickness of the dielectric layer to 0.065
between Top and Inner_Layer_2.
• Change the thickness of the dielectric layer to 0.065 between Bot and Inner_Layer_5.
• Click OK to close Layer Stackup dialog.

• Please select Analysis - Signal Integrity - Crosstalk Analysis menu.


• Click Find Coupling
• Select MCU_AA3
• Click Display/Analyze Coupling
• Click Run Analysis button at Display/Analyze Coupling dialog.
• Please select MCU_AA3 net to be displayed at the Waveform Viewer.

User can verify that having closely placed ground plane to the signal plane can reduce the crosstalk noise
dramatically. Using the measure function, you can find the peak to peak coupled NEXT noise level reduced
to about 0.37V and FEXT noise level reduced to about 0.44V.

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• Close Waveform Viewer related dialogs

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[Lab.22 Extracting “Network Parameter” among coupled
net groups]

When you change the Analysis Type at Display/Analyze Coupling dialog from Waveform to Network
Parameter, User can have S, Y and Z-parameters for all ports which are assigned at the driving and
receiving ends of all victim and aggressor nets.

• Click Network Parameter as Analysis Type.


• Click Run Analysis.

Explore the extracted S, Y, Z parameters in Graphical or table format. Touchstone file can be exported also.
• Close all Crosstalk Analysis related dialogs.

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7. Net Topology Analysis

Net topology analysis is used to construct or view the detailed physical topology of nets schematically
and run signal integrity analysis on the interconnect network model. At a pre-route stage, it can be
effectively used for playing with various topology options to find routing constraints for critical nets.
At a post-route stage, it is useful for viewing interconnect topology of the nets with signal integrity
problems and finding the best way of fixing the problems by changing the net topology.

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[Lab.23 Single-ended topology analysis (Type 5)]

• Click Analysis - Signal Integrity - Net Topology Analysis - Net Topology Analyzer menu.

• Click File - New or icon and give Model Name as Clock and click OK.
• Select Type 5 which has parallel ac termination and click Close.

• Click R2 & delete, click C2 & delete, click GND & delete. (All 3 elements below will be removed.)

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• Click C1 & Delete.


• Click VCC, Assign the Voltage from 1.8 V to 0.75V as a termination voltage and click Apply.

The topology should be looked like below. Until the driver (U1-1), receiver (U2-1) and signal line model are
not ready to be simulated. Then the next step should be followed assigning the electrical properties for
these.

• Click both U1-1 (①) and click Part Name selection button(②) below.

• Select DDR3 component named as IC-NXP4330 and select L2 pin named as ACK as below. By
assigning this pin model, the Driver will excite the net with the AC and DC electrical properties of
DDR3_DQS_60ohm model described in IBIS file. Click OK.

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• Click single line TML model and select one of the trace model from ① below. The selected 1_0.08”
model denotes that it is routed at 1 layer having 0.08 (mm) width. The thickness of the trace and
distance to the ground will follow the stack up information.
• Put 10 as the length for it. Click Apply.

• Click R1 (①) as below, You can select certain resister from the activated PCB system at ②, or just
put the value as 50ohm at ③ and click Apply.

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• Like as assigning the Driver (U1-B1) above, please select and assign Receiver (U2-1) as below and
click Apply.
• Part Name is H5TQ4G63AFR, Pin Name is J7. Click OK.

• Click Analysis - Network Analysis menu or just click F5 function key, then the Topology
Network Analysis dialog will be displayed for detailed simulation setup.
• Click Device Models button on the CLOCK net, then select the DDR3_DQS_30ohm in Model
menu. And Click OK button.

• Click Analyze button. The simulated waveform will be shown as below.

• If you want to save and use the waveform later, please save it with File - Save As menu.

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• Close all dialog are related to topology analyzer.

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[Lab.24 Topology analysis from selected Netlist]

• Click Property - Layer Stack: By selecting this menu, Layer Stack Manager dialog will be
displayed.
• Execute Import menu. By clicking this menu, Explorer dialog will be displayed.
• Find the directory path in which your own stack-up files in navigation tree section. (C:\temp\Altair-
PollEx\PollExSI\Stackup)
• Select StandardStackup.udls for 6-layer stack-up.

• Click Analysis - Signal Integrity - Net Topology Analysis - Select Net for Analysis menu.

• Select MCU_AA4 net from the Topology Select Net and click Analyze button. The Net Topology
Analyzer dialog will be invoked.

Please acknowledge that the lengths from driver to two receivers are slightly different among others. It
means that all receivers are taking signals from driver through different electrical length. Therefore, there
might be significant differences for the receiving signals between two DDRs.

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• Click Analysis - Network Analysis or just click F5 key for the waveform analysis setup.
• Click Waveform as Analysis Type.
• Change the Pulse Period from 2 (ns) to 1.0 (ns) and extend both Simulation time (ns) and
Signaling time (ns) as 5.
• Click Device Models button on the MCU_AA4 net, then select the DDR3_DQS_30ohm model in
U1. And Click OK button.

• Click Analyze to start simulation.

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• Click Save As at the Waveform Viewer and save the waveform name as MCU_AA4_org.spw.
• Close Waveform Viewer.

This original net waveform will be compared later with modified topology.

Please note that this activated PCB system is not an actual working system but is designed partially only
for demonstration purpose. Therefore, the timing information and signal levels might not adaptive to the
technical standard related to the devices employed in this demo PCB.

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Pulse period defined as 1.0ns (1000MHz) will be excited to the MCU_AA4 net during the signaling and
simulation time set for 5 (ns). Then total 5 pulse sequences are shown at Waveform Viewer above. As
you can see receiving signals are showing big deviation.

Generally, the lengths for the net segments those are close to the driver should be longer than the other
ones routed further away from the driver. And the total path (electrical) length to each receiver from the
driver should be the same.

Therefore, at next trial, we will adjust net lengths as same for all and route it over the same layer. Vias will
be removed and the parallel termination will be applied at the first T-branch location for expecting better
receiving signals.

• Click Close to close Waveform Viewer dialog.


• Click Close to close Topology Network Analysis dialog.

At Net Topology Analyzer dialog:

• Change Length 3rd branch for U205 models to 10.537.

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• Click Resistor icon and type 50 as resistance value. Click OK. Then mouse cursor will be
come up with resistor symbol. Move mouse cursor over 1st net trace connected to the driver, push
and hold the Ctrl key and click the 1st net.
• Click Esc key to exit the resistor insertion mode. Then the resistor will be added at parallel to the
clicked 1st net elements as below.

• Select Edit – Add - Power or click icon, enable you to add DC voltage source to the net. Please
put 0.75 V as below and click OK. And move cursor over to the R1 and click it.

[Final Topology for Analysis]

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• Click Analysis - Network Analysis or F5 key, change the Pulse Period from 2 (ns) to 1.0 (ns)
and extend both Simulation time (ns) and Signaling time (ns) as 5.
• Click Device Models button on the MCU_AA4 net, then select the DDR3_DQS_30ohm model in
U1. And Click OK button.
• Click Analyze to start simulation.

• Please click Open and select the original net waveform MCU_AA4_org.spw saved before. When
you are asked Remove currently displayed waveform?, click No. User can compare two nets.

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SECTION 4: Radiated Emission Analysis


In this section, user can learn how to do radiated emission Analysis for the PCB system.
Radiated Emission Analysis is running transient circuit simulation on the network model for user-specified
simulation time in order to obtain time-domain or frequency-domain current waveforms at the input and
output of each segment. The simulated results can be exported in XML file format which can be used for
subsequent EM analysis systems like Feko.

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[Lab.25 Exploring the “Radiated Emission Analysis”]

<Run Radiated Emission Analysis>


• Execute Analysis-Radiated Emission menu, Radiated Emission Analysis dialog will be open.

① Model Name: Assign Model Name.


② Select Net: Nets for analysis can be selected over Select Net dialog.
③ Remove: Remove selected net from Net List Window.
④ Active Driver Pin: User can specify the active driver pin among the connected pin to this net.
The other pins will be assigned as receiver pin(s) automatically.
⑤ Initial State: User can specify the initial value of input waveform.
⑥ Pulse Period(ns): User can adjust the driver’s operating frequency/speed by changing this
value. The default pulse period of input signal is automatically obtained from the operating
frequency information of the net.
⑦ Input Signal: Upon clicking this button, the Input Signal dialog will be open. User can review
and change the detailed parameters which can specify the actual shape of the input signal e.g.
TD (Time Delay), TR (Rise Time), TR (Fall Time), PW (Pulse Width) and pulse train.
⑧ Device Models: Upon clicking this button, the Device Model List dialog will be open. User can
review default device models selected for the output and inputs pins. For the selected active
driver, actual driver model can be selectable among many different models in IBIS or Linear
device model types. User can use one of available models considering the output impedance,
driving capability measured by output current level and operating frequencies. These driver’s
characteristics lead huge impact on the simulated current waveforms.
⑨ Net List Window: All the selected nets will be displayed this window.
⑩ Simulation (sampling) time (ns): User can edit end time of the SPICE transient analysis.
⑪ Preamble Time (ns): Simulation start after this time to wait until status of internal circuit
becomes stable.

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⑫ Sampling frequency (GHz): Adjust the sampling frequency point for FFT. The sampling time
intervals is 1/(sampling frequency).
⑬ Analyze: Simulation will be started by this button.
⑭ Display Currents: Upon clicking this button, the Display Current dialog will be open. User can
review the simulation result in this dialog.
⑮ Save: Any nets have been simulated, can be saved with Model Name and easily selected again
when the PCB reactivated later by using Copy button. The saved models are listed in the left-
hand side of the dialog. Users can select the saved models anytime and copy the model to view
the model, view the analysis results, edit the model, and rerun analysis.
ⓐ Export to Feko: Upon clicking this button, the simulation result will be exported in XLM
format file. This file is saved in Radiation/Model_Name directory under the PCB design job
folder. The model name plus “.REI” is used for the file name.
ⓑ Close: Close the Radiated Emission Analysis dialog.
© Model Name region: All the saved simulation results are saved in this region.

• Click Select Net button, the Select Net dialog will be open. Multi select MCU_ACK, MCU_AA0,
MCU_AA1 and click OK to close this dialog.

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• At the Radiated Emission Analysis dialog, type in DDR_Address at Model Name.
• Click Analyze button to start Radiated Emission Analysis. Then analysis starts, when the
analyze is over, the message is displayed as follows.

• Click OK to close this message.

• Click Save button to save the result. You will find that this model name is listed into left window.

<Review the analysis result of selected nets>


• Click Display Currents button to review the result, the Display Currents dialog will be open. User
can review the current waveform of selected net or selected segment in time domain and frequency
domain.

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① Waveform Type: User can select waveform type. The time-domain or frequency-domain.
② Currents At: User can view net result or segment result. When All segments option is selected,
the results of all selected nets in the Net Name Tree(④) region are displayed. When selecting
the Selected segments option, user have to click the desired segment on the screen to select it.
③ Display: Display result in pre-selected format.
④ Net name tree region: All nets belong to simulated model are listed here.

• Select MCU_ACK and MCU_ACKB nets in the Net Name field.


• Select the Waveform Type as Time-domain which will show the time-domain current waveform.
• Select the Currents At as All segments which will show the current waveform of selected nets.

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• Click Display button, then the Radiated Emission Time-Domain Viewer dialog will be open. User
can review the current waveform of start point and end point of each segment of selected net. User
can measure the time and amplitude with View Option button.

① Current waveform display region.


② Toggle on and off to display certain desired waveform.
③ Background color can be changed.

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④ When click X and Y, measure line will be appeared crossing the cursor, moves the mouse to the
desired position to measure and click there. Then the X and Y values will be displayed near the
clicked positions.
⑤ When both X and Y is checked at this Distance menu, the distance value between two measured
points will be displayed.
⑥ Clear the measured line and value.

• Click Close button to close this dialog.

<Review the analysis result of selected segment>


• Select all nets in the Net Name field.
• Select the Waveform Type as Time-domain which will show the time-domain current waveform.
• Select the Currents At as Selected segments which will show the current waveform of selected
segments.
• Click required segment to review the result. By using Control key, user can select multiple
segments.

• Click Display button, then the Radiated Emission Time-Domain Viewer dialog will be open. User
can review the current waveform of start point and end point of selected segments.

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• Click Close button to close this dialog.

<Review the frequency-domain analysis result of selected segment>


• Select all nets in the Net Name field.
• Select the Waveform Type as Frequency-domain which will show the time-domain current
waveform.
• Select the Currents At as Selected segments which will show the current waveform of selected
segments.
• Click required segment to review the result. By using Control key, user can select multiple
segments.

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• Click Display button, then the Radiated Emission Frequency-Domain Viewer dialog will be open.
The current of net will be displayed in frequency based. The current magnitude values among ports
are initially displayed. Users can change the segment port pair selections and change the plot type
to decibel, phase, real number, or imaginary number. Also, users can choose the scale of frequency
axis or value axis. Many display and measurement options are available in the Frequency-Domain
Viewer.

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① Current waveform display region.


② Select the display type to be displayed.
③ Toggle on and off to display certain desired waveform.
④ Frequency scale: Linear or Log.
⑤ Value scale: Linear or Log.

• Click Close button to close Radiated Emission Frequency-Domain dialog.


• Click Close button to close Display Currents dialog.

<Export result in XML format>


• Click Export to Feko button to save analysis result in XML format. This file is saved in
Radiation/Model_Name directory under the PCB design job folder. The model name plus “.REI”
is used for the file name.

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