Teaching/Examination Scheme

February 9, 2021
 Unit 1:
Introduction to 80386

February 9, 2021 Dr.Sable Nilesh (ICOER) 2

 Unit 1:
Introduction to 80386

80386 DX Features and Architecture,

Programmers Model

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 Features of 80386DX
• Flexible 32-bit Microprocessor
– 8, 16, 32-Bit Data Types • Hardware Debugging Support
– 8 General Purpose 32-Bit Registers
– 32 bit ALU • 3 stage Pipeline
– 32 bit Data Bus(4 memory Bank)
– 32 bit Address Bus( 4 GB Memory)
• Multitasking
• Very Large Address Space • Operating Speed-16,20,25,33 MHz
– 4 Gigabyte Physical
– 64 Terabyte Virtual
– 4 Gigabyte Maximum Segment Size • SX (16 bit Data Bus)
DX(32 bit Data Bus)
• Integrated Memory Management Unit
– Segmentation and Paging
– 4 Levels of Protection
– Fully Compatible with 80286

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 80386DX Architecture

Memory Management Unit

Bus Control Unit

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Central Processing Unit
 80386DX Architecture

The Intel386DX consists of

• A central processing unit,
• Execution unit
• Instruction unit

• A memory management unit and

• Segmentation unit
• Paging unit

• A bus interface.
• offers address pipelining, dynamic data bus sizing, and direct Byte Enable signals for
each byte of the data bus

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 Execution Unit
• The execution unit contains the
✔ Eight 32-bit general purpose registers which are used for both address calculation, data
operations and

✔ A 64-bit barrel shifter used to speed shift, rotate, multiply, and divide operations.

• The multiply and divide logic uses a 1-bit per cycle algorithm.

• The multiply algorithm stops the iteration when the most significant bits of the multiplier are
all zero.

• This allows typical 32-bit multiplies to be executed in under one microsecond.

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 Execution Unit (Cont…)
✔ The linear address consists of two components:
• The segment base address and
• An effective address.

✔ The effective address is calculated by using four address elements:

• DISPLACEMENT: An 8-, 16- or 32-bit immediate value
• BASE: The contents of any general purpose register. It is generally used by compilers to point
to the start of the local variable area.
• INDEX: The contents of any general purpose register except for ESP. The index registers are
used to access the elements of an array, or a string of characters.
• SCALE: The index register's value can be multiplied by a scale factor, either 1, 2, 4 or 8. Scaled
index mode is especially useful for accessing arrays or structures .

EA = Base Register + (Index Register * Scaling) + Displacement.

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 Instruction and Segmentation Unit
Instruction Unit:

The instruction unit decodes the instruction opcodes and stores them in the decoded
instruction queue for immediate use by the execution unit.

Segmentation Unit:

Segmentation allows the managing of the logical address space by providing an extra
addressing component, one that allows
✔ easy code
✔ data relocatability, and
✔ efficient sharing

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 Paging Unit
• The paging mechanism operates beneath and is transparent to the segmentation
process, to allow management of the physical address space.

• Each segment is divided into one or more 4K byte pages.

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 Microprocessor

✔ Unit 2: Bus Cycles and System Architecture

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 Unit 2:
Bus Cycles and System Architecture

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 Unit 2:
Bus Cycles and System Architecture

Initialization

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 Initialization

• After a signal on the RESET pin, certain registers of 80386 are

set to predefined values.

• These values are adequate to enable execution of a bootstrap

program.

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 Processor State after RESET

• Contents of EAX depends on results power-up self test

• Self-test may be requested externally by assertion of BUSY# at the end of

RESET (EAX=0 if the 80386 passed the test, else 80386 unit is faulty)

• If self-test is not requested , EAX is undefined

• DX holds a component identifier and revision number

(DH=3, indicates 80386, DL=unique identifier of the revision level)

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 Processor State after RESET

• Control Register 0 (CR0) contains

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State of flags and other registers

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Functional Pin Diagram

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Pin Description Table

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Pin Description Table (Cont…)

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 I/O Addressing

The 80386 allows input/output to be performed in either of two

ways:
a. By means of a separate I/O address space (using specific I/O
instructions)

b. By means of memory-mapped I/O (using generalpurpose

operand manipulation instructions )

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 Separate I/O address space
(An Isolated I/O)
✔ I/O devices treated separately from memory.
• Hardware and software architecture of
8088/8086 support separate memory I/O
address space.

✔ Can be accessed as either byte-wide or word-wide.

✔ Can be treated as either independent byte-wide

I/O ports or word-wide I/O ports.

✔ Page 0:
• Certain I/O instructions can only perform
operations to ports in this part of the address
range.
• Other I/O instructions can input/output data
for ports anywhere in the address space.
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Separate I/O address space
(An Isolated I/O)

Advantages: -
✔ 1 MByte memory address space is available for use
with memory.
✔ Special instructions have been provided in the
instruction set of 8088/8086 to perform isolated
I/O input and output operations.
✔ These instructions have been tailored to maximize
I/O performance.

Disadvantages: -
✔ All input and output data transfers must take place
between AL or AX register and the I/O port

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 Memory-mapped I/O
I/O devices is placed in memory
address space of the
microcomputer.
• The memory address space is
assigned to I/O devices.

• MPU looks at the I/O port as

though it is a storage location in
memory.

• Make use of instructions that affect

data in memory rather than special
input/output instructions.

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Memory-mapped I/O
Advantages:
✔ Many more instructions and addressing
modes are available to perform I/O
operations.
✔ I/O transfers can now take place between
I/O port and internal registers other than
just AL/AX.

Disadvantages:
✔ Memory instructions tend to execute
slower than those specifically designed
for isolated I/O.
✔ Part of the memory address space is lost

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 I/O Instructions

There are two classes of I/O instruction:

1. Those that transfer a single item (byte, word, or doubleword)
located in a register.

2. Those that transfer strings of items (strings of bytes, words, or

doublewords) located in memory.

These are known as "string I/O instructions" or "block I/O

instructions".

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 Register I/O Instructions

• The I/O instructions IN and OUT

are provided to move data
between I/O ports and the EAX
(32-bit I/O), the AX (I6-bit I/O), or
AL (8-bit I/O) general registers.

• IN and OUT instructions

addresses I/O ports either
directly, with the address of one of
up to 256 port

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 Block I/O Instructions

• The block (or string) I/O instructions INS and OUTS move blocks of
data between I/O ports and memory space.

• Block I/O instructions use the DX register to specify the address of a

port in the I/O address space.

• Block I/O instructions use either SI or DI to designate the source or

destination memory address.

• For each transfer, SI or DI are automatically either incremented or

decremented as specified by the direction bit in the flags register.

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 Read and Write Cycles
• Data transfers occur as a result of bus cycles, • When pipelining is selected and the
classified as read or write cycles. Intel386 DX has a bus request pending
internally, the address and definition of the
• Two choices of address timing are next cycle is made available even before the
dynamically selectable: non-pipelined, or current bus cycle is acknowledged by
pipelined. READY#.

• After a bus idle state, the processor always • Terminating a read cycle or write cycle, like
uses non-pipelined address timing. any bus cycle, requires acknowledging the
cycle by asserting the READY# input.
• However, the NA# (Next Address) input may
be asserted to select pipelined address • Until acknowledged, the processor inserts
timing for the next bus cycle. wait states

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Non-pipelined read & write cycles

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 Non-pipelined read & write cycles

• At the end of the second bus state within the bus cycle,
READY# is sampled

• If asserted the bus cycle terminates

• Else the cycle continues another bus state (a wait state) and
READY# is sampled again at the end of that state.

• This continues indefinitely until the cycle is acknowledged by

READY# asserted.

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 Unit 2:
Bus Cycles and System Architecture

System Architecture

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 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers

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 Systems Registers
✔ EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers

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 EFLAGS

System Flags of EFLAG REGISTER

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 Systems Registers
• EFLAGS

✔ Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers

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 Memory-Management Registers
• Four registers of the 80386 locate the data structures that control segmented
memory management:
✔ GDTR Global Descriptor Table Register
✔ LDTR Local Descriptor Table Register

• These registers point to the segment descriptor tables GDT and LDT.

• IDTR Interrupt Descriptor Table Register

This register points to a table of entry points for interrupt handlers (the IDT).

• TR Task Register
This register points to the information needed by the processor to define the
current task.

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 Systems Registers
• EFLAGS

• Memory Management Registers

✔ Control Registers

• Debug Registers

• Test Registers

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Control Registers

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 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

✔ Debug Registers

• Test Registers

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 Debug Registers
• Six registers: to control debug
features
• Accessed by variants of the MOV
instruction
• debug registers are privileged
resources

Registers are:
✔ Debug Address Registers
(DRO-DR3)
✔ Debug Status Register (DR6)
✔ Debug Control Register (DR7)

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 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

✔ Test Registers

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 Test Registers
• Two test registers are provided for the purpose of testing.

• TR6 is the test command register, and TR7 is the test data
register.

• The test registers are privileged resources; in protected mode, the

MOV instructions that access them can only be executed at
privilege level 0

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 The Test Command Register (TR6)
• C: Command bit, two commands: ‘0’- write • V: The Valid bit for this TLB entry. The TLB uses the
entries into the TLB and ‘1’ perform TLB valid bit to identify entries that contain valid data.
lookups Entries of the TLB that have not been assigned values
have zero in the valid bit. All valid bits can be cleared
• Linear Address: by writing to CR3.
✔ on a TLB write command, a TLB entry is
allocated to this linear address and the rest of • D, D#: The dirty bit for/from the TLB entry
that TLB entry is set as per the values of TR7 • U, U#: The U/S bit for/from the TLB entry
& TR6 • W, W#: The R/W bit for/from the TLB entry
✔ on a TLB lookup command, the TLB is
interrogated as per this value and if one and Meaning of D, U, and W Bit Pairs
only one TLB entry matches, the rest of the
fields of TR6 & TR7 are set from the matching
TLB entry.

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 The Test Data Register (TR7)
Holds data read from or data to be written to the TLB

• Physical Address: This is the data field of the TLB. On a write to the TLB, the TLB
entry allocated to the linear address in TR6 is set to this value. On a TLB lookup, if
HT is set, the data field (physical address) from the TLB is read out to this field. If
HT is not set, this field is undefined.

• HT: For a TLB lookup, the HT bit indicates whether the lookup was a hit (HT <- 1)
or a miss (HT <- 0). For a TLB write, HT must be set to 1.

• REP: For a TLB write, selects which of four associative blocks of the TLB is to be
written. For a TLB read, if HT is set, REP reports in which of the four associative
blocks the tag was found; if HT is not set, REP is undefined.

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 Test Operations
✔ To write a TLB entry
• Move a doubleword to TR7 that contains the desired physical address, HT, and
REP values. HT must contain 1. REP must point to the associative block in
which to place the entry
• Move a doubleword to TR6 that contains the appropriate linear address, and
values for V, D, U, and W. Be sure C=0 for "write" command.

✔ To look up (read) a TLB entry

• Move a doubleword to TR6 that contains the appropriate linear address and
attributes. Be sure C = 1 for "lookup" command
• Store TR 7. If the HT bit in TR 7 indicates a hit, then the other values reveal
the TLB contents. If HT indicates a miss, then the other values in TR 7 are
indeterminate

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 Systems Instructions
1. Verification of pointer parameters: 3. Multitasking:
• ARPL ── Adjust RPL • LTR ── Load Task Register
• LAR ── Load Access Rights • STR ── Store Task Register
• LSL ── Load Segment Limit
• VERR ── Verify for Reading
• VERW ── Verify for Writing 4. Coprocessing and Multiprocessing :
• CLTS ── Clear Task-Switched Flag
2. Addressing descriptor tables: • ESC ── Escape instructions
• LLDT ── Load LDT Register • WAIT ── Wait until Coprocessor not
• SLDT ── Store LDT Register Busy
• LGDT ── Load GDT Register • LOCK ── Assert Bus-Lock Signal
• SGDT ── Store GDT Register

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 Systems Instructions
5. Input and Output : 7. Debugging :
• IN ── Input • MOV ── Move to and from debug
• OUT ── Output INS ── Input registers
String
• OUTS ── Output String 8. TLB testing :
• MOV ── Move to and from test registers

6. Interrupt control : 9. System Control:

• CLI ── Clear Interrupt-Enable Flag • SMSW ── Set MSW
• STI ── Set Interrupt-Enable Flag • LMSW ── Load MSW
• LIDT ── Load IDT Register • HLT ── Halt Processor
• SIDT ── Store IDT Register • MOV ── Move to and from control
registers

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