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RCA

The document describes various digital adder modules including a 4-bit Ripple Carry Adder (RCA) using both dataflow and gate-level implementations, as well as a 5-input Carry-Save Adder (CSA) in both dataflow and behavioral styles. It also includes a Carry Lookahead Adder (CLA) with dataflow and behavioral implementations. Each module is defined with input and output specifications, along with the logic for calculating sums and carries.
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0% found this document useful (0 votes)
4 views

RCA

The document describes various digital adder modules including a 4-bit Ripple Carry Adder (RCA) using both dataflow and gate-level implementations, as well as a 5-input Carry-Save Adder (CSA) in both dataflow and behavioral styles. It also includes a Carry Lookahead Adder (CLA) with dataflow and behavioral implementations. Each module is defined with input and output specifications, along with the logic for calculating sums and carries.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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RCA

Dataflow
module RCA_4bit_Dataflow(

input [3:0] A, B,

input Cin,

output [3:0] Sum,

output Cout

);

wire c1, c2, c3; // Internal carry wires

// Sum and Carry expressions using dataflow

assign Sum[0] = A[0] ^ B[0] ^ Cin;

assign c1 = (A[0] & B[0]) | ((A[0] ^ B[0]) & Cin);

assign Sum[1] = A[1] ^ B[1] ^ c1;

assign c2 = (A[1] & B[1]) | ((A[1] ^ B[1]) & c1);

assign Sum[2] = A[2] ^ B[2] ^ c2;

assign c3 = (A[2] & B[2]) | ((A[2] ^ B[2]) & c2);

assign Sum[3] = A[3] ^ B[3] ^ c3;

assign Cout = (A[3] & B[3]) | ((A[3] ^ B[3]) & c3);

endmodule

Gate-level

module FullAdder(

input A, B, Cin,

output Sum, Cout

);

wire w1, w2, w3;


xor (w1, A, B);

xor (Sum, w1, Cin);

and (w2, A, B);

and (w3, w1, Cin);

or (Cout, w2, w3);

endmodule

module RCA_4bit(

input [3:0] A, B,

input Cin,

output [3:0] Sum,

output Cout

);

wire c1, c2, c3;

FullAdder FA0 (A[0], B[0], Cin, Sum[0], c1);

FullAdder FA1 (A[1], B[1], c1, Sum[1], c2);

FullAdder FA2 (A[2], B[2], c2, Sum[2], c3);

FullAdder FA3 (A[3], B[3], c3, Sum[3], Cout);

Endmodule
CSA- 5 operands

Dataflow

module csa_5x4bit(

input [3:0] A, B, C, D, E, // 4-bit input operands

output [6:0] Sum // 7-bit output sum

);

wire [3:0] Sum1, Sum2, Sum3; // Sum outputs of each CSA stage

wire [3:0] Carry1, Carry2, Carry3; // Carry outputs of each CSA stage

wire [6:0] FinalSum; // Final sum output

wire [6:0] FinalCarry; // Final carry output

// Stage 1: Add A, B, C using CSA

assign Sum1 = A ^ B ^ C;

assign Carry1 = (A & B) | (B & C) | (A & C);

// Stage 2: Add Sum1, Carry1, D using CSA

assign Sum2 = Sum1 ^ Carry1 ^ D;

assign Carry2 = (Sum1 & Carry1) | (Carry1 & D) | (Sum1 & D);

// Stage 3: Add Sum2, Carry2, E using CSA

assign Sum3 = Sum2 ^ Carry2 ^ E;

assign Carry3 = (Sum2 & Carry2) | (Carry2 & E) | (Sum2 & E);

// Final addition using Ripple Carry Adder

assign FinalSum = {Carry3, Sum3};

assign FinalCarry = {1'b0, Carry3, 2'b00}; // Align carry bits for final addition

// Final sum output

assign Sum = FinalSum + FinalCarry;

endmodule
Behavioral

module csa_5x4bit_behavioral(

input [3:0] A, B, C, D, E, // 4-bit input operands

output reg [6:0] Sum // 7-bit output sum

);

reg [3:0] Sum1, Sum2, Sum3;

reg [3:0] Carry1, Carry2, Carry3;

reg [6:0] FinalSum, FinalCarry;

always @(*) begin

// Stage 1: Add A, B, C using CSA

Sum1 = A ^ B ^ C;

Carry1 = (A & B) | (B & C) | (A & C);

// Stage 2: Add Sum1, Carry1, D using CSA

Sum2 = Sum1 ^ Carry1 ^ D;

Carry2 = (Sum1 & Carry1) | (Carry1 & D) | (Sum1 & D);

// Stage 3: Add Sum2, Carry2, E using CSA

Sum3 = Sum2 ^ Carry2 ^ E;

Carry3 = (Sum2 & Carry2) | (Carry2 & E) | (Sum2 & E);

// Final addition using Ripple Carry Adder

FinalSum = {Carry3, Sum3};

FinalCarry = {1'b0, Carry3, 2'b00}; // Align carry bits for final addition

// Final sum output

Sum = FinalSum + FinalCarry;

end

endmodule
CLA

Dataflow

module cla_dataflow(input [3:0] a, b, input cin, output [3:0] sum, output cout);

wire [3:0] g, p, c;

assign g = a & b; // Generate

assign p = a ^ b; // Propagate

assign c[0] = cin;

assign c[1] = g[0] | (p[0] & cin);

assign c[2] = g[1] | (p[1] & c[1]);

assign c[3] = g[2] | (p[2] & c[2]);

assign cout = g[3] | (p[3] & c[3]);

assign sum = p ^ c;

endmodule

Behavioral

module cla_behavioral(input [3:0] a, b, input cin, output reg [3:0] sum, output reg cout);

reg [3:0] g, p, c;

always @(*) begin

g = a & b;

p = a ^ b;

c[0] = cin;

c[1] = g[0] | (p[0] & cin);

c[2] = g[1] | (p[1] & c[1]);

c[3] = g[2] | (p[2] & c[2]);

cout = g[3] | (p[3] & c[3]);


sum = p ^ c;

end

endmodule

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