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LEC_02 ~ Microprocessor Architecture Classification.pdf_s=1

Microprocessors can be classified based on Instruction Set Architecture (ISA) complexity into Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). CISC architectures utilize complex instructions that can perform multiple operations but require more clock cycles, while RISC architectures use simplified instructions that allow for faster execution but may require more instructions overall. Additionally, microprocessors can be categorized by memory interface architectures, such as von Neumann and Harvard architectures.

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3 views

LEC_02 ~ Microprocessor Architecture Classification.pdf_s=1

Microprocessors can be classified based on Instruction Set Architecture (ISA) complexity into Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). CISC architectures utilize complex instructions that can perform multiple operations but require more clock cycles, while RISC architectures use simplified instructions that allow for faster execution but may require more instructions overall. Additionally, microprocessors can be categorized by memory interface architectures, such as von Neumann and Harvard architectures.

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Chester rampas
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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MICROPROCESSOR ARCHITECTURE CLASSIFICATION

COMPLEXITY-BASED ISA CLASSIFICATION

• Using the ISA complexity as the classification measure, we can categorize the microprocessors into two
groups:
COMPLEX INSTRUCTION SET COMPUTERS (CISC)

• The key features of the CISC architecture :


• In early computers where the processors were much faster than available memories. Fetching an
instruction from memory used to become the performance bottleneck.
• A single complex instruction can perform many operations. However, complex instructions require
many processor clock cycles to complete and most of the instructions can access memory.
• A program involves a relatively small number of complex instructions, which can provide high code
density. In addition, many instruction types with varying instruction length are available supporting
different addressing modes while requiring fewer and specialized registers.
• Complexity is embedded in the processor hardware, making the compilation tools design simpler.
REDUCED INSTRUCTION SET COMPUTERS (RISC)

• The main features of the RISC architecture:


• For those scenarios where the processor speeds match that of memories. And the simplified
instructions used by this architecture.
• Load and Store instructions are provided for memory read and write operations. The other
instructions cannot access memory directly.
• The simplified instructions make it possible to execute an instruction in a single processor clock cycle;
still, some of the instructions may require more than one clock cycle for its execution completion.
• A task when run on a RISC computer requires a relatively larger number of simplified instructions and
results in low code density; but fewer memory addressing modes resulting in reduced complexity.
• The simplicity in the hardware architecture in RISC is complemented by the increased complexity in
the generation of assembly code by the tools (compiler) or by the programmer.
SPARC
INSTRUCTION OPERAND-BASED ISA CLASSIFICATION

• Memory – Memory
• Register – Memory
• Register – Register (e.g. ARM and MIPS)
MICROPROCESSOR ARCHITECTURE CLASSIFICATION
MEMORY INTERFACE-BASED ARCHITECTURE CLASSIFICATION
Von Neumann architecture
• Mostly, microprocessors are implemented using
von Neumann architecture…
MEMORY INTERFACE-BASED ARCHITECTURE CLASSIFICATION

Harvard architecture
• …microcontrollers use Harvard architecture.
PERFORMANCE COMPARISON

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