(Advanced) Computer Architechture

Prof. Dr. Hasan Hüseyin BALIK

(4th Week)
Outline
2. The computer system
—A Top-Level View of Computer Function and
Interconnection
—Operating System Support
+
2.2 Operating System Support
2.2 Outline
• Operating System Overview
• Scheduling
• Memory Management
• Intel x86 Memory Management
• ARM Memory Management
Computer Hardware and Software Structure

Application programs
Application
programming interface
Application Libraries/utilities Software
binary interface
Operating system
I nstruction Set
Architecture
Execution hardware

M emory
System interconnect
translation Hardware
(bus)

I /O devices
M ain
and
memory
networking
Operating System (OS) Services
• The most important system program
• Masks the details of the hardware from the programmer and
provides the programmer with a convenient interface for using
the system
• The OS typically provides services in the following areas:
– Program creation
– Program execution
– Access to I/O devices
– Controlled access to files
– System access
– Error detection and response
– Accounting
 Interfaces
• Key interfaces in a typical computer system:
Instruction set Application Application
architecture binary programming
(ISA) interface (ABI) interface (API)
Gives a program access to
the hardware resources
Defines the machine Defines a standard for and services available in a
language instructions that binary portability across system through the user
a computer can follow programs ISA supplemented with
high-level language (HLL)
library calls

Defines the system call

Using an API enables
interface to the operating
application software to be
Boundary between system and the hardware
ported easily to other
hardware and software resources and services
systems that support the
available in a system
same API
through the user ISA
Operating System as Resource Manager

• A computer is a set of resources for the movement,

storage, and processing of data and for the control of
these functions
– The OS is responsible for managing these resources

• The OS as a control mechanism is unusual in two

respects:
– The OS functions in the same way as ordinary computer software – it is a
program executed by the processor
– The OS frequently relinquishes control and must depend on the processor to
allow it to regain control
The Operating System as Resource Manager
Computer System
I /O Devices
M emory
Operating I /O Controller Printers,
System keyboards,
Software digital camera,
I /O Controller etc.

Programs
and Data

I /O Controller

Processor Processor

Storage
OS
Programs

Data
Types of Operating Systems
• Interactive system
– The user/programmer interacts directly with the computer to
request the execution of a job or to perform a transaction
– User may, depending on the nature of the application,
communicate with the computer during the execution of the job

• Batch system
– Opposite of interactive
– The user’s program is batched together with programs from other
users and submitted by a computer operator
– After the program is completed results are printed out for the user
Early Systems
• From the late 1940s to the mid-1950s the programmer
interacted directly with the computer hardware – there was no
OS
– Processors were run from a console consisting of display lights, toggle switches,
some form of input device and a printer

• Problems:
– Scheduling
▪ Sign-up sheets were used to reserve processor time
– This could result in wasted computer idle time if the user finished early
– If problems occurred the user could be forced to stop before resolving the
problem
– Setup time
▪ A single program could involve
– Loading the compiler plus the source program into memory
– Saving the compiled program
– Loading and linking together the object program and common functions
Memory Layout for a Resident Monitor
I nterrupt
Processing
Device
Drivers
M onitor
Job
Sequencing
Control Language
I nterpreter
Boundary

User
Program
Area
From the View of the Processor . . .
• Processor executes instructions from the portion of main memory containing the monitor
– These instructions cause the next job to be read in another portion of main memory
– The processor executes the instruction in the user’s program until it encounters an ending or error condition
– Either event causes the processor to fetch its next instruction from the monitor program

• The monitor handles setup and scheduling

– A batch of jobs is queued up and executed as rapidly as possible with no idle time

• Job control language (JCL)

– Special type of programming language used to provide instructions to the monitor

• Example:
– $JOB
– $FTN **Each FORTRAN instruction and each item of
data is on a separate punched card or a separate record on
– ... Some Fortran instructions tape. In addition to FORTRAN and data lines, the job includes
job control instructions, which are
– $LOAD
denoted by the beginning “$”.
– $RUN
– ... Some data
– $END

• Monitor, or batch OS, is simply a computer program

– It relies on the ability of the processor to fetch instructions from various portions of main memory in order to seize and relinquish
control alternately
Desirable Hardware Features
• Memory protection • Privileged instructions
– User program must not alter – Can only be executed by the
the memory area containing monitor
the monitor
– The processor hardware – If the processor encounters
should detect an error and such an instruction while
transfer control to the monitor executing a user program an
– The monitor aborts the job, error interrupt occurs
prints an error message, and – I/O instructions are
loads the next job privileged so the monitor
retains control of all I/O
devices
• Timer
– Used to prevent a job from • Interrupts
monopolizing the system – Gives the OS more flexibility
– If the timer expires an in relinquishing control to and
interrupt occurs and control regaining control from user
returns to monitor programs
System Utilization Example
Multiprogramming Example
Program A Run Wait Run Wait

Time
(a) Uniprogramming

Program A Run Wait Run Wait

Program B Wait Run Wait Run Wait

Run Run Run Run

Combined Wait Wait
A B A B
Time
(b) M ultiprogramming with two programs

Program A Run Wait Run Wait

Program B Wait Run Wait Run Wait

Program C Wait Run Wait Run Wait

Run Run Run Run Run Run

Combined Wait Wait
A B C A B C
Time
(c) M ultiprogramming with three programs

Figure 9.5 M ultiprogramming Example

Sample Program Execution Attributes

JOB1 JOB2 JOB3

Type of job Heavy compute Heavy I/O Heavy I/O

Duration (min) 5 15 10
Memory required (M) 50 100 80

Need disk? No No Yes

Need terminal? No Yes No

Need printer? No No Yes

Effects of Multiprogramming on Resource
Utilization
Uniprogramming Multiprogramming
Processor use (%) 20 40

Memory use (%) 33 67

Disk use (%) 33 67

Printer use (%) 33 67

Elapsed time (min) 30 15

Throughput rate (jobs/hr) 6 12

Mean response time (min) 18 10

Utilization Histograms
100% 100%

CPU CPU
0% 0%
100% 100%

M emory M emory
0% 0%
100% 100%

Disk Disk
0% 0%
100% 100%

Terminal Terminal
0% 0%
100% 100%

Printer Printer
0% 0%

Job History Job History JOB1

JOB1 JOB2 JOB3
JOB2
0 5 10 15 20 25 30
minutes JOB3

time 0 5 10 15
minutes
time
(a) Uniprogramming (b) M ultiprogramming

Figure 9.6 Utilization Histograms

Time Sharing Systems

• Used when the user interacts directly with the computer

• Processor’s time is shared among multiple users
• Multiple users simultaneously access the system through
terminals, with the OS interleaving the execution of each
user program in a short burst or quantum of computation
• Example:
– If there are n users actively requesting service at one time, each user will
only see on the average 1/n of the effective computer speed
Batch Multiprogramming versus Time
Sharing

Batch Multiprogramming Time Sharing

Principal objective Maximize processor use Minimize response time
Source of directives to Job control language commands Commands entered at the
operating system provided with the job terminal
Types of Scheduling
Long-term scheduling The decision to add to the pool of processes to be executed.
The decision to add to the number of processes that are partially or
Medium-term scheduling
fully in main memory.
The decision as to which available process will be executed by the
Short-term scheduling
processor.
The decision as to which process’s pending I/O request shall be han-
I/O scheduling
dled by an available I/O device.
 Long Term Scheduling

In some systems a newly

created process begins in a
Determines which Once submitted, a job
swapped-out condition, in
programs are submitted for becomes a process for the
which case it is added to a
processing short term scheduler
queue for the medium-term
scheduler

Time-sharing system Batch system

• A process request is generated when a
• Newly submitted jobs are routed to disk and
user attempts to connect to the system
held in a batch queue
• OS will accept all authorized comers until
• The long-term scheduler creates processes
the system is saturated
from the queue when it can
• At that point a connection request is met
with a message indicating that the system
is full and to try again later
Medium-Term Scheduling
and Short-Term Scheduling
Medium-Term Short-Term

• Part of the swapping • Also known as the

function dispatcher
• Executes frequently and
• Swapping-in decision is makes the fine-grained
based on the need to manage decision of which job to
the degree of execute next
multiprogramming

• Swapping-in decision will

consider the memory
requirements of the swapped-
out processes
Five-State Process Model

Dispatch
Admit Release
New Ready Running Exit
Timeout

Event
Occurs Event
Wait

Blocked

Figure 9.7 Five-State Process M odel

Process Control Block
I dentifier
State

Priority
Program counter
M emory pointers

Context data

I /O status
information

Accounting
information
Scheduling Example
Operating system Operating system Operating system
In
control

Service handler Service handler Service handler

Scheduler Scheduler Scheduler
I nterrupt handler I nterrupt handler I nterrupt handler

A A A
"Running" "Waiting" "Waiting"

In
control

B B B
"Ready" "Ready" "Running"

In
control

Other partitions Other partitions Other partitions

(a) (b) (c)

Figure 9.9 Scheduling Example

Key Elements of an Operating System for
Multiprogramming
Operating System
Service Call Service
from Process Call
Handler (code)

Long- Short- I /O
I nterrupt
Term Term Queues
from Process I nterrupt
Queue Queue
I nterrupt Handler (code)
from I /O
Short-Term
Scheduler
(code)

Pass Control
to Process
Queuing Diagram Representation of
Processor Scheduling
Long-term Short-term
queue queue
Admit End
Processor

I /O 1
Occurs
I /O 1 Queue

I /O 2
Occurs
I /O 2 Queue

I /O n
Occurs
I /O n Queue
The Use of Swapping
M ain
Disk storage memory
Operating
system

Long-term Completed jobs

queue and user sessions

(a) Simple job scheduling

Disk storage

M ain
memory
I ntermediate
queue Operating
system

Completed jobs
Long-term
and user sessions
queue

(b) Swapping
Example of Fixed Partitioning of a 64-Mbyte
Memory
Operating System Operating System
8M 8M

2M
8M 4M

6M
8M

8M

8M

8M

8M

12 M
8M

8M

16 M

8M

(a) Equal-size partitions (b) Unequal-size partitions

Figure 9.13 Example of Fixed Partitioning of a 64-M byte M emory

The Effect of Dynamic Partitioning
Operating Operating Operating Operating
System 8M System System System

Process 1 20M Process 1 20M Process 1 20M

Logical address
- expressed as a location relative
56M Process 2 14M Process 2 14M
to the beginning of the program

Physical address 36M

- an actual location in main Process 3 18M
22M
memory
4M
Base address
- current starting location of the (a) (b) (c) (d)
process

Operating Operating Operating Operating

System System System System

Process 2 14M
Process 1 20M Process 1 20M 20M

6M
Process 4 8M Process 4 8M Process 4 8M
14M
6M 6M 6M

Process 3 18M Process 3 18M Process 3 18M Process 3 18M

4M 4M 4M 4M

(e) (f) (g) (h)

Allocation of Free Frames
M ain M ain
memory memory

Page 1
Process A 13 Process A 13
of A
Page 0 Page 0
Page 1 Page 1 Page 2
14 14
Page 2 Page 2 of A
Page 3 Page 3
Page 3
15 15
of A

In In
16 16
use use
Free frame list Free frame list
13 In 20 In
17 17
14 use use
15 Process A
page table Page 0
18 18 18
of A
20 18
In 13 In
19 19
use use
14
15
20 20

(a) Before (b) After

Logical and Physical Addresses
M ain
M emory

Page 1
13
of A

page relative address frame relative address Page 2

number within page number within frame
14
of A

Logical Physical Page 3

Address 1 30 Address 13 30 15
of A

16

18
17
13
14 Page 0
18
of A
15

Process A
Page Table
Virtual Memory
Demand Paging
• Each page of a process is brought in only when it is needed

• Principle of locality
– When working with a large process execution may be confined to a small section
of a program (subroutine)
– It is better use of memory to load in just a few pages
– If the program references data or branches to an instruction on a page not in main
memory, a page fault is triggered which tells the OS to bring in the desired page

• Advantages:
– More processes can be maintained in memory
– Time is saved because unused pages are not swapped in and out of memory

• Disadvantages:
– When one page is brought in, another page must be thrown out (page
replacement)
– If a page is thrown out just before it is about to be used the OS will have to go get
the page again
– Thrashing
▪ When the processor spends most of its time swapping pages rather than
executing instructions
Inverted Page Table Structure
Virtual address
n bits
Page # Offset
Control
n bits bits
Process
hash m bits Page # ID Chain
function 0

2m – 1 Frame # Offset
m bits
I nverted page table Real address
(one entry for each
physical memory frame)
Operation of Paging and Translation
Lookaside Buffer (TLB)
Start
Return to
faulted instruction
CPU checks the TLB

Page table Yes

entry in
TLB?
No

Access Page Table

Page fault
handling routine

OS instructs CPU Page

No in main
to read the page
from disk memory?

Yes
CPU activates
I /O hardware Update TLB

Page transferred
from disk to CPU generates
main memory physical address

M emory Yes
full?

No Perform page
replacement

Page tables
updated
Translation Lookaside Buffer and Cache
Operation
TLB Operation
Virtual Address

Page # Offset
TLB
TLB miss
TLB
hit Cache Operation

Real Address

+ Tag Remainder Hit Value

Cache
M iss

M ain
M emory

Page Table
Value

Figure 9.19 Translation Lookaside Buffer and Cache Operation

Segmentation 1/2
• Usually visible to the
programmer • Advantages:
• Provided as a convenience – Simplifies the handling of
for organizing programs and growing data structures
data and as a means for – Allows programs to be
associating privilege and altered and recompiled
protection attributes with independently without
instructions and data requiring that an entire set
of programs be re-linked
• Allows the programmer to
and re-loaded
view memory as consisting of
– Lends itself to sharing
multiple address spaces or
among processes
segments
– Lends itself to protection
Intel x86 and Memory Management
• Includes hardware for both segmentation and paging
• Unsegmented unpaged memory
– Virtual address is the same as the physical address
– Useful in low-complexity, high performance controller applications

• Unsegmented paged memory

– Memory is viewed as a paged linear address space
– Protection and management of memory is done via paging
– Favored by some operating systems

• Segmented unpaged memory

– Memory is viewed as a collection of logical address spaces
– Affords protection down to the level of a single byte
– Guarantees that the translation table needed is on-chip when the segment is in memory
– Results in predictable access times

• Segmented paged memory

– Segmentation is used to define logical memory partitions subject to access control, and
paging is used to manage the allocation of memory within the partitions
– Operating systems such as UNIX System V favor this view
Segmentation 2/2
• Each virtual address consists of a 16-bit segment
reference and a 32-bit offset
– Two bits of segment reference deal with the protection mechanism
– 14 bits specify segment

• Unsegmented virtual memory is 232 = 4Gbytes

• Segmented virtual memory is 246=64 terabytes (Tbytes)
• Physical address space employs a 32-bit address for a
maximum of 4 Gbytes
• Virtual address space is divided into two parts
– One-half is global, shared by all processors
– The remainder is local and is distinct for each process
Segment Protection
• Associated with each segment are two forms of protection:
– Privilege level
– Access attribute
• There are four privilege levels
– Most protected (level 0)
– Least protected (level 3)
• Privilege level associated with a data segment is its “classification”
• Privilege level associated with a program segment is its “clearance”
• An executing program may only access data segments for which its
clearance level is lower than or equal to the privilege level of the
data segment

• The privilege mechanism also limits the use of certain instructions

Intel x86 Memory Management Formats
15 3 2 1 0
I ndex T RPL
I
TI — Table indicator
RPL — Requestor privilege level
(a) Segment selector

31 22 21 12 11 0

Directory Table Offset

(b) Linear address

31 24 23 22 20 19 16 15 14 13 12 11 8 7 0
D A Segment
Base 31...24 G / L V limit P DPL S Type Base 23...16
B L 19...16

Base 15...0 Segment limit 15...0

AVL — Available for use by system software L — 64-bit code segment

Base — Segment base address (64-bit mode only)
D/B — Default operation size P — Segment present
DPL — Descriptor privilege size Type — Segment type
G — Granularity S — Descriptor type
(c) Segment descriptor (segment table entry)

31 12 11 9 76 5 4 3 2 1 0
P P P U R
Page frame address 31...12 AVL S 0 A C
D
W SWP
T
AVL — Available for systems programmer use PWT — Write through = reserved
P — Page size US — User/supervisor
A — Accessed RW — Read-write
PCD — Cache disable P — Present
(d) Page directory entry

31 12 11 9 76 5 4 3 2 1 0
P P U R
Page frame address 31...12 AVL D A C W SWP
D T
D — Dirty
(e) Page table entry
x86 Memory Management Parameters (1 of 2)
Segment Descriptor (Segment Table Entry)
Base
Defines the starting address of the segment within the 4-Gbyte linear address space.
D/B bit
In a code segment, this is the D bit and indicates whether operands and addressing modes are 16 or 32 bits.
Descriptor Privilege Level (DPL)
Specifies the privilege level of the segment referred to by this segment descriptor.
Granularity bit (G)
Indicates whether the Limit field is to be interpreted in units by one byte or 4 Kbytes.
Limit
Defines the size of the segment. The processor interprets the limit field in one of two ways, depending on
the granularity bit: in units of one byte, up to a segment size limit of 1 Mbyte, or in units of 4 Kbytes, up to a
segment size limit of 4 Gbytes.
S bit
Determines whether a given segment is a system segment or a code or data segment.
Segment Present bit (P)
Used for nonpaged systems. It indicates whether the segment is present in main memory. For paged
systems, this bit is always set to 1.
Type
Distinguishes between various kinds of segments and indicates the access attributes.
(Table is on page 323 in the textbook)
x86 Memory Management Parameters (2 of 2)
Page Directory Entry and Page Table Entry
Accessed bit (A)
This bit is set to 1 by the processor in both levels of page tables when a read or write operation to the
corresponding page occurs.
Dirty bit (D)
This bit is set to 1 by the processor when a write operation to the corresponding page occurs.
Page Frame Address
Provides the physical address of the page in memory if the present bit is set. Since page frames are aligned
on 4K boundaries, the bottom 12 bits are 0, and only the top 20 bits are included in the entry. In a page direc-
tory, the address is that of a page table.
Page Cache Disable bit (PCD)
Indicates whether data from page may be cached.
Page Size bit (PS)
Indicates whether page size is 4 Kbyte or 4 Mbyte.
Page Write Through bit (PWT)
Indicates whether write-through or write- back caching policy will be used for data in the corresponding page.
Present bit (P)
Indicates whether the page table or page is in main memory.
Read/Write bit (RW)
For user-level pages, indicates whether the page is read- only access or read/write access for user- level
programs.
User/Supervisor bit (US)
Indicates whether the page is available only to the operating system (supervisor level) or is available to
both operating system and applications (user level).
(Table is on page 323 in the textbook)
Paging
• Segmentation may be disabled
– In which case linear address space is used

• Two level page table lookup

– First, page directory
▪ 1024 entries max
▪ Splits 4 Gbyte linear memory into 1024 page groups of 4 Mbyte
▪ Each page table has 1024 entries corresponding to 4 Kbyte pages
▪ Can use one page directory for all processes, one per process or
mixture
▪ Page directory for current process always in memory
– Use TLB holding 32 page table entries
– Two page sizes available, 4k or 4M
Intel x86 Memory Address Translation
Mechanisms
ARM Memory System Overview
M emory M anagement Unit (M M U)

Access bits, Virtual Physical

Access
domain Virtual address memory address
control TLB
hardware
Access bits, translation
domain hardware

Abort Physical address

M ain
Control Physical memory
bits address

ARM
core Cache
Virtual and Cache
address write line fetch
buffer hardware
Virtual Memory Address
Translation • Sections and supersections are supported
to allow mapping of a large region of
memory while using only a single entry in
• The ARM supports memory access based
the TLB
on either sections or pages
• The translation table held in main memory
• Supersections (optional)
has two levels:
– Consist of 16-MB blocks of main
memory
• Level 1 table
• Sections – Holds level 1 descriptors that contain
the base address and translation
– Consist of 1-MB blocks of main
properties for a Section and
memory
Supersection
• Large pages – And translation properties and pointers
– Consist of 64-kB blocks of main to a level 2 table for a large page or a
memory small page

• Small pages • Level 2 table

– Consist of 4-kB blocks of main – Holds level 2 descriptors that contain
memory the base address and translation
properties for a Small page or a Large
page
– Requires 1kB of memory
ARM Virtual Memory Address
Translation for Small Pages
ARM Memory-Management Formats
ARM Memory-Management Parameters
Access Permission (AP), Access Permission Extension (APX)
These bits control access to the corresponding memory region. If an access is made to an area of memory
without the required permissions, a Permission Fault is raised.
Bufferable (B) bit
Determines, with the TEX bits, how the write buffer is used for cacheable memory.
Cacheable (C) bit
Determines whether this memory region can be mapped through the cache.
Domain
Collection of memory regions. Access control can be applied on the basis of domain.
not Global (nG)
Determines whether the translation should be marked as global (0), or process specific (1).
Shared (S)
Determines whether the translation is for not-shared (0), or shared (1) memory.
SBZ
Should be zero.
Type Extension (TEX)
These bits, together with the B and C bits, control accesses to the caches, how the write buffer is used, and
if the memory region is shareable and therefore must be kept coherent.
Execute Never (XN)
Determines whether the region is executable (0) or not executable (1).
(Table is on page 329 in the textbook)
Access Control
• The AP access control bits in each table entry control access to a region of memory by a
given process
• A region of memory can be designated as:
– No access
– Read only
– Read-write

• The region can be privileged access only, reserved for use by the OS and not by
applications

• ARM employs the concept of a domain:

– Collection of sections and/or pages that have particular access permissions
– The ARM architecture supports 16 domains
– Allows multiple processes to use the same translation tables while maintaining some protection from
each other

• Two kinds of domain access are supported:

– Clients
▪ Users of domains that must observe the access permissions of the individual sections and/or pages
that make up that domain
– Managers
▪ Control the behavior of the domain and bypass the access permissions for table entries in that domain