3.5.Memory Swapping
3.5.Memory Swapping
Endadul Hoque
Acknowledgement
Focus:
• How to support many concurrently-running large
address spaces?
• How to leverage a larger (slower) device to
transparently provide the illusion of a large virtual
address space?
Memory Hierarchy
• Require an additional level in the memory hierarchy.
• OS needs a place to stash away portions of address space that
currently aren’t in great demand.
• Such a location should have more capacity, but it is generally slower
• In modern systems, this role is usually served by a hard disk drive
Registers
speed
size
Cache
Memory Hierarchy
in modern system
Main Memory
Value Meaning
1 page is present in physical memory
0 The page is not in memory but rather on disk.
The Page Fault
• Accessing page that is not in physical memory.
– If a page is not present and has been swapped to disk,
the OS needs to swap the page into memory
in order to service the page fault.
• Using a page-fault handler
What if (physical) memory is full ?
• The OS like to swap out pages to make room for
the new pages the OS is about to bring in.
– The process of picking a page to kick out, or replace is
known as page-replacement policy
Page Fault Control Flow
• PTE’s PFN is used to hold the disk address of the page in swap space.
NP
Page Frame
Page Frame
Page Frame
Virtual Address
Page Fault Control Flow
• PTE’s PFN is used to hold the disk address of the page in swap space.
NP
P
Page Frame
Virtual Address
Page Fault Control Flow – Hardware
1: VPN = (VirtualAddress & VPN_MASK) >> SHIFT
2: (Success, TlbEntry) = TLB_Lookup(VPN)
3: if (Success == True) // TLB Hit
4: if (CanAccess(TlbEntry.ProtectBits) == True)
5: Offset = VirtualAddress & OFFSET_MASK
6: PhysAddr = (TlbEntry.PFN << SHIFT) | Offset
7: Register = AccessMemory(PhysAddr)
8: else RaiseException(PROTECTION_FAULT)
Page Fault Control Flow – Hardware
1: VPN = (VirtualAddress & VPN_MASK) >> SHIFT
9: else // TLB Miss
2: (Success, TlbEntry) = TLB_Lookup(VPN)
10: PTEAddr = PTBR + (VPN * sizeof(PTE))
3: if (Success == True) // TLB Hit
11: PTE = AccessMemory(PTEAddr)
4: if (CanAccess(TlbEntry.ProtectBits) == True)
12: if (PTE.Valid == False)
5: Offset = VirtualAddress & OFFSET_MASK
13: RaiseException(SEGMENTATION_FAULT)
6: PhysAddr = (TlbEntry.PFN << SHIFT) | Offset
14: else
7: Register = AccessMemory(PhysAddr)
15: if (CanAccess(PTE.ProtectBits) == False)
8: else RaiseException(PROTECTION_FAULT)
16: RaiseException(PROTECTION_FAULT)
17: else if (PTE.Present == True)
18: // assuming hardware-managed TLB
19: TLB_Insert(VPN, PTE.PFN, PTE.ProtectBits)
20: RetryInstruction()
21: else if (PTE.Present == False)
22: RaiseException(PAGE_FAULT)
Page Fault Control Flow – Software
Page fault handler – Pseudocode
1: PFN = FindFreePhysicalPage()
2: if (PFN == -1) // no free page found
3: PFN = EvictPage() // run replacement algorithm
4: DiskRead(PTE.DiskAddr, PFN) // sleep (waiting for I/O)
5: PTE.present = True // update page table with present
6: PTE.PFN = PFN // bit and translation (PFN)
7: RetryInstruction() // retry instruction
𝐴𝑀𝐴𝑇 = 𝑇𝑀 + (𝑃𝑀𝑖𝑠𝑠 ∗ 𝑇𝐷 )
Argument Meaning
𝑇𝑀 The cost of accessing memory
𝑇𝐷 The cost of accessing disk
𝑃𝑀𝑖𝑠𝑠 The probability of not finding the data in the cache(a miss)
The Optimal Replacement Policy
• Leads to the fewest number of misses overall
– Replaces the page that will be accessed furthest in the
future
– Resulting in the fewest-possible cache misses
• Serve only as a comparison point, to know how
close we are to a perfect solution
Tracing the Optimal Policy
Reference Row
0 1 2 0 1 3 0 3 1 2 1 Physical memory
holds 3 frames
𝐻𝑖𝑡𝑠
Hit rate is = 𝟓𝟒. 𝟔% Future is not known.
𝐻𝑖𝑡𝑠+𝑀𝑖𝑠𝑠𝑒𝑠
A Simple Policy: FIFO
• Pages were placed in a queue when they enter the
system.
• When a replacement occurs, the page at the tail of the
queue (the “First-in” pages) is evicted.
– It is simple to implement but can’t determine the importance of
pages (in terms of reducing memory access time)
Tracing the FIFO Policy
Reference Row
0 1 2 0 1 3 0 3 1 2 1 Physical memory
holds 3 frames
Access Hit/Miss? Evict Resulting Cache State
0 Miss 0
1 Miss 0,1
2 Miss 0,1,2
0 Hit 0,1,2
1 Hit 0,1,2
3 Miss 0 1,2,3
0 Miss 1 2,3,0
3 Hit 2,3,0
1 Miss 2 3,0,1
2 Miss 3 0,1,2
1 Hit 0,1,2
Reference Row
1 2 3 4 1 2 5 1 2 3 4 5
14
12
Page Fault Count
10
0
1 2 3 4 5 6 7
Page Frame Count
Another Simple Policy: Random
• Picks a random page to replace under memory pressure.
– It doesn’t really try to be too intelligent in picking which pages
to evict.
– Random does depends entirely upon how lucky Random gets in
its choice.
Access Hit/Miss? Evict Resulting Cache State
0 Miss 0
1 Miss 0,1
Physical memory
2 Miss 0,1,2
holds 3 frames
0 Hit 0,1,2
Reference 1 Hit 0,1,2
Row
0 1 2 0 1 3 0 3 1 2 1 3 Miss 0 1,2,3
0 Miss 1 2,3,0
3 Hit 2,3,0
1 Miss 3 2,0,1
2 Hit 2,0,1
1 Hit 2,0,1
Performance of Random Policy
• Sometimes, Random is as good as optimal, achieving 6
hits on the example trace.
50
40
Frequency
30
20
10
0
1 2 3 4 5 6
Number of Hits
Historical
Meaning Algorithms
Information
The more recently a page has been accessed,
recency LRU
the more likely it will be accessed again
If a page has been accessed many times, it
frequency should not be replaced as it clearly has some LFU
value
Using History : LRU
• Replaces the least-recently-used page.
Reference Row
Physical memory
0 1 2 0 1 3 0 3 1 2 1
holds 3 frames
• Clock Algorithm
– All pages of the system arranges in a circular list.
– A clock hand points to some particular page to begin with.
Clock Algorithm
When a page fault occurs, the page the hand is pointing to is inspected.
The action taken depends on the Use bit
A
H B
Use bit Action
G C 0 Evict the page
1 Clear Use bit and advance hand
F D
E
The Clock page replacement algorithm